JP4520177B2 - Signal processing circuit - Google Patents

Description

  The present invention relates to a signal processing circuit that performs discrete-time signal processing at high speed, and more particularly to a signal processing circuit that includes a switched capacitor circuit to improve the signal processing accuracy.

In this type of signal processing circuit, it is desired to reduce non-linearity caused by switching elements such as MOS transistors when performing discrete-time signal processing. As a conventional signal processing circuit designed to reduce this, a conventional circuit as shown in FIG. 8 (see Non-Patent Document 1) or a conventional circuit as shown in FIG. 9 (see Non-Patent Document 2) is known. It has been.
The conventional circuit shown in FIG. 8 includes a switched capacitor circuit 1 and source follower circuits 2 and 3 connected to the input and output sides of the switched capacitor circuit 1, respectively.

  The switched capacitor circuit 1 includes a complementary switch including an N-type MOS transistor M1 and a P-type MOS transistor M2, and a capacitor C1. A clock signal CLK is supplied to the gates of the MOS transistors M1 and M2. The source follower circuit 2 includes a MOS transistor M3 and a constant current source I1. Further, the source follower circuit 3 includes a MOS transistor M4 and a constant current source I2.

In the conventional circuit of FIG. 8 having such a configuration, when the clock CLK is at the H level, the MOS transistor M1 is turned on and at the same time the MOS transistor M2 is turned off. When the clock CLK is at the L level, the MOS transistor M1 is turned off and at the same time M2 turns on.
Here, the output impedance of the source follower circuit 2 is Zout, the input impedance of the source follower 3 is Zin, the impedance of the source follower circuit 2 side viewed from the MOS transistor M1 is Z1, and the impedance of the source follower circuit 3 side viewed from the MOS transistor M1 is The frequency of Z2 and the clock CLK is defined as f1.

Then, since conditions Zout = 0 and Zin = ∞ of an ideal source follower circuit, impedances Z1 and Z2 are expressed by the following equations.
Z1 = Zout≈0 (1)
Z2 = (1 / (2 × π × f1 × C1)) // Zin≈1 / (2 × π × f1 × C1) (2)

Under this condition, the MOS transistor M1 is turned off, and of the charge Q accumulated in the MOS transistor M1, Q / 2 is discharged to the source follower circuit 2 side, and the remaining Q / 2 is transferred to the source follower circuit 3 side. It shall be exhaled. In this case, the potential V1 on the source follower circuit 2 side where the impedance Z1 is zero does not change, but the potential V2 on the source follower circuit 3 side where the impedance Z2 is high is expressed by the following equation.
V2 = (Q / 2) / C1 = Q / (2 × 1) (3)

  This change in potential is the cause of nonlinearity. Therefore, in the conventional circuit of FIG. 8, the gate of the MOS transistor M2 that is complementary to the gate of the MOS transistor M1 is short-circuited, and a common-phase clock is applied to the terminal thereof, so that the MOS transistor M2 The discharged Q / 2 charge is absorbed, or the charge absorbed by the MOS transistor M1 is discharged to the MOS transistor M2, thereby canceling the above effect.

The conventional circuit shown in FIG. 9 includes a switched capacitor circuit 11 and a current mirror circuit 12 formed with the switched capacitor circuit 11 interposed therebetween.
The switched capacitor circuit 11 includes N-type MOS transistors M11 and M12 and a capacitor C1. The gates of both MOS transistors M11 and M12 are supplied with clock signals CLK and / CLK having a complementary relationship as shown in FIG.

The current mirror circuit 12 includes an N-type MOS transistor M13 and an N-type MOS transistor M14. Constant current sources I11 and I12 for supplying an appropriate bias current are connected in series to the MOS transistors M13 and M14, respectively.
9, the MOS transistors M11 and M12 are turned on when the clocks CLK and / CLK are at the H level, and the MOS transistors M11 and M12 are turned off when the clocks CLK and / CLK are at the L level. .

Here, the impedance on the MOS transistor M13 side viewed from the MOS transistor M11 is defined as Z1, the impedance on the MOS transistor M14 side viewed from the MOS transistor M11 is defined as Z2, and the frequencies of the clocks CLK and / CLK are defined as f2.
In this case, assuming that the MOS transistors M13 and M14 are ideal MOS transistors, the impedance viewed from the gate of the MOS transistor M13 is 1 / gm due to diode connection, and that of the MOS transistor M14 is ∞. Here, gm is the mutual conductance of the MOS transistor M13.

As a result, the impedances Z1 and Z2 are as follows.
Z1 = 1 / gm (4)
Z2 = 1 / (2 × π × f2 × C1) (5)
Under this condition, the MOS transistor M11 is turned off, and of the charge Q accumulated in the MOS transistor M11, Q / 2 is discharged to the MOS transistor M13 side, and the remaining Q / 2 is discharged to the MOS transistor M14 side. As a result, the voltage fluctuations at the terminals 13 and 14 depend only on the impedances Z1 and Z2 shown in the equations (4) and (5).

Assuming that the MOS transistors M13 and M14 are used in the saturation region, the mutual conductance gm is about 10 ⁻³ to 10 ⁻⁵ , the frequency f2 is about 10 ³ to 10 ⁶ , and the capacitance value C1 of the capacitor C1 is C1 <10. ^{About -12} .
Accordingly, it can be understood that the voltage fluctuation of the MOS transistor M13 can be ignored as compared with the voltage fluctuation of the MOS transistor M11. For this reason, the charge of Q / 2 supplied from the MOS transistor M11 can be canceled by turning on / off the MOS transistor M12 having half the size of the MOS transistor M11 with a complementary clock.

As can be seen from the above description, the conventional circuits of FIGS. 8 and 9 are effective when the left and right impedances seen from the switches inserted in series in the signal path are greatly different.
As a circuit for supplying clocks CLK and / CLK to the conventional circuit of FIG. 9, a non-overlapping clock generation circuit as shown in FIG. 11 is known (see Non-Patent Document 3).

  The clock generation circuit shown in FIG. 11 includes NOR circuits 21 and 22 and inverters 31 to 39. A clock signal A having a duty of 50% is input to the NOR circuit 21 and the inverter 31. Further, the output of the NOR circuit 21 is taken out as an output CLKB through the inverters 32 to 35 and input to the NOR circuit 22. Further, the output of the NOR circuit 22 is taken out as an output CLKA via the inverters 36 to 39 and input to the NOR circuit 21.

With such a configuration, the output of the NOR circuit 22 has a period of H level corresponding to the delay difference between the propagation delay of the clock signal A by the NOR circuit 21 and the inverters 32 to 35 and the propagation delay of the inverter 31 of the clock signal A. Shorter. Therefore, the clock CLKA is shorter in the H level period than in the L level period.
The same thing occurs in the system of the NOR circuit 22 and the inverters 36 to 39, and the clock CLKB is shorter in the H level period than in the L level period.

Therefore, in the clock generation circuit of FIG. 11, the clock CLKA and the clock CLKB are in the feedback system, the phase relationship between them is uniquely determined, and their H level periods do not overlap.
E. Yeung, M.C. A. Horowitz “A 2.4 Gb / s / pin Simulaneous Bidirectional Parallel Link with Per-Pin Skew Compensation” JSSC, U.S. Pat. S. A. 2000, November, Vol. 35, no. 11, pp 1619-1628. H. C. Yang, T .; S. Fiez, D.C. J. et al. Allshot, “Current-Feedthrough Effect and Cancellation Techniques in Switched-Current Circuits” ISCAS, U.S. Pat. S. A. May 1990 pp 3186-3188. R. Gregorian, G.M. C. Temes, “Analog MOS Integrated Circuits for Signal Processing,” U.S. Pat. S. A. Wiley-Interscience, 1986, pp 469-470.

However, the conventional circuits of FIGS. 8 and 9 cannot sufficiently reduce the influence of non-linearity caused by the switching element as described above when processing discrete time signals at high speed (especially in the GHz band). There is a problem that high-accuracy analog signal processing cannot be performed.
Therefore, in view of the above points, an object of the present invention is to reduce the influence of nonlinearity caused by a switching element and perform high-precision analog signal processing when processing discrete-time signals at high speed. An object of the present invention is to provide a signal processing circuit which can be used.

In order to solve the above-described problems and achieve the object of the present invention, the present inventor has made a balance between the impedance of a switching element and the input / output impedance of an amplifier located before and after the switching element, which has not been considered in the past. Focusing attention, the inventors have found that the influence of electric charges emitted from the switching element contributes to the low impedance side at low frequencies.
And based on this knowledge, each invention which concerns on Claims 1-5 is completed, and the structure of each invention is as follows.

That is, the invention according to claim 1 is the first transistor and the capacitor for switching connected in series between the input terminal and the common connection portion, the second transistor disposed at both ends of the first transistor, and A voltage at a common connection between the first transistor and the capacitor, and a first source follower circuit that includes a third transistor and a fourth transistor connected to the input terminal and supplies a signal to the input terminal. A second source follower circuit including a fifth transistor that performs a predetermined operation as the second and third transistors, the drain and source of the second and third transistors are connected in common, and the common connection portion is connected to the first transistor. Connected to the source and drain of the transistor, respectively, and the gate of the first transistor and the second Beauty third to the gates of both transistors are made a binary signal of opposite phase to supply respectively.

According to a second aspect of the present invention, there are provided a first transistor and a capacitor for switching connected in series between the input terminal and the common connection portion, a second transistor and a third transistor respectively disposed at both ends of the first transistor. A second transistor connected to the input terminal; a fifth transistor connected to the output terminal; and a second transistor connected to the output terminal. And the third transistor has a drain and a source connected in common, and each common connection is connected to the source and the drain of the first transistor, respectively, the gate of the first transistor, and the second and third transistors Two-phase binary signals are supplied to both gates of the transistors, and the fourth transistor is supplied. Data and said fifth transistor so as to form a current mirror circuit.
According to a third aspect of the present invention, in the signal processing circuit according to the first or second aspect, the second transistor and the third transistor are emitted from the first transistor when the first transistor is off. Each charge is absorbed.

According to a fourth aspect of the present invention, the signal processing circuit according to any one of the first to third aspects further includes a clock generation circuit that generates the binary signal, and the clock generation circuit includes a power supply line. A sixth transistor and a seventh transistor connected in series between the power supply line and the common connection line, and an eighth transistor and a ninth transistor connected in series between the power supply line and the common connection line. The clock signal is input to the gate of the sixth transistor, the inverted signal of the clock signal is input to the gate of the eighth transistor, and the first connection is made from the common connection between the sixth transistor and the seventh transistor. It takes out an output signal, and supplies the first output signal to a gate of said ninth transistor and said eighth transistor From the common connection of the ninth transistor is taken out of the second output signal and the second output signal is supplied to the gate of the seventh transistor.
According to a fifth aspect of the present invention, in the signal processing circuit according to any one of the first to fourth aspects, the frequency of the binary signal is in the range of 100 [MHz] to 10 [GHz].

  According to the present invention having such a configuration, when high-speed discrete-time signal processing is performed, it is possible to reduce the influence of non-linearity due to the switching element and perform high-precision analog signal processing. .

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 shows the configuration of the signal processing circuit according to the first embodiment of the present invention.
As shown in FIG. 1, the signal processing circuit according to the first embodiment includes a switched capacitor circuit 41 and source follower circuits 42 and 43 connected to the input side and the output side of the switched capacitor circuit 41, respectively. ing.
The switched capacitor circuit 41 includes an N-type MOS transistor M41, which is a switching element, a capacitor (capacitance element) C1, and N-type MOS transistors M42 and M43. The MOS transistor M41 and the capacitor C1 are connected in series between the output terminal 44 of the source follower circuit 42 and the common connection line (common connection portion) 45.

  In addition, auxiliary MOS transistors M42 and M43 are arranged at both ends of the MOS transistor M41 symmetrically with the MOS transistor M41 interposed therebetween. Both the MOS transistors M42 and M43 absorb the electric charges discharged from the source side and the drain side of the MOS transistor M41 when the MOS transistor M41 is turned off, respectively.

  More specifically, the source of the MOS transistor M41 is connected to the output terminal 44 of the source follower circuit 42, the drain thereof is connected to one end of the capacitor C1, and the MOS transistor M45 constituting the source follower circuit 43 is connected. Connected to the gate. The source and drain of the MOS transistor M42 are connected in common, and the common connection is connected to the source of the MOS transistor M41. Further, the source and drain of the MOS transistor M43 are commonly connected, and the common connection portion is connected to the drain of the MOS transistor M41. The other end of the capacitor C1 is connected to the common connection line 45.

  The MOS transistor M41 is supplied with a clock CLK at its gate and is controlled to be turned on / off. The gates of the MOS transistors M42 and M43 are connected in common, and the same clock / CLK is supplied to each gate. That is, the gate of the MOS transistor M41 and the gates of the MOS transistors M42 and M43 are, for example, binary signals having opposite phases as shown in FIG. 10, that is, binary complementary signals having opposite polarities, respectively. The clock CLK and the clock / CLK are supplied.

  As shown in FIG. 1, the source follower circuit 42 includes an N-type MOS transistor M44 and a constant current source I41 which is a load of the MOS transistor M44. That is, the MOS transistor M44 and the constant current source I41 are connected in series between the power supply line 46 and the common connection line 45. An input signal is supplied to the gate of the MOS transistor M44, and an output signal is extracted from the source.

  As shown in FIG. 1, the source follower circuit 43 is composed of a P-type MOS transistor M45 and a constant current source I42 serving as a load of the MOS transistor M45. That is, the constant current source I41 and the MOS transistor M44 are connected in series between the power supply line 46 and the common connection line 45. The voltage across the capacitor C1 is input to the gate of the MOS transistor M45, and the output signal is extracted from the source.

Next, the usefulness of the MOS transistors M42 and M43 of the first embodiment having such a configuration will be specifically described using numerical examples in the high frequency region.
Here, the impedance of the input / output source follower circuits 42 and 43 in the high frequency region is higher than that in the low frequency region.
(1) The output impedance Zout of the source follower circuit 42 is increased.
(2) The input impedance Zin of the source follower circuit 43 is lowered.
(3) In order to shorten the settling time, the ON resistance Ron of the MOS transistor M41 and the total capacitance Cs of the input capacitance and the parasitic capacitance of the MOS transistor M45 are reduced.
The settling time ts and the on-resistance Ron are related by the following equation.
ts∝ (Ron × Cs) (6)

(4) Since the nonlinear effect is reduced from the MOS transistor M41, it is desired to make the MOS transistor M41 small. This is equivalent to increasing the on-resistance Ron.
(5) The capacitance Cs occupies the main part of the input capacitance of the source follower circuit 43. This places a limit on the minimum value of the capacitor Cs.

A numerical example of the impedances Zin, Zout, and Ron in the high frequency region when these five conditions are taken into consideration is as follows.
(Numerical example in the high frequency range)
Now, the maximum value of the capacitance value Cs allowed when the sampling clock frequency is f = 1 [GHz] and the on-resistance of the MOS transistor M41 is Ron = 100 [Ω] is expressed by the following equation.
Cs = (1 / (2 × π × Ron × f)) × (1/2) × (1/3) = 2.652 × 10 ⁻¹³ (7)
(1/2): What can be used for settling is a period when the clock is at the H level, that is, a half cycle of the clock.
(1/3): If the time is three times as long as the time constant, the signal can be settled by 99% or more.

When the input impedance Zin of the source follower circuit 43 is obtained with reference to the equation (7), the following equation is obtained.
Zin = (1 / (2 × π × 10 ⁹ × 2.652 × 10 ⁻¹³ )) = 600 (8)
Further, the output impedance Zout of the source follower circuit 42 is about several tens to several hundreds [Ω]. The on-resistance Ron of the MOS transistor M41 is 100 [Ω] on the assumption as described above, and is inversely proportional to the size of the MOS transistor M41.

As can be seen from the above, the values of the impedances Zin, Zout, and Ron in the high-frequency region are each in the vicinity of 100 [Ω].
In the conventional circuit shown in FIG. 8, the main cause of nonlinearity is the interaction between the discharge / absorption of charges associated with the switching operation (on / off operation) of the switching element and the impedance level of the circuit element connected to the switching element. It is.

However, in the first embodiment, as shown in FIG. 1, the MOS transistors M42 and M43 are symmetrically arranged on the left and right sides of the MOS transistor M41 so as to minimize charge redistribution and impedance variation due to the switching operation. Therefore, a high nonlinear removal effect can be obtained.
Here, if the relationship between the input impedance Zin of the source follower circuit 43 and the output impedance Zout of the source follower circuit 42 is Zin = Zout, the transistor sizes of the MOS transistor M42 and the MOS transistor M43 may be the same.

  In an actual circuit, the performance can be optimized by adjusting the sizes of the MOS transistors M42 and M43 with respect to a slight difference between the input impedance Zin and the output impedance Zout. When the effect of this optimization was verified with Spice (electronic circuit simulator), a third-order distortion reduction effect of 10 dB was recognized.

(Second Embodiment)
Next, a signal processing circuit according to a second embodiment of the present invention will be described with reference to FIG.
As shown in FIG. 1, the signal processing circuit of the first embodiment is provided with source follower circuits 42 and 43 on the input / output side of the switched capacitor circuit 41, respectively.
However, in the signal processing circuit of the second embodiment, the input circuit provided on the input side of the switched capacitor circuit 41 is not limited to the source follower circuit, and is a general circuit including various amplifier circuits, and is output from this circuit. The switched capacitor circuit 41 receives the received signal as the input signal IN.

  Therefore, as shown in FIG. 2, the second embodiment includes an input circuit (not shown), a switched capacitor circuit 41, and a source follower circuit 43 connected to the output side of the switched capacitor circuit 41. The configuration is the same as the corresponding configuration of the first embodiment shown in FIG. 1 except for the input circuit. For this reason, the same components are denoted by the same reference numerals, and description of the configuration is omitted.

According to the second embodiment having such a configuration, the output impedance Zout of the input circuit provided on the input side of the switched capacitor circuit 41 and the input impedance Zin of the source follower circuit 43 are nonlinear by switching of the MOS transistor M41. If the sizes of the MOS transistors M42 and M43 are optimized so as to minimize the influence of the characteristics, highly accurate signal processing can be realized.
In FIG. 2, the source follower circuit 43 is connected to the output side of the switched capacitor circuit 41, but instead, a general circuit including various amplifier circuits may be connected to the output side. . In this case as well, high-accuracy signal processing can be realized as described above.

Next, a modification of the second embodiment will be described with reference to FIG.
In this modification, as shown in FIG. 3, the N-type MOS transistors M41 to M43 of the switched capacitor circuit 41 in FIG. 2 are replaced with P-type MOS transistors M51 to M53. Further, as shown in FIG. 3, the P-type MOS transistor M45 of the source follower circuit 43 of FIG. 2 is replaced with an N-type MOS transistor M55, and the constant current source I42 of FIG. 2 is replaced with a constant current source I52. It is.
According to the modified example having such a configuration, as in the second embodiment shown in FIG. 2, an effect of reducing non-linearity can be obtained, and highly accurate signal processing can be realized.

(Third embodiment)
Next, the configuration of the signal processing circuit according to the third embodiment of the present invention will be described with reference to FIG.
As shown in FIG. 4, the signal processing circuit according to the third embodiment includes a switched capacitor circuit 61 and a current mirror circuit 62 formed in a form including or including the switched capacitor circuit 61. .
The switched capacitor circuit 61 includes an N-type MOS transistor M61 that is a switching element, a capacitor C1, and N-type MOS transistors M62 and M63. The MOS transistor M61 and the capacitor C1 are connected in series between the gate of the N-type MOS transistor M64 constituting the current mirror circuit 62 and the common connection line 65.

  In addition, auxiliary MOS transistors M62 and M63 are symmetrically disposed on both ends of the MOS transistor M61 with the MOS transistor M61 interposed therebetween. Both the MOS transistors M62 and M63 absorb respective charges discharged from the source side and the drain side of the MOS transistor M61 when the MOS transistor M61 is turned off.

  More specifically, the MOS transistor M61 has its source connected to the gate of the MOS transistor M64, its drain connected to one end of the capacitor C1, and to the gate of the MOS transistor M65 constituting the current mirror circuit 62. Has been. The source and drain of the MOS transistor M62 are connected in common, and the common connection is connected to the source of the MOS transistor M61. Further, the source and the drain of the MOS transistor M63 are commonly connected, and the common connection portion is connected to the drain of the MOS transistor M61.

The MOS transistor M61 is supplied with a clock CLK at its gate and is controlled to be turned on / off. The gates of the MOS transistors M62 and M63 are connected in common, and the same clock / CLK is supplied to each gate.
That is, the clock CLK and the clock / CLK, which are binary signals having opposite phases as shown in FIG. 10, for example, are supplied to the gate of the MOS transistor M61 and the gates of the MOS transistors M62 and M63, respectively. It is like that.

As shown in FIG. 4, the current mirror circuit 62 includes an N-type MOS transistor M64 and an N-type MOS transistor M65. A constant current source I61 is connected in series to the MOS transistor M64, and the MOS transistor M66 includes A constant current source I62 is connected in series.
That is, the drain of the MOS transistor 64 is connected to the power supply line 66 via the constant current source I61. The drain and gate of the MOS transistor M64 are connected in common, and the common connection is connected to the source of the MOS transistor M61 in the switched capacitor circuit 61. Further, the source of the MOS transistor M64 is connected to the drain of the MOS transistor M65 via the common connection line 65.

The gate of the MOS transistor M65 is connected to the drain of the MOS transistor M61 of the switched capacitor circuit 61. The drain of the MOS transistor M65 is connected to the power supply line 66 through the constant current source I62, and the output is taken out from the drain.
In the third embodiment having such a configuration, the impedance on the MOS transistor M64 side viewed from the MOS transistor M61 is Z1, the impedance on the MOS transistor M65 side viewed from the MOS transistor M61 is Z2, the on-resistance Ron of the MOS transistor M61 and Then, these orders are equivalent as in the first embodiment.
Therefore, in the third embodiment, when the same effect as that of the first embodiment was verified by Spice (electronic circuit simulator), a 3 dB third-order distortion reduction effect was recognized.

Next, a modification of the third embodiment will be described with reference to FIG.
As shown in FIG. 5, this modification is obtained by replacing the N-type MOS transistors M61 to M63 of the switched capacitor circuit 61 of FIG. 4 with P-type MOS transistors M71 to M73. Further, as shown in FIG. 5, the N-type MOS transistors M64 and 65 of the current mirror circuit 62 of FIG. 4 are replaced with P-type MOS transistors M74 and M75, and the constant current sources I61 and I62 of FIG. The sources I71 and I72 are replaced.
According to the modified example having such a configuration, as in the third embodiment shown in FIG. 4, an effect of reducing nonlinearity can be obtained, and highly accurate signal processing can be realized.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described with reference to FIG.
The fourth embodiment is a clock generation circuit that generates clocks CLK and CKL2 whose phases are opposite to each other supplied to the switched capacitor circuits of the first to third embodiments, and is configured as shown in FIG. Is done.
That is, the clock generation circuit 81 includes an inverter 81, an N-type MOS transistor M81, a P-type MOS transistor M82, an N-type MOS transistor M83, and a P-type MOS transistor M84. When a clock A as shown in A) is input, complementary clocks CLKA and / CLKA as shown in FIGS. 5E and 5F are generated and output.

Here, examples of waveforms of the respective parts of the clock generation circuit 81 are as shown in (A) to (F) of FIG.
More specifically, a MOS transistor M81 and a MOS transistor M82 are connected in series, and both ends thereof are connected to a power supply line 83 and a common connection line 84, respectively. The clock A is inputted to the gate of the MOS transistor M81. The clock / CLK is taken out from the common connection portion of the MOS transistor M81 and the MOS transistor 82, and the common connection portion is connected to the gate of the MOS transistor M84 at the subsequent stage.

  The MOS transistor M83 and the MOS transistor M84 are connected in series, and both ends thereof are connected to the power supply line 83 and the common connection line 84, respectively. Further, the clock / A inverted by the inverter 82 is inputted to the gate of the MOS transistor M83. The clock CLK is taken out from the common connection portion between the MOS transistor M83 and the MOS transistor 84, and the common connection portion is connected to the gate of the preceding MOS transistor M82.

Next, the operation of the clock generation circuit having such a configuration will be described.
The inverted clock / CLKA output from the MOS transistor M81 constituting the common source amplifier is connected to the gate of the MOS transistor M84. For this reason, when the polarities of the clock / A output from the inverter 82 and the inverted clock / CLK are aligned, the complementary amplifier composed of the MOS transistor M83 and the MOS transistor M84 operates as an inverter. Further, since the delay of the inverter 82 and the delay of the MOS transistor M81 are inverting amplifiers with one stage of the transistors, both delay amounts are substantially the same.

Therefore, the complementary amplifier composed of the MOS transistor M83 and the MOS transistor M84 operates as a simple inverter.
On the other hand, in the complementary amplifier composed of the MOS transistor M81 and the MOS transistor M82, the delay between the inverter 82 and the MOS transistor M83 overlaps, and the H level period is slightly shortened. However, the output clocks CLKA, / CLKA have a duty ratio close to 50% compared to the non-overlap clock generation circuit shown in FIG.

Further, since both of the above are coupled by a positive feedback loop 86 as shown in FIG. 6, in the steady state, the duty ratio of the output clocks CLKA, / CLKA is approximately 50%. Become.
By the way, in the high-speed clock generation circuit, a slight decrease in delay time caused by the inverter 82 greatly affects the circuit operation.

On the other hand, since the conventional signal processing circuit as shown in FIG. 9 requires a non-overlap clock, it is necessary to increase the delay conversely, which increases the circuit scale and, consequently, the delay due to the increase in the number of elements. Increased variation.
However, in each of the first to third embodiments according to the present invention, since a non-overlap interval is not required, a clock signal generation circuit with a simple configuration and a small delay variation can be used as shown in FIG. Thus, highly accurate signal processing can be realized.

  The present invention can be suitably used in the field of discrete-time analog signal processing using switching elements.

1 is a circuit diagram showing a circuit configuration of a first embodiment of the present invention. It is a circuit diagram which shows the circuit structure of 2nd Embodiment of this invention. It is a circuit diagram which shows the circuit structure of the modification of the 2nd Embodiment. It is a circuit diagram which shows the circuit structure of 3rd Embodiment of this invention. It is a circuit diagram which shows the circuit structure of the modification of the 3rd Embodiment. It is a circuit diagram which shows the circuit structure of the clock generation circuit used for each of the first to third embodiments of the present invention. It is a wave form diagram showing an example of a waveform of each part at the time of operation of the clock generation circuit. It is a circuit diagram which shows the structure of the conventional signal processing circuit. It is a circuit diagram which shows the structure of the other conventional signal processing circuit. FIG. 10 is a waveform diagram showing an example of a clock supplied to the circuit of FIG. 9. It is a circuit diagram which shows an example of the non-overlap clock generation circuit which generates the clock supplied to the conventional signal processing circuit. It is a wave form diagram which shows the example of a waveform of each part of the non-overlap clock generation circuit.

Explanation of symbols

41 Switched capacitor circuit 42, 43 Source follower circuit 46, 66, 83 Power supply line 45, 65, 84 Common connection line (ground line)
62 Currant mirror circuit 81 Clock generation circuit 82 Inverter C1 Capacitors M41 to M44 N-type MOS transistor M45 P-type MOS transistors M61 to M65 N-type MOS transistor

Claims (5)

A first switching transistor and a capacitor connected in series between the input terminal and the common connection;
  A second transistor and a third transistor respectively disposed at both ends of the first transistor;
  A first source follower circuit including a fourth transistor connected to the input terminal and supplying a signal to the input terminal;
  A second source follower circuit including a fifth transistor that performs a predetermined operation using a voltage at a common connection between the first transistor and the capacitor as an input voltage;
  The second and third transistors have their drains and sources connected in common, and their common connections are connected to the sources and drains of the first transistors, respectively.
  The signal processing circuit is characterized in that a binary signal having opposite phases is supplied to the gate of the first transistor and the gates of the second and third transistors. A first switching transistor and a capacitor connected in series between the input terminal and the common connection;
  A second transistor and a third transistor respectively disposed at both ends of the first transistor;
  A fourth transistor connected to the input terminal;
  A common connection between the first transistor and the capacitor as an output terminal, and a fifth transistor connected to the output terminal,
  The second and third transistors have their drains and sources connected in common, and their common connections are connected to the sources and drains of the first transistors, respectively.
  A binary signal of opposite phase is supplied to the gate of the first transistor and the gates of the second and third transistors, respectively.
  The signal processing circuit is characterized in that the fourth transistor and the fifth transistor form a current mirror circuit. The said 2nd transistor and the said 3rd transistor each absorb the electric charge discharge | released from the 1st transistor when the said 1st transistor is OFF, respectively, The Claim 1 or Claim 2 characterized by the above-mentioned. The signal processing circuit described. A clock generation circuit for generating the binary signal;
  This clock generation circuit
  A sixth transistor and a seventh transistor connected in series between the power supply line and the common connection line;
  An eighth transistor and a ninth transistor connected in series between the power supply line and the common connection line;
  A clock signal is input to the gate of the sixth transistor, an inverted signal of the clock signal is input to the gate of the eighth transistor,
  Taking out the first output signal from the common connection of the sixth transistor and the seventh transistor, and supplying the first output signal to the gate of the ninth transistor;
  The second output signal is taken out from a common connection portion between the eighth transistor and the ninth transistor, and the second output signal is supplied to the gate of the seventh transistor. The signal processing circuit according to claim 1.   5. The signal processing circuit according to claim 1, wherein a frequency of the binary signal is in a range of 100 [MHz] to 10 [GHz].

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