JPH10135817A - Level shirt circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a level shift circuit of reduced signal delay by providing first to fourth MOS transistors and fetching an output signal from the fourth MOS transistor. SOLUTION: Both of pMOS 30 and nMOS 31 are diode-connected and pMOS 34 and nMOS 35 constitute an inverter gate 38 inputting the potential Va of the connecting point of pMOS 30 and nMOS 31. Then when the W/L ratios (W is a gate width and L is a gate length) of pMOS 30 and pMOS 34 are made the same and the W/L ratios of pMOS 31 and nMOS 35 are made the same, the neighborhood of the center of a potential Va and the threshold value of the inverter gate 38 are nearly coincident so that the inverter gate 38 is immediately inverted with the transition of the potential Va. Consequently, delay between CK and Vout is reduced to apply a thin film transistor using the polycrystalline silicon thin film to nMOS 31 and nMOS 35, for instance, without any problem.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a level shift circuit used for a liquid crystal display (LCD).

[0002]

BACKGROUND OF THE INVENTION In recent years, demands for display quality and power consumption of LCDs have become increasingly severe. For example, in the case of a TN type liquid crystal, a 10 V _PP image signal is supplied to a data bus and a By adopting a so-called common fixed driving method in which the potential of the electrode (sometimes referred to as a common electrode or a common electrode) is fixed to an intermediate potential and ± 5 V bipolar driving is performed, flicker and the like are suppressed and display quality is suppressed. In order to process a 10V _PP image signal in the data side driver circuit, at least one
Since a control signal of 0 V _PP or more and a power supply voltage are required, there is a disadvantage that power consumption increases. Therefore, in order to reduce the routing of the high-voltage control signal, a required high-voltage control signal is generated from the low-voltage control signal by a level shift circuit.

[0003]

2. Description of the Related Art FIGS. 4 and 5 are two structural diagrams of a conventional level shift circuit. CK is a low-voltage drive signal (CKx
Is an inverted signal of CK), and Vout is a high-voltage drive signal (V
outx is an inverted signal of Vout). Although not particularly limited, in the following description, the voltage of CK is set to 0 V to +5 V, the voltage of Vout is set to 0 V to +15 V, and p
The type MOS transistor is abbreviated as “pMOS” and the n-type MOS transistor is abbreviated as “nMOS”.

[0004] The level shift circuit shown in FIG. 4 operates between a power supply Vcc (+15 V) corresponding to the highest potential of Vout and a power supply Vss (0 V) corresponding to the lowest potential of Vout.
OS1 and nMOS2 are connected in series, and pMOS3 and nMOS2
MOS4 is connected in series, the gate of pMOS1 is connected to the output node 5 (an intermediate node between pMOS3 and nMOS4), and the gate of pMOS3 is connected to the output node 6 (p
(The intermediate node between the MOS1 and the nMOS2).

The level shift circuit shown in FIG.
Current mirror circuit 1 composed of S10 and pMOS11
2 is used as a load of the nMOS 13 and the nMOS 14, CK is applied to the gate of the nMOS 13 and the source of the nMOS 14, CKx is applied to the gate of the nMOS 14 and the source of the nMOS 13, and Vout is extracted from the drain of the nMOS 14.

In such a configuration, at the time of transition of CK (at the time of transition from 0 V to +5 V or the reverse), one of nMOS 2 (reference numeral 13 in FIG. 5) and nMOS 4 (reference numeral 14 in FIG. 5) is used. Are turned on and the other is turned off, and the turn-on and turn-off timings need to match as much as possible. For example, n
After the MOS 2 (13 in FIG. 5) is turned on, the nMOS 4 (1 in FIG. 5) is delayed for a short time td.
If 4) is turned off, an undesired delay corresponding to time td occurs between CK and Vout.

[0007]

The above delay is caused by the nMOS.
2 (reference numeral 13 in FIG. 5) and nMOS 4 (reference numeral 1 in FIG. 5).
In 4), for example, when a thin film transistor using a poly silicon thin film is applied, the size tends to increase. This is because it is difficult to uniformly control the threshold value of this type of transistor at a low voltage.

Accordingly, an object of the present invention is to provide a level shift circuit having a small signal delay.

[0009]

According to the first aspect of the present invention,
A first MOS transistor of one conductivity type having a source connected to a power supply terminal and having a common gate and drain;
The gate and drain are connected to the input signal terminal and the first MO
2M of the other conductivity type connected to the drain of the S transistor
An OS transistor, a third MOS transistor of one conductivity type having a source connected to the power supply terminal and a gate connected to the gate of the first MOS transistor, and a source connected to a second input signal terminal and a gate connected to the gate of the second MOS transistor; And a fourth MOS transistor of another conductivity type having a drain connected to the drain of the third MOS transistor, and an output signal is taken out from the drain of the fourth MOS transistor.

According to a second aspect of the present invention, a first MOS transistor of one conductivity type having a source connected to the first power supply terminal and a gate connected to the second power supply terminal, and a gate connected to the first input signal terminal and having the source connected to the first input signal terminal. A second MOS transistor of another conductivity type having a drain connected to the drain of the first MOS transistor; a third MOS transistor of one conductivity type having a source connected to the first power supply terminal and a gate connected to the second power supply terminal; Is connected to a second input signal terminal, a gate is connected to the gate of the second MOS transistor, and a drain is connected to the drain of the third MOS transistor. An output signal is extracted.

According to the present invention, the potential difference between the power supply terminal (or the first power supply terminal) and the first input signal terminal is equal to the potential difference between the first MOS transistor and the second MO transistor.
The voltage is divided by the S transistor, and the third
The MOS transistor and the fourth MOS transistor are turned on / off. If the size ratio of the first MOS transistor and the second MOS transistor is substantially equal to the size ratio of the third MOS transistor and the fourth MOS transistor, the divided voltage becomes the third MOS transistor. And near the threshold value of the fourth MOS transistor.
The on / off of the OS transistor and the fourth MOS transistor can be accelerated to reduce signal delay.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 show a first embodiment of the level shift circuit according to the present invention. In FIG. 1, 3
0 is pMO as the first MOS transistor of one conductivity type
S and 31 are nMOSs as second MOS transistors of the other conductivity type, and the source of the pMOS 30 is Vcc1 (+
15V), the gate and drain of the pMOS 30 are connected to the drain and gate of the nMOS 31, and the source of the nMOS 31 is connected to the first input signal terminal 33 for CK.

Reference numeral 34 denotes a pMOS as a third MOS transistor of one conductivity type, and 35 denotes a fourth MOS transistor of another conductivity type.
An nMOS as a transistor, the source of the pMOS 34 is connected to the power supply terminal 36 for Vcc2 (+15 V), the gate of the pMOS 34 is connected to the gate of the pMOS 30, the drain of the pMOS 34 is connected to the drain of the nMOS 35, and the gate of the nMOS 35 is connected. It is configured to be connected to the gate of the pMOS 30 and takes out Vout from the drain of the nMOS 35.

With this configuration, the pMOS 30 and n
Each of the MOSs 31 is diode-connected,
pMOS34 and nMOS35 are pMOS30 and nMO
The inverter gate 38 that receives the potential (Va for convenience) at the connection point with S31 is configured. FIG. 2 is a waveform diagram of each part in FIG. In this waveform example, Va is CK
About + 11V in the + 5V period of CK and about + 7V in the 0V period of CK
It has become. That is, Va is about + 7V to about +11.
It has a variation width up to V.

Here, W of pMOS30 and pMOS34
/ L ratio (W is the gate width, L is the gate length) and the W / L ratio of nMOS31 and nMOS35 are the same, the center of the variation width of Va and the inverter gate 3
8 can be made substantially equal to the threshold value VT, and the inverter gate 38 is immediately inverted (pM
One of the OS 34 and the nMOS 35 is turned on and the other is turned off).

Therefore, the delay between CK and Vout can be reduced, and for example, a thin film transistor using a poly silicon thin film for the nMOS 31 and nMOS 35 can be applied without any trouble. The transistors (pMOS30, pMOS34, nMOS31) of the above embodiment are used.
And nMOS 35) can be switched. In this case, if Vcc1 = Vcc2 = -10V, the amplitude of Va (see the broken line in FIG. 2) is + 1V to -3V.
And the amplitude of Vout (see the broken line in FIG. 2) is
+ 5V to -10V.

Further, one of CK and CKx can be a constant potential of an external input. For example, when CKx is set to a constant potential, although the amplitude of the gate-source voltage of the nMOS 35 becomes small and the allowable operation range of the threshold becomes narrow, a plurality of level shift circuits are provided on the same substrate. CKx terminal 3
7 can be shared, so that there is an advantage that the number of terminals required for driving can be reduced and power can be saved.

FIG. 3 is a diagram showing a second embodiment of the level shift circuit according to the present invention. In FIG. 3, reference numeral 40 denotes a source connected to a first power supply terminal 42 for Vcc1 (+15 V), and a gate connected to a second power supply terminal 43 for Vcc3 (+8 V).
, And the pMOS 40 corresponds to a first MOS transistor of one conductivity type. Reference numeral 41 denotes an nMO having a source connected to the first input signal terminal 44 for CK, and a drain and a gate connected to the drain of the pMOS 40.
S, and this nMOS 41 corresponds to a second MOS transistor of another conductivity type. 45 sets the source to Vcc2 (+1
5V) is connected to the third power supply terminal 47 (common to the first power supply terminal 42 when Vcc1 = Vcc2), and the gate is connected to the second power supply terminal 47.
This is a pMOS connected to the power supply terminal 45.
45 corresponds to a third MOS transistor of one conductivity type.
Reference numeral 46 denotes an nMOS having a source connected to the second input signal terminal 48 for CKx, a gate connected to the gate of the nMOS 41, a drain connected to the drain of the pMOS 45, and Vout taken out from the drain.
46 corresponds to a fourth MOS transistor of another conductivity type.

With this structure, the pMOS 40 and pMOS
The MOS 45 is a constant current source controlled by Vcc3, and the nMOS 41 is diode-connected. Therefore, the drain potential of the nMOS 41 is the potential V obtained by dividing the potential difference between Vcc1 and CK by the pMOS 40 and the nMOS 41.
b, and the nMOS 46 is quickly turned on and off in accordance with this Vb. Therefore, as in the first embodiment, CK and Vout
Between the nMOS 41 and nMOS 41
A thin film transistor using a poly silicon thin film can be applied to the MOS 46 without any trouble.
Is advantageous in that it can flexibly cope with variations in the threshold values of the pMOS 40 and the pMOS 45.

Also in this embodiment, the conductivity type of each transistor can be switched, and one of CK and CKx can be set to a constant potential of an external input.

[0021]

According to the first or second aspect of the present invention, the third MOS transistor and the fourth MOS transistor can be turned on / off at a high speed to reduce a signal delay. The thin film transistor using the silicon thin film can be applied without any trouble.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment.

FIG. 2 is a waveform chart of the first embodiment.

FIG. 3 is a configuration diagram of a second embodiment.

FIG. 4 is a configuration diagram of a conventional example.

FIG. 5 is another configuration diagram of a conventional example.

[Explanation of symbols]

 Vout: output signal 30: pMOS (first MOS transistor) 31: nMOS (second MOS transistor) 32, 36: power supply terminal 33: first input signal terminal 34: pMOS (third MOS transistor) 35: nMOS (fourth MOS transistor) 37 : Second input signal terminal 40: pMOS (first MOS transistor) 41: nMOS (second MOS transistor) 42: first power supply terminal 43: second power supply terminal 45: pMOS (third MOS transistor) 46: nMOS (fourth MOS transistor) 47: Third power terminal (first power terminal)

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Keizo Morita 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Hiroshi Yoshioka 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 Inside Fujitsu Limited

Claims (2)

[Claims] A first MOS transistor of one conductivity type having a source connected to a power supply terminal and having a common gate and drain, and a source connected to a first input signal terminal and having a gate and a drain connected to a drain of the first MOS transistor. A second MOS transistor of another conductivity type, a source connected to the power supply terminal and a gate connected to the first MOS transistor.
One conductivity type third MOS connected to the gate of the transistor
A transistor and a source are connected to the second input signal terminal, and a gate is connected to the second input signal terminal.
The drain of the third transistor is connected to the gate of the OS transistor.
A fourth MOS transistor of another conductivity type connected to the drain of the MOS transistor, wherein an output signal is taken out from the drain of the fourth MOS transistor. 2. A first MOS transistor of one conductivity type having a source connected to a first power supply terminal and a gate connected to a second power supply terminal, and a source connected to a first input signal terminal and having a gate and a drain connected to the first MOS transistor. A second MOS transistor of another conductivity type connected to the drain of the transistor, a third MOS transistor of one conductivity type having a source connected to the first power supply terminal and a gate connected to the second power supply terminal, and a source connected to the second input signal terminal And the gate is connected to the second M
The drain of the third transistor is connected to the gate of the OS transistor.
A fourth MOS transistor of another conductivity type connected to the drain of the MOS transistor, wherein an output signal is taken out from the drain of the fourth MOS transistor.