JPH0879053A - Level shift circuit - Google Patents

Abstract

PURPOSE: To provide a level shift circuit small in pattern area and fast in voltage conversion rate. CONSTITUTION: This level shift circuit is provided with a level shift section 20 connected among a VDD and nodes A, B, receiving an input signal IN having a level between the VDD and the VSS1 and outputting an output signal OUT whose level is between the VDD and a VSS2 and with a current control section 21 comprising an N-channel 1st MOS transistor(TR) Q17 connected between the node A and the VSS1, whose gate receives a voltage Va (VSS2<Va<VSS1) and an N-channel 2nd MOSTR Q18 connected between the node B and the VSS1 and whose gate receives the voltage Va.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift circuit. In particular, the present invention relates to a level shift circuit used for a liquid crystal display driving semiconductor integrated circuit which requires a high voltage conversion rate.

[0002]

2. Description of the Related Art A semiconductor integrated circuit for driving a liquid crystal display captures an image signal serially, converts it into a parallel signal group, and further performs level conversion (voltage conversion),
It outputs a drive signal for driving the column / row lines of the liquid crystal display. While the image signal has a signal level of about 5V, the column row line of the liquid crystal display needs to be driven at a high voltage of about 40V.
Therefore, this liquid crystal display driving semiconductor integrated circuit requires a level shift circuit having a very high voltage conversion rate.

A conventional high voltage conversion rate level shift circuit will be described with reference to FIG. That is, P-channel MO
It is composed of S transistors Q11 and Q12, N-channel MOS transistors Q13, Q14, Q15 and Q16, and an inverter 11. MOS transistors Q11, Q13, Q15
The source and drain are connected in series between the first power supply potential VDD (for example, 5 V) and the third power supply potential VSS2 (for example, -40 V). Also, the MOS transistor Q
Sources and drains of 12, Q14 and Q16 are connected in series between the first power supply potential VDD and the third power supply potential VSS2. The gate of the MOS transistor Q13 is connected to the drain of the MOS transistor Q14, and the gate of the MOS transistor Q14 is connected to the drain of the MOS transistor Q13. The gates of the MOS transistors Q11 and Q15 are commonly connected to receive the input signal IN, and the gates of the MOS transistors Q12 and Q14 are commonly connected to receive the output signal of the inverter 11 which is the inverted signal of the input signal IN. There is. The inverter 11 has a first power supply potential VDD
And the second power supply potential VSS1 (for example, 0V). With the above configuration, the transistor Q13
The output signal OUT is obtained at the drain of and the input signal IN
The signal amplitude level of VDD-VSS1 (about 5V) is set to about 9
A signal amplitude level of VDD-VSS2 (about 45 V) amplified twice can be obtained.

By the way, in order to operate the level shift circuit shown in FIG. 6, it is necessary that both the conductance of Q11> the conductance of Q13 and Q15 and the conductance of Q12> the conductance of Q14 and Q16 be satisfied. The left side of the above two equations must be larger than the right side in order to obtain stable operation. In practice, the conductance is adjusted by the gate width / gate length (hereinafter abbreviated as W / L) of the transistor. Specifically, for the MOS transistors Q11 and Q12, the W / L is set to 25/1 (the minimum processing line width of the gate polysilicon film is set to 1), and the MO
W / L of each of the S transistors Q13, Q14, Q15 and Q16 is set to 1/25. A signal with an amplitude of 5V is applied to the MOS transistors Q11 and Q12, while
Since the gate bias of the transistors Q13, Q14, Q15, Q16 becomes deep (the gate potential becomes very high with respect to the source potential), it is necessary to make a difference to this extent.

However, in recent years, a low voltage operation is required in a semiconductor integrated circuit for driving a liquid crystal display, and a low voltage of an input signal is also being advanced. At the same time, due to the characteristics of liquid crystal displays, the output voltage is becoming higher. As a result, a higher voltage conversion rate is required in the level shift circuit inside the liquid crystal display driving semiconductor integrated circuit. Specifically, assuming that the power supply voltage is 2.5 V and the output voltage is -60 V, the voltage conversion rate of about 25 times is required in the level shift circuit. If this is to be realized in the conventional level conversion circuit as shown in FIG. 6, it is necessary to make the difference in W / L between the MOS transistors Q11 and Q13 and the MOS transistors Q13 and the like very large. This leads to an increase in the pattern area, and at the same time, the W and L of the transistor are increased, so that the parasitic capacitance is increased, which is an obstacle in performing high-speed level shift.

[0006]

As described above,
In the level shift circuit, when trying to obtain a high voltage conversion rate, there is a problem that the pattern area of the level shift circuit increases and it becomes difficult to increase the speed. SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned drawbacks and provide a high level voltage conversion rate level shift circuit with a small pattern area.

[0007]

In order to achieve the above object, according to the present invention, a first power supply potential and a second power supply potential which are connected between a first power supply potential and a first node and a second node are provided. A level shifter that receives an input signal having an amplitude between the first power supply potential and the third power supply potential, and outputs an output signal having an amplitude between the first power supply potential and the third power supply potential; A first MOS transistor of a first conductivity type, a second node, and a second power supply which are connected to a power supply potential and whose gate is supplied with a predetermined potential between the second power supply potential and the third power supply potential There is provided a level shift circuit comprising: a current control unit including a second MOS transistor of the first conductivity type which is connected between the gate and a predetermined potential and is applied to the gate.

Further, the level shift section includes third and fourth MOS transistors of the first conductivity type, and the gate of each MOS transistor is connected to the drain of another MOS transistor. I will provide a.

[0009]

When the means provided by the present invention is used, the current control section has the first and second MOS transistors.
Since the amount of current flowing between the second node and the third power supply potential is limited, the stability of the level shift circuit for level conversion is significantly improved. In order to adjust the conductance of the first and second MOS transistors to be low, adjustment is not performed by adjusting W and L, but by applying a predetermined potential to the gate. As a result, it is possible to prevent an increase in pattern area.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A level shift circuit of the present invention and a liquid crystal display driving semiconductor integrated circuit equipped with the same will be described below with reference to the drawings. FIG. 1 shows a circuit configuration diagram of the level shift circuit of the first embodiment. That is, it is composed of the level shift section 20 and the current control section 21.

The level shift unit 20 is a P channel type MO.
It is composed of S transistors Q11 and Q12, N-channel MOS transistors Q13, Q14, Q15 and Q16, and an inverter 11. MOS transistors Q11, Q13, Q15
Has a source / drain connected in series between the first power supply potential VDD (for example, 2.5 V) and the first node A. Also, the MOS transistors Q12, Q14, Q16 are the first
The source and the drain are connected in series between the power supply potential VDD and the second node B. MOS transistor Q
The gate of 13 is the drain of the MOS transistor Q14, and M
The gate of the OS transistor Q14 is a MOS transistor Q
Connected to 13 drains respectively. The gates of the MOS transistors Q11 and Q15 are commonly connected to receive the input signal IN, and the gates of the MOS transistors Q12 and Q14 are commonly connected to be an inverted signal of the input signal IN.
The output signal of the inverter 11 is given. The inverter 11 has a first power supply potential VDD and a second power supply potential VSS1.
(For example, 0V).

The current control section 21 is composed of N-channel type MOS transistors Q17 and Q18. The source / drain of the transistor Q17 is connected between the node A and the third power supply potential VSS2 (for example, -60V), and the gate is applied with a predetermined potential Va (for example, -30V). The source / drain of the transistor Q18 is connected between the node B and the third power supply potential VSS2, and the gate thereof is applied with a predetermined potential Va, like the transistor Q17. In addition,
If the potential of Va is the potential obtained by adding the threshold voltage (for example, 3 V) of the MOS transistors Q17 and Q18 to the third power source potential VSS2, it operates.

With the above configuration, the output signal OUT is obtained at the drain of the transistor Q13, and VDD-VSS1 (about 2.
VDD-VSS2 (about 62.5V) which is amplified about 25 times.
A signal amplitude level of 5 V) can be obtained. To realize such a high voltage conversion rate with the circuit described in the conventional example,
It was not realistic from the viewpoint of pattern area and speedup.

In the circuit shown in FIG. 1, due to the presence of the two MOS transistors in the current controller 21, the amount of current flowing between the first node A and the second node B and the third power supply potential is limited. Therefore, the stability of the level shift circuit with respect to the level conversion is significantly improved. First and second MO
In order to adjust the conductance of the S transistor to a low value, it is not adjusted by W and L, but by applying a predetermined potential to the gate. As a result, it is possible to prevent an increase in pattern area.

Also in this embodiment, it is necessary to satisfy both conditions of conductance of Q11> conductance of Q13, Q15, Q17 and conductance of Q12> conductance of Q14, Q16, Q18. The left side of the above two equations must be larger than the right side in order to obtain stable operation. Here, it is a feature of the present invention that the voltage applied to the gates of the transistors Q17 and Q18 is used instead of using W / L for adjusting the conductance. When the conductance is adjusted by W / L as in the conventional example, since the conductance and W / L are in direct proportion, it was necessary to set proportional W / L in order to make a difference. However, when the voltage applied to the gate is adjusted as in the present application, the conductance is substantially proportional to the square of the gate voltage, which makes the adjustment easier. W /
Of course, it is not necessary to adjust L.

The size of a specific MOS transistor is described below. MOS transistors Q11 and Q12 are 10/1
(The minimum processing line width of the gate polysilicon film is 1 and is 0.8 μm, for example), and the MOS transistor Q1
1 / W / L for 3, Q14, Q15, Q16, Q17, Q18
Set to 1. It will be appreciated that this results in a significant reduction in pattern area. Further, since the size of the transistor is extremely small, the parasitic capacitance can be significantly reduced. As a result, the level shift is also performed at high speed.

FIG. 2 shows operation waveforms of the level shift circuit of the present invention. Next, the circuit configuration of the liquid crystal display driving semiconductor integrated circuit 30 using the level shift circuit of the present invention will be described with reference to FIG. The semiconductor integrated circuit 30 for driving the liquid crystal display has the first power supply potential VDD (2.5
V) and the second power supply potential VSS1 (0V) supply terminal, as well as V0R, V2R, V3R, V which are the input terminals of the high voltage power supply.
There are 5R, V0L, V2L, V3L and V5L. The voltage of the high-voltage power supply differs depending on the liquid crystal display, but for example, 0
V, -10V, -30V, -60V, 0V, -10V,
It is set to -30V and -60V. In addition, the integrated circuit 30
Has eight data input terminals D11 to D18, various control signal terminals SCP, DIR, E101, E102, LP, FR and the like.

As shown in FIG. 3, the liquid crystal display driving semiconductor integrated circuit 30 includes a serial-parallel conversion circuit 31, an 8-bit 20-row shift register 32, a 160-bit latch 33, and a 160-bit level shift circuit array 3.
It is composed of a 4-valued buffer 35 of 4, 160 bits. In the 160-bit level shift circuit array 34,
The level shift circuit described in FIG. 1 can be used.

As described above, by using the level shift circuit of the present invention in the liquid crystal display driving semiconductor integrated circuit, it is possible to significantly reduce the chip area. In a semiconductor integrated circuit for driving a liquid crystal display, since a serially input image data is converted into parallel data of 160 bits and then a level shift is performed, a very large number (160 in this embodiment) is used. This is because a level shift circuit is required and the chip area can be reduced by 160 times.

As described above, in the semiconductor integrated circuit for driving a liquid crystal display, since a plurality of high voltages are supplied from the outside, one of them, for example, V3R or V3L can be used as Va. As a result, it is not necessary to have an intermediate gate generating circuit or the like inside.

Next, FIG. 4 shows a circuit configuration diagram of a level shift circuit according to a second embodiment of the present invention. Similarly to the first embodiment, it is composed of a level shift section 20 and a current control section 21.

The level shift unit 20 is a P channel type MO.
It is composed of S transistors Q11 and Q12, N-channel MOS transistors Q13 and Q14, and an inverter 11. The MOS transistors Q11 and Q13 have a first power supply potential V
The source and drain are connected in series between DD (for example, 2.5 V) and the first node A. Further, the MOS transistors Q12 and Q14 have source and drain connected in series between the first power supply potential VDD and the second node B. The gate of the MOS transistor Q13 is connected to the drain of the MOS transistor Q14, and the gate of the MOS transistor Q14 is connected to the gate of the MOS transistor Q13. The input signal IN is applied to the gate of the MOS transistor Q11, and the output signal of the inverter 11, which is an inverted signal of the input signal IN, is applied to the gate of the MOS transistor Q12. The inverter 11 operates between the first power supply potential VDD and the second power supply potential VSS1 (for example, 0V).

The current controller 21 is composed of N-channel type MOS transistors Q17 and Q18. The source / drain of the transistor Q17 is connected between the node A and the third power supply potential VSS2 (for example, -60V), and the gate is applied with a predetermined potential Va (for example, -30V). The source / drain of the transistor Q18 is connected between the node B and the third power supply potential VSS2, and the gate thereof is applied with a predetermined potential Va, like the transistor Q17.

With the above configuration, the output signal OUT is obtained at the drain of the transistor Q13, and VDD-VSS1 (about 2.
VDD-VSS2 (about 62.5V) which is amplified about 25 times.
A signal amplitude level of 5 V) can be obtained.

Since the function and effect are almost the same as those of the first embodiment, detailed description thereof will be omitted. Next, FIG. 5 shows a circuit configuration diagram of a level shift circuit according to a third embodiment of the present invention. Similarly to the first and second embodiments, the level shift unit 20
And a current control unit 21.

The level shift unit 20 is a P channel type MO.
It is composed of S transistors Q11 and Q12, N-channel MOS transistors Q13 and Q14, and an inverter 11. The MOS transistors Q11 and Q13 have a first power supply potential V
The source and drain are connected in series between DD (for example, 2.5 V) and the first node A. Further, the MOS transistors Q12 and Q14 have source and drain connected in series between the first power supply potential VDD and the second node B. The drain and gate of the MOS transistor Q11 are commonly connected, and are connected to the gate of the MOS transistor Q12. The gate of the MOS transistor Q13 is supplied with the input signal IN, and the gate of the MOS transistor Q14 is supplied with the output signal of the inverter 11, which is an inverted signal of the input signal IN. The inverter 11 has a first power supply potential VDD and a second power supply potential VSS1 (for example, 0
V).

The current control section 21 is composed of N-channel type MOS transistors Q17 and Q18. The source / drain of the transistor Q17 is connected between the node A and the third power supply potential VSS2 (for example, -60V), and the gate is applied with a predetermined potential Va (for example, -30V). The source / drain of the transistor Q18 is connected between the node B and the third power supply potential VSS2, and the gate thereof is applied with a predetermined potential Va, like the transistor Q17.

With the above configuration, the output signal OUT is obtained at the drain of the transistor Q14, and the signal amplitude level of the input signal IN is VDD-VSS1 (about 2.
VDD-VSS2 (about 62.5V) which is amplified about 25 times.
A signal amplitude level of 5 V) can be obtained.

Since the function and effect are almost the same as those of the first embodiment, detailed description thereof will be omitted. As described above with reference to the first, second, and third embodiments, when the present invention is used, the current controller has the first node and the second node due to the presence of the first and second MOS transistors. Since the amount of current flowing between the node and the third power supply potential is limited, the stability of the level shift circuit for level conversion is significantly improved. In order to adjust the conductance of the first and second MOS transistors to be low, adjustment is not performed by W and L, but
It is adjusted by applying a predetermined potential to the gate. As a result, it is possible to prevent an increase in pattern area.

Although the above description has been made by using the level shift circuit for amplifying to a negative voltage, the polarity of the MOS transistor is changed to change the P-channel type to the N-channel type and the N-channel type to the P-channel type. Thus, it is possible to configure a level shift circuit that amplifies to a positive voltage. Further, it goes without saying that various modifications can be made without departing from the spirit of the present invention.

[0031]

As described above, according to the present invention, it is possible to provide a high-speed level conversion circuit with a high voltage conversion rate in a small pattern area.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing waveforms during operation of the present invention.

FIG. 3 is a circuit configuration diagram of a semiconductor integrated circuit for driving a liquid crystal display to which the first embodiment of the present invention is applied.

FIG. 4 is a circuit configuration diagram showing a second embodiment of the present invention.

FIG. 5 is a circuit configuration diagram showing a third embodiment of the present invention.

FIG. 6 is a circuit configuration diagram showing a conventional level shift circuit.

[Explanation of symbols]

 11 inverter 20 level shift unit 21 current control unit A, B node Q MOS transistor

Claims (2)

[Claims] 1. A first power supply potential, a first node and a second
Of the first power supply potential and the first power supply potential, the first power supply potential and an input signal having an amplitude between the first power supply potential and the second power supply potential.
A level shifter that outputs an output signal having an amplitude between the second power supply potential and the third power supply potential, and the second power supply connected to the gate between the first node and the third power supply potential. A first conductivity type first MOS transistor to which a predetermined potential is applied between the second power supply potential and the second power supply potential, and a predetermined potential between the third power supply potential and the second power supply potential. First to be given a potential
A level shift circuit comprising: a current control unit including a conductive second MOS transistor. 2. The level shift unit is a third conductive type third.
2. The level shift circuit according to claim 1, further comprising a fourth MOS transistor, wherein the gate of each MOS transistor is connected to the drain of another MOS transistor.