JP3092506B2 - Semiconductor device and display driving device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a leakage current small, to perform high integration, to perform formation with less processes and to make an output level be appropriate by performing constitution by the transistors of the same conductive type. SOLUTION: The respective source and drain of P type transistors 13 and 14 are serially connected between a power source and ground, positive logic or negative logic is impressed from an input (IN) side to the gate of the P type transistor 13 and logic for which input (IN) is inverted is impressed from an inverted input (IN with upper bar) side to the gate of the P type transistor 14. Then, the source and drain of the P type transistor 12 are interposed between the inverted input (IN with upper bar) to the gate of the P type transistor 14 and a capacitor 15 whose one end is connected between the P type transistor 12 and the gate of the P type transistor 14 and other end is connected between the P type transistor 13 and connection point of the P type transistor 14 is interposed. Thus, a Low level outputted from an output terminal (OUT) is corrected so as to be a potential equivalent to a ground level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a display driving device using the same, and more particularly, to a semiconductor device including a plurality of transistors of the same conductivity type and a display driving device using the same.

[0002]

2. Description of the Related Art Conventionally, for example, a driver circuit of a liquid crystal display device or the like is provided with a thin film transistor (TFT).
sistor), usually CMOS (complementary type)
A circuit is used. This CMOS circuit is widely used because of its advantages such as low power consumption and proper output.

FIG . 40 shows a configuration of a CMOS inverter circuit. As shown in FIG. 40 , CMOS1
Two types of transistors, PMOS2 and NMOS3, are used in pairs. In this CMOS1, when IN (input) is "0", PMOS2 is turned on and "1" is output (output) from the power supply. When the input is “1”,
The NMOS 3 is turned on, and “0” is output from the ground. As described above, the CMOS inverter circuit outputs the inverted input.

In addition, a PMOS or N
It is also possible to form an inverter circuit using one of the MOS transistors. This inverter circuit includes a ratio-type inverter circuit and a non-ratio-type inverter circuit.
There are resistance load type, E / E type, E / D type, and the like.

In the above conventional example, an inverter circuit has been described as an example. However, in addition to this, when a latch circuit, a tristate circuit, a drain driver circuit, a gate driver circuit, etc. are configured, or an OR circuit as a logic circuit, CMOS and the like have also been used to form exclusive OR circuits, AND circuits, NAND circuits, and the like.

[0006]

However, in such a conventional semiconductor device, the CMO shown in FIG.
Since S1 is composed of two types of transistors, PMOS2 and NMOS3, when manufacturing CMOS, P1
Since it is necessary to form both the MOS and the NMOS, the number of impurity implantation steps increases, and the number of masks also increases. Therefore, there is a problem that the manufacturing process and the element structure are complicated, and the cost is increased.

In order to suppress a leakage current from a channel portion of a semiconductor device, an LDD structure in which regions having different impurity concentrations are formed as a semiconductor element structure is adopted.
Further, there is a problem that the number of impurity implantation steps increases.

[0008] Therefore, without using the above-mentioned CMOS, PM
As a configuration using either the OS or the NMOS transistor, for example, in the case of a resistance load type of the above-described ratio type inverter circuit, a transistor and a load resistor are provided. Since this transistor uses either PMOS or NMOS, the element structure is simplified and the number of manufacturing steps can be reduced. However, since a load resistor occupying a large area is required in addition to the transistor, high integration cannot be achieved, and a circuit using the load resistor has a problem that a DC leakage current increases and an output level decreases. is there.

Further, FIG. 41 shows a case where two PMOSs are used.
FIG. 4 is a diagram showing a proportionless inverter circuit 7 in which three basic circuits of the constructed proportionless inverter are connected in series;
FIG. 2 is a diagram showing signal waveforms of various parts when the non-ratio inverter circuit 7 of FIG. 41 operates.

As shown in FIGS. 41 and 42 , even if the potential of the input (IN) and the inverted input (￣IN) initially input to the ratioless inverter circuit 7 are Vdd and the ground potential, 01 output is obtained. (01) and the inverted 01 output ($ 01), the voltage slightly rises above the ground potential,
When the two outputs (02) and the inverted 02 output (） 02) are reached, the voltage further rises from the ground potential, and the final output (OU
At T) and the inverted output (￣OUT), the low level rises significantly above the ground potential, so that a circuit using this inverter may malfunction.

As described above, when the CMOS circuit is constituted only by the PMOS, the ground potential VGND rises by the threshold value of the PMOS. However, when the CMOS circuit is constituted only by the NMOS, the power supply potential Vdd is reduced by the NMOS. It rises by the threshold.

That is, the CMOS circuit is replaced by PMOS or N
If only one of the transistors is used, the output becomes dull by the threshold value of the transistor, and the operating margin of the next-stage circuit is reduced. Therefore, it is impossible to connect a large number of inverter circuits in cascade and also to connect other circuits.

Therefore, the present invention increases the ground potential VGND or the power supply potential Vdd even if the inverter circuit composed of the complementary transistors is constituted by only one of the P-type and N-type insulated gate transistors. Another object is to provide a semiconductor device capable of outputting without falling and a display driving device using the semiconductor device.

[0014]

According to a first aspect of the present invention, there is provided a semiconductor device according to the first aspect, wherein a high potential is input to an input terminal, a first transistor of one conductivity type, and a low potential is input to an input terminal. A second transistor of the same conductivity type as the first transistor, output means connected to the output terminals of the first and second transistors, and non-inverting signal supply means connected to the gate of the first transistor; an inverted signal supply means connected to the gate of said second transistor, said anti
Input terminal is connected to the inverted signal supply means or the non-inverted signal supply means.
Same conductivity as the connected first and second transistors
And a third transistor of the type
An output terminal and an output terminal of the first and second transistors;
An output voltage compensating circuit comprising a connected capacitor means , wherein the output voltage compensating circuit suppresses a rise in a low potential or a drop in a high potential output from the output means. .

That is, the first transistor and the second transistor perform a switching operation by the supply signals of the non-inversion signal supply means and the inversion signal supply means connected to their respective gates, and output from the output means to a high potential or a low potential. When the potential is output, the output voltage compensating circuit suppresses the rise of the low potential and the fall of the high potential.

Therefore, even if the semiconductor device according to the first aspect is constructed using transistors of the same conductivity type, an appropriate high voltage is applied in accordance with signals input from the non-inverted signal supply means and the inverted signal supply means, respectively. Since an output signal of a potential or a low potential is output, malfunction can be prevented even if a circuit is formed using this semiconductor device.

Further, since the first transistor and the second transistor are composed of transistors of the same conductivity type, the number of manufacturing steps is reduced, high integration is possible, and cost reduction and high density Can be achieved.

Further, since the first transistor and the second transistor are alternately switched by the non-inverting signal supply means and the inversion signal supply means, the leakage current can be reduced.

Further, the output voltage compensation circuit includes a third transistor of the inverting signal supply means or non-inverted signal supply means input connected to the first and second transistors of the same conductivity type, the An output terminal of the third transistor and capacitance means connected to the output terminals of the first and second transistors may be included.

That is, as a specific output voltage compensating circuit, for example, the input terminal of the third transistor is connected to the inversion signal supply means or the non-inversion signal supply means,
Is connected between the output terminal of the first transistor and the output terminals of the first and second transistors.

Therefore, the first or second transistor of the same conductivity type has a characteristic that its output potential becomes dull by the threshold value, so that a so-called "bootstrap" is formed by the third transistor and the capacitor means. With this configuration, an appropriate output potential can be compensated.

The semiconductor device according to claim 2 wherein the claim 1 or the invention of claim 2, wherein the first and second
May be P-type.

The semiconductor device according to claim 3 is the invention of claim 3, wherein, the input end of the first transistor may be connected to the inversion signal supply means.

According to a fourth aspect of the present invention, in the semiconductor device according to the third aspect, an input terminal of the second transistor may be connected to the inverted signal supply means.

According to a fifth aspect of the present invention, in the third aspect of the invention, the gate of the third transistor may be connected to the inverted signal supply means.

[0026] That is, the semiconductor device according to claims 2 to 5, the first, second and third transistors or the P-type, the input terminal of the first transistor, the input terminal of the second transistor Alternatively, the gate of the third transistor may be connected to the inverted signal supply means.

Therefore, it is not necessary to always input a high potential or a low potential to the input terminal or the gate, and it is sufficient to input a high potential or a low potential at a predetermined timing. By doing so, wiring can be simplified and power consumption can be reduced.

According to a sixth aspect of the present invention, in the semiconductor device according to the first aspect, the first and second transistors may be N-type.

According to a seventh aspect of the present invention, in the semiconductor device according to the sixth aspect , an input terminal of the first transistor may be connected to the non-inverting signal supply means.

The semiconductor device according to claim 8 is the invention of claim 6, wherein, the input end of the second transistor may be connected to the non-inverting signal supply means.

The semiconductor device according to claim 9 is the invention of claim 6, wherein a gate of the third transistor may be connected to the non-inverting signal supply means.

[0032] That is, the semiconductor device according to claims 6 to 9, the first, the second and third transistors or N-type, the input terminal of the first transistor, the input terminal of the second transistor Alternatively, the gate of the third transistor may be connected to the non-inverted signal supply means.

Therefore, it is not necessary to always input a high potential or a low potential to the input terminal or the gate, and a high potential or a low potential may be input at a predetermined timing. By connecting, the wiring can be simplified and the power consumption can be reduced.

According to a tenth aspect of the present invention, in the semiconductor device, the first and third transistors of the one conductivity type to which a high potential is inputted to an input terminal and the low potential to be inputted to an input terminal. And the fourth and fourth transistors of the same conductivity type as the third transistor.
Transistors, output means connected to the output terminals of the first and second transistors, and the third and fourth transistors
An inverting output unit connected to the output terminal of the first transistor and outputting a signal having a polarity opposite to that of the output unit; a non-inverting signal supply unit connected to gates of the first and fourth transistors; An inverted signal supply means connected to the gates of the second and third transistors, a first output voltage compensation circuit connected between the output terminals of the first and second transistors and the inverted signal supply means, , A second output voltage compensating circuit connected between the output terminals of the third and fourth transistors and the non-inverting signal supply means.

That is, a high potential is inputted to the input terminals of the first and third transistors, a low potential is inputted to the input terminals of the second and fourth transistors, and a non-potential is inputted to the gates of the first and fourth transistors. The inverted signal supply means is connected, the inverted signal supply means is connected to the gates of the second and third transistors, and the switching operation is performed by these supply signals. , The first and second output voltage compensating circuits suppress a rise in the low potential and a fall in the high potential.

[0036] Thus, the semiconductor device according to claim 10, wherein, in response to signals input respectively non-inverted signal supply means from the inverted signal supply means, output means and the inverted output by the first and second output voltage compensation circuit Since an appropriate high-potential or low-potential output signal is output from the means, malfunction can be prevented even if a circuit is formed using this semiconductor device.

Further, since the first to fourth transistors are of the same conductivity type, the number of manufacturing steps is reduced, high integration is possible, and low cost and high density are achieved. be able to.

Further, since the first and second transistors and the third and fourth transistors are alternately switched by the non-inverting signal supply means and the inversion signal supply means, respectively, the leakage current can be reduced. .

The semiconductor device according to the eleventh aspect is the first aspect.
0 , the first output voltage compensating circuit comprises: a fifth transistor having an input terminal connected to the inverted signal supply means and having the same conductivity type as the first to fourth transistors; 5 and the first terminal connected to the output terminals of the first and second transistors.
Wherein said second output voltage compensating circuit comprises:
A sixth transistor having an input terminal connected to the non-inverting signal supply means and having the same conductivity type as the first to fourth transistors; an output terminal of the sixth transistor;
And a second capacitor connected to the output terminal of the fourth transistor.

That is, as a specific output voltage compensating circuit, for example, the input terminal of the fifth transistor is connected to the inverted signal supply means, and the output terminal of the fifth transistor is connected to the output terminal of the first and second transistors. The first capacitor means is connected between the output terminal and the output terminal, the input terminal of the sixth transistor is connected to the non-inverting signal supply means, and the output terminal of the sixth transistor is connected to the output terminals of the third and fourth transistors. The second capacitance means is connected between the end and the other end.

Therefore, the first to fourth transistors of the one conductivity type have the characteristic that the output potential becomes dull by the threshold value, so that the fifth and sixth transistors and the first and second capacitors have the same characteristics. By constructing a so-called “bootstrap” by the means, an appropriate output potential is compensated.

According to a twelfth aspect of the present invention, there is provided a semiconductor device according to the first aspect.
0 or in the invention of claim 11, wherein said first to fourth transistors may be a P-type.

The semiconductor device according to the thirteenth aspect is the first aspect.
In the invention described in Item 2, the input terminal of the second transistor may be connected to the inverted signal supply unit.

The semiconductor device according to the fourteenth aspect is the first aspect.
In the invention described in Item 2, an input terminal of the first transistor may be connected to the inverted signal supply unit.

The semiconductor device according to the fifteenth aspect is the first aspect.
In the invention described in Item 2, the input terminal of the fourth transistor may be connected to the non-inverted signal supply unit.

The semiconductor device according to the sixteenth aspect is the first aspect.
In the invention described in Item 2, the input terminal of the third transistor may be connected to the non-inverted signal supply unit.

That is, in the semiconductor device according to the twelfth to sixteenth aspects, the first to sixth transistors are P-type, and the input terminals of the first and second transistors are connected to the inverted signal supply means. At the same time, the input terminals of the third and fourth transistors may be connected to a non-inverting signal supply unit.

Therefore, it is not necessary to always input a high potential or a low potential to each of the input terminals, and it is sufficient to input a high potential or a low potential at a predetermined timing. By connecting to the signal supply means, wiring can be simplified and power consumption can be reduced.

In the semiconductor device according to the seventeenth aspect , the first and third transistors of one conductivity type having a high potential input to an input terminal and a low potential being input to an input terminal. And the fourth and fourth transistors of the same conductivity type as the third transistor.
, An inverting output means connected to the output terminals of the first and second transistors, and a signal connected to the output terminals of the third and fourth transistors and having a polarity opposite to that of the inverting output means. An output means for outputting, the first
And a non-inverted signal supply connected to the gates of the fourth and fourth transistors, an inverted signal supply connected to the gates of the second and third transistors, and output terminals of the first and second transistors. A first output voltage compensating circuit connected between the non-inverted signal supply means and a second output connected between the output terminals of the third and fourth transistors and the inverted signal supply means; And a voltage compensating circuit.

That is, a high potential is input to the input terminals of the first and third transistors, a low potential is input to the input terminals of the second and fourth transistors, and a non-input is applied to the gates of the first and fourth transistors. The inverted signal supply means is connected, the inverted signal supply means is connected to the gates of the second and third transistors, and the switching operation is performed by these supply signals. , The first and second output voltage compensating circuits suppress a rise in the low potential and a fall in the high potential.

Therefore, in the semiconductor device according to the seventeenth aspect , the output means and the inverted output are provided by the first and second output voltage compensating circuits in accordance with the signals input from the non-inverted signal supply means and the inverted signal supply means, respectively. Since an appropriate high-potential or low-potential output signal can be output from the means, malfunction can be prevented even if a circuit is formed using this semiconductor device.

Further, since the first to fourth transistors are of the same conductivity type, the number of manufacturing steps is reduced, high integration is possible, and low cost and high density are achieved. be able to.

Further, since the first and second transistors and the third and fourth transistors are alternately switched by the non-inverting signal supply means and the inversion signal supply means, respectively, the leakage current can be reduced. .

The semiconductor device according to the eighteenth aspect is the first aspect.
7. The invention according to claim 7 , wherein the first output voltage compensating circuit comprises: a fifth transistor having an input terminal connected to the non-inverting signal supply means and having the same conductivity type as the first to fourth transistors; A first capacitance means connected to an output terminal of a fifth transistor and output terminals of the first and second transistors, wherein the second output voltage compensating circuit comprises:
An input terminal connected to the inverted signal supply means,
A sixth transistor having the same conductivity type as that of the fourth to fourth transistors, and a second capacitor connected to the output terminal of the sixth transistor and the output terminals of the third and fourth transistors may be included. .

That is, as a specific output voltage compensating circuit, for example, the input terminal of the fifth transistor is connected to the non-inverting signal supply means, and the output terminal of the fifth transistor is connected to the first and second transistors. Between the output end of
And an input terminal of a sixth transistor connected to the inverted signal supply means, and a second capacitor connected between the output terminal of the sixth transistor and the output terminals of the third and fourth transistors. It connects the means.

Therefore, the first to fourth transistors of the same conductivity type have the characteristic that their output potentials become dull by the threshold value, so that the fifth and sixth transistors are connected to the first and second capacitors. By constructing a so-called “bootstrap” by the means, an appropriate output potential is compensated.

The semiconductor device according to the nineteenth aspect is the first aspect.
In the invention according to claim 7 or claim 18 , the first to fourth transistors may be N-type.

According to a twentieth aspect of the present invention, there is provided a semiconductor device according to the first aspect.
In the invention described in Item 9, the input terminal of the first transistor may be connected to the non-inverted signal supply unit.

The semiconductor device according to the twenty- first aspect is the first aspect.
In the invention described in Item 9, the input terminal of the third transistor may be connected to the inverted signal supply unit.

The semiconductor device according to claim 22 is the first embodiment.
In the invention described in Item 9, the input terminal of the second transistor may be connected to the non-inverted signal supply unit.

The semiconductor device according to the twenty- third aspect is the first aspect.
In the invention described in Item 9, the input terminal of the fourth transistor may be connected to the inverted signal supply unit.

That is, in the semiconductor device according to the nineteenth to twenty- third aspects, the first to sixth transistors are N-type, or the input terminals of the first and second transistors are connected to the non-inverting signal supply means. And the third and fourth
May be connected to the inverted signal supply means.

Therefore, it is not necessary to always input a high potential or a low potential to each of the input terminals, and it is sufficient to input a high potential or a low potential at a predetermined timing. By connecting to the signal supply means, wiring can be simplified and power consumption can be reduced.

According to a twenty-fourth aspect of the present invention, there is provided a semiconductor device according to the first aspect.
0 or in the invention of claim 17, wherein the non-inverting input means and connected to the question and said output means, a seventh transistor of the first to fourth transistors of the same conductivity type, said inverting input means An eighth transistor connected between the first and fourth transistors and an inverting output means and having the same conductivity type as the first to fourth transistors.

That is, in the semiconductor device according to claim 10 or 17 , a seventh transistor is provided between the non-inverting input means and the output means, and an eighth transistor is provided between the inverting input means and the inverting output means. By providing,
A latch circuit is configured.

Therefore, by using transistors of the same conductivity type, the number of manufacturing steps can be reduced, the cost can be reduced, and the latch circuit can be mounted at a high density and obtain an appropriate output potential. it can.

[0067] Hanshirube俸apparatus of claim 25, wherein the claim 1
In the invention described in Item 0 or Claim 17 , the semiconductor device may include a logic circuit including a plurality of transistors of the same conductivity type as the first to fourth transistors.

The semiconductor device according to the twenty-sixth aspect is the second aspect.
5. The invention according to claim 5 , wherein the logic circuit is AND or N
An AND circuit may be included.

The semiconductor device according to the twenty-seventh aspect is the second aspect.
5. The invention according to claim 5 , wherein the logic circuit is OR or NO
An R circuit may be included.

The semiconductor device according to the twenty-eighth aspect is the second aspect.
In the invention described in Item 5 , the logic circuit may include an EXOR or EXNOR circuit.

That is, the semiconductor device according to the twenty-fifth to twenty- eighth aspects is the semiconductor device according to any one of the tenth to twenty- third aspects, wherein a plurality of transistors of the same conductivity type are used for AND, NAND, OR. , NOR,
A logic circuit such as EXOR or EXOR may be provided.

Therefore, by using transistors of the same conductivity type, it is possible to reduce the number of manufacturing steps, to reduce the cost, to implement high-density mounting, and to obtain a logic circuit capable of obtaining an appropriate output potential. it can.

The semi-developing device according to claim 29 is characterized by claim 1
20. The semiconductor device according to claim 17 , wherein the semiconductor device has a ninth transistor of the same conductivity type as the first to fourth transistors, and at least one of the output means or the inverted output means is provided with the ninth transistor. It may be connected to the gate of the ninth transistor.

That is, at least one of the output means and the inverted output means of the semiconductor device according to claim 10 or 17 is connected to the gate of the ninth transistor.

Therefore, the present invention can be applied to, for example, a tri-state circuit for switching the ninth transistor by using the output potential from the output means or the inverted output means of the semiconductor device.

A display driving device according to a thirtieth aspect of the present invention is a display driving device including a plurality of latch circuits formed on an insulating substrate, wherein each of the latch circuits receives a high potential at an input terminal. A first transistor of a conductivity type, a second transistor having the same conductivity type as the first transistor to which a low potential is input to an input terminal, and an output terminal of the first and second transistors; Output means, non-inverted signal supply means connected to the gate of the first transistor, inverted signal supply means connected to the gate of the second transistor, and output terminals of the first and second transistors Between the first and second inversion signal supply means or the first
And an output voltage compensating circuit connected between the output terminal of the second transistor and the non-inverted signal supply means, wherein the output voltage compensation circuit comprises the inverted signal supply means or the non-inverted signal supply means. A third transistor having the same conductivity type as the first and second transistors whose input terminals are connected to the inverted signal supply means, an output terminal of the third transistor, and an output terminal of the first and second transistors; And a capacitance means connected to the

That is, in the plurality of latch circuits constituting the display driving device, the high potential is input to the input terminal of the first transistor, the low potential is input to the input terminal of the second transistor, and the first and second latches are connected. Output means is connected to the output terminal of the transistor, the non-inverted signal supply means is connected to the gate of the first transistor, the inverted signal supply means is connected to the gate of the second transistor, the output means and the inverted signal An output voltage compensating circuit is connected between either the supplying means or the non-inverting signal supplying means, and the output voltage compensating circuit connects the input terminal of the third transistor to the inverting signal supplying means or the non-inverting signal supplying means. Is connected to this third
Is connected between the output terminal of the first transistor and the output terminal of the first and second transistors.

Therefore, since the display driving device is constituted by using the latch circuit including the semiconductor device of the present invention, it is possible to perform the display driving reliably and accurately with an appropriate output potential.

A display driving device according to a thirty- first aspect is a display driving device including a plurality of inverter circuits formed on an insulating substrate and connected to each other, wherein each of the inverter circuits has a high potential at an input terminal. Input, one conductivity type first
A second transistor of the same conductivity type as the first transistor, to which a low potential is input to an input terminal; output means connected to output terminals of the first and second transistors; Non-inverted signal supply means connected to the gate of the first transistor, inverted signal supply means connected to the gate of the second transistor, output terminals of the first and second transistors, and the inverted signal supply And an output voltage compensating circuit connected between the output terminal of the first and second transistors and the non-inverting signal supply means. A third transistor having the same conductivity type as the first and second transistors, the input terminals of which are connected to the inversion signal supply means or the non-inversion signal supply means; and a third transistor. Characterized in that it comprises a connected capacitor means output terminal and the output terminal of said first and second transistors of the register.

That is, in a plurality of cascaded inverter circuits constituting a display driving device, a high potential is input to an input terminal of a first transistor, a low potential is input to an input terminal of a second transistor, and output means Are connected to the output terminals of the first and second transistors, the non-inverted signal supply means is connected to the gate of the first transistor, and the inverted signal supply means is connected to the gate of the second transistor. An output voltage compensation circuit is connected between the inversion signal supply means and the non-inversion signal supply means, and the output voltage compensation circuit is connected to the inversion signal supply means or the non-inversion signal supply means by a third signal. An input terminal of the transistor is connected, and capacitance means is connected between the output terminal of the third transistor and the output terminals of the first and second transistors.

Therefore, since the display driving device is configured by using the inverter circuit including the semiconductor device of the present invention, the display driving can be reliably and accurately performed with an appropriate output potential.

[0082]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor device of the present invention and a display driving device using the same will be described below with reference to the drawings.

FIGS. 1 to 39 show an embodiment of the semiconductor device of the present invention and a display driving device using the same. In this embodiment, only a PMOS is used as a transistor of the same conductivity type used in the semiconductor device. It was implemented.

1 to 39 , FIG. 1 shows a basic circuit configuration of the semiconductor device of the present invention, and FIGS. 2 to 15 show inverter circuits formed by combining the circuits of FIG. FIGS. 16 to 20 show a latch circuit formed using a circuit and a plurality of P-type transistors, and an AND circuit formed using the circuit in FIG . 1 and a plurality of P-type transistors.
(And NAND) shows a circuit in FIGS. 21 to 26, O
The R (and NOR) circuit is shown in FIGS.
FIGS. 29 and 30 show an XOR (and EXNOR) circuit . FIGS. 31 to 31 show tristate circuits formed by using the circuit of FIG. 1, a plurality of P-type transistors, and a plurality of voltage sources (VC, VL, VH) . 34 shows an inverter circuit described above, the latch circuits, and (and NAND) circuit 35 and a liquid crystal drive circuit having a drain driver and a gate driver configured using a tristate circuit,
39 to FIG .

(Basic Inverter Circuit) FIG. 1 is a diagram showing a basic circuit configuration of an inverter of a semiconductor device according to the present invention.
As shown in FIG. 1, a semiconductor device 11 of the present invention includes three P-type insulated gate (hereinafter referred to as P-type transistors) transistors 12, 13, and 14 and one capacitor 15.
It is composed of Here, the P-type transistor is a P-type field-effect thin film transistor (MIS-FET) formed of a P-type gate insulating film formed of a silicon oxide film or another insulating film such as a silicon nitride film. Each of the three P-type transistors 12, 13, and 14 has a semiconductor layer formed of non-single-crystal silicon such as amorphous silicon or polysilicon. The sources and drains of the P-type transistor 13 and the P-type transistor 14 are connected in series between the power supply potential (Vdd) and the ground potential (VGND), and the input (IN) is connected to the gate of the P-type transistor 13. A positive logic or a negative logic is applied from the side, and an inverting input (ト ラ ン ジ ス タ
The logic inverted from the input (IN) is applied from the IN) side.

If only the above configuration is used, it is the same as the non-ratio inverter circuit shown in the conventional example of FIG. 35 , in which "0" is input to the input (IN) and "1" is input to the inverted input ($ IN). Is input, "1" is output from the output end (OUT).
On the other hand, when "1" is input to the input (IN) and "0" is input from the inverting input ($ IN), a low level that cannot be sufficiently reduced from the output (OUT) is output. "0" is output. This is because when the P-type transistor 14 is turned on, the low potential side is raised by the threshold voltage.

Therefore, according to the present invention, the inverting input (￣IN) of the semiconductor device 11 shown in FIG.
14 and an output voltage compensating circuit is connected between
The low potential output from the type transistor 14 is suppressed from rising from the ground potential (VGND).

The output voltage compensating circuit is a P-type transistor 1
A P-type transistor 12 and a capacitor 15 of the same conductivity type as the P-type transistors 3 and 14 are connected. The source of the P-type transistor 12 is connected to the inverting input (入 力 IN), the drain is connected to the gate of the P-type transistor 14, and
5 is connected to the connection point on the output side of the P-type transistors 13 and 14, and the other electrode is connected to the P-type transistor 12
Is connected to the connection line between the drain of the P-type transistor 14 and the gate of the P-type transistor 14. The gate of the P-type transistor 12 is connected to the ground potential (VGND).
As described above, by combining the P-type transistor 12 and the capacitor 15 with a conventional ratioless inverter circuit, the low level output from the output terminal (OUT) can be reduced to the same potential as the ground potential. Became.

Further, the above-mentioned three transistors 12,
Since the transistors 13 and 14 can be constituted by transistors of the same conductivity type (here, P-channel type), the number of impurity implantation steps and the number of masks can be reduced, and the manufacturing steps can be simplified to reduce costs. Can be.

Further, the P-type transistor 13 serving as a switching transistor is connected to the power supply side, and the P-type transistor 14
Is provided on the ground side to input both positive logic and negative logic to each gate, so that leakage current is reduced and power consumption can be reduced.

(Inverter Circuit) FIG. 2 is a diagram showing a configuration of an inverter circuit 21 which combines two inverter basic circuits shown in FIG. 1 and outputs a negative of both positive logic and negative logic.

First, the configuration will be described.

As shown in FIG.
Are P-type transistors Q1, Q2, Q3 and a capacitor C
1 and an inverter basic circuit 23 composed of P-type transistors Q4, Q5, Q6 and a capacitor C2.

In the inverter basic circuit 22, an input (IN) is input to the gate of the P-type transistor Q2, and an inverted input (￣IN) is input to the gate of the P-type transistor Q3 via the P-type transistor Q1. In addition, inverter basic circuit 2
3 is connected to the gates of the P-type transistors Q5 and Q6.
The input (IN) and the inverted input (￣IN) are input to the inverter basic circuit 22 in reverse.

Next, the operation will be described.

The inverter circuit 21 has, for example, an input (I
N) is input with negative logic "0" and the inverted input (@IN) is input with positive logic "1".
P-type transistor Q2 is turned on, "1" is output (OUT) from power supply Vdd, and P-type transistor Q3 is turned off. Conversely, in the inverter basic circuit 23, the P-type transistor Q5 is turned off and the P-type transistor Q6 is turned on, and the ground potential “0” is output as the inverted output (￣OUT).

Further, in the inverter circuit 21, when the logic of the input (IN) and the inverted input ($ IN) are opposite to the above, "0" is output from the output (OUT) side,
“1” is output from the inverted output (￣OUT) side.

As described above, when both the positive logic and the negative logic are input as the input and the inverted input, the inverter circuit 21 of the present embodiment outputs the negation thereof as the output and the inverted output.

Further, the inverter circuit 21 of the present embodiment
Is the P-type transistor Q3 of the inverter basic circuit 22 or the P-type transistor Q6 of the inverter basic circuit 23.
Is turned on, the ground potential is output as an output or an inverted output. However, as shown in FIG. 2, the gates of the P-type transistors Q3 and Q6 are connected to the P-type transistor Q1.
And Q4 are provided. A capacitor C having a predetermined capacitance is provided between the P-type transistor Q1 and the output terminal and between the P-type transistor Q4 and the inverted output terminal.
1 · C2 is arranged.

Therefore, when a low level is output as an output or an inverted output, it is possible to prevent the low level from rising, and it is possible to prevent the appropriate Vdd level from being "1" and the ground potential from being "0". Can be output as an output or an inverted output.

FIG. 3 is a diagram showing symbols of the inverter circuit 21 shown in FIG. 2. The input side of the inverter circuit 21 has an input (IN) and an inverted input (￣IN) obtained by negating the input (IN).
Is input, an output (OUT) in which the logic of the input is inverted from the output side and an inverted output (￣OUT) that negates the output.
Is output.

FIG. 4 is a diagram showing a circuit configuration in which three symbols of the inverter circuit 21 of FIG. 3 are connected in series, and corresponds to the circuit configuration of the conventional example shown in FIG .
The signal level of each section of the conventional example shown in FIG. 42 described above is such that when the low level is output from the inverter circuit at each stage, the output low level slightly increases from the ground potential (VGND). When three are connected in series and operated, the accumulated result of those rises becomes the final output level of the inverter circuit, and the output low level is significantly higher than the ground potential (VGND). Output level could not be obtained.

FIG. 5 is a diagram showing a simulation result of input / output signals when the inverter circuit of FIG. 4 is operated. The P used in the simulation in this specification
Transistor has a transistor size L = 4 μm,
W = 4 μm, threshold voltage is −3 V, field effect mobility is 40 cm 2 / V · S, and gate electrode capacitance is 1.22 × 10 −
14F, the S / D (source / drain) resistance is 200Ω, and the substrate voltage is the same as the power supply voltage (Vdd). The capacitors used for the inverter basic circuit are:
A capacitor having a capacitance of 0.2 pF is used.

Therefore, as shown in FIG. 5, in the inverter circuit of the present embodiment, even when three inverter circuits are connected in series, there is no loss in the output level such that the low level increases, and the inverter circuit is always appropriate. Ground potential (VGND)
And the power supply level (Vdd) can be output (OUT) or inverted output (￣OUT).

Further, the inverter circuit of the present embodiment has no output level loss as described above, and has the power supply voltage (Vd
d) It was confirmed that the device operates at 12 V and an operation frequency of 100 KHz, and that there is no DC leakage current and only a transition current flows. For this reason, for example, it has been found that the device has sufficient characteristics with respect to the operation speed and current consumption when used as a driving circuit of a TFT-LCD.

Next, FIGS. 6 to 9 are diagrams showing circuit configuration examples in which the inverter circuit 21 of FIG. 2 is modified. As in FIG. 2, P-type transistors Q1 to Q6 and a capacitor C
1, C2 is used, but the input terminal of each P-type transistor or the connection relation of the gate is changed.

That is, the transistor Q3 of the inverter circuit 21 shown in FIG. 2 is turned on to output a low level when the inverted input signal (￣IN) is at the low level.
Therefore, the electrode of the input terminal where the transistor Q3 is grounded does not need to be always at the low level, and only needs to be low when the inverted input signal (￣IN) is at the low level.

Therefore, as shown in FIG. 6, there is no problem if the input terminal of the transistor Q3 is connected not to the ground but to the inverting input terminal (@IN) which becomes low level when the transistor Q3 is turned on. And exactly the same operation is performed.

For transistor Q6 in FIG. 6, for the same reason as described above, the input terminal grounded to ground is connected to the input terminal (IN) which goes low when transistor Q6 is turned on. By doing so, the number of grounding points is reduced, wiring is simplified, and power consumption can be reduced.

Next, the reason why the transistor Q2 of the inverter circuit 21 shown in FIG.
This is when the input signal (IN) is at a low level. For this reason,
The electrode of the input terminal to which the transistor Q2 is connected to the power supply does not need to be always at the high level, and the input signal (I
Only when N) is at a low level, a high level needs to be input.

Therefore, as shown in FIG. 7, the input terminal of the transistor Q2 is not a power source, but is at a high level when the transistor Q2 is turned on.
IN), there is no problem and the same operation is performed.

For transistor Q5 in FIG. 7, for the same reason as above, the input terminal connected to the power supply is connected to the input terminal (IN) which becomes high level when transistor Q5 is turned on. By doing so, the number of connection points with the power supply is reduced, wiring is simplified, and power consumption can be reduced.

Next, as shown in FIG.
2, Q3, Q5, and Q6 are connected to the input terminal (IN) or the inverted input terminal (￣I
N) does not cause any trouble, and the same operation as that in FIG. 2 can be performed.

Further, the inverter circuit 21 shown in FIG.
In the first embodiment, the gate electrodes of the bootstrap transistors Q1 and Q4 for compensating the gate voltages of the transistors Q3 and Q6 and reliably outputting a low-level signal are grounded, but the transistors Q1 and Q4 are always on. It is not necessary to be in the state, and when the transistor Q3 or Q6 is turned on, a low level may be input to the gate electrode of the P-type transistor Q1 or Q4 to be turned on.

Therefore, as shown in FIG. 9, instead of grounding the gate electrode of the transistor Q1 or Q4 to ground, a transistor is connected to the inverting input terminal (@IN) which becomes low when the transistor Q3 turns on. The gate electrode of Q1 is connected, and the transistor Q6
Input terminal (IN) which becomes low level when is turned on
There is no problem even if the gate electrode of the transistor Q4 is connected to this, and the same operation can be performed.

As a result, the number of connection points of the transistor to the ground and the power supply can be further reduced, so that the wiring can be simplified and the power consumption can be reduced.

Next, FIG. 10 is a circuit diagram in the case where the inverter circuit of the P-type transistor shown in FIG. 2 is constituted by an N-type insulated gate transistor (hereinafter, referred to as an N-type transistor).

Here, the N-type transistor is an N-type field effect transistor (MIS-FET) in which the gate insulating film is formed of another insulating film such as a MOS or a silicon nitride film formed of a silicon oxide film. .

As shown in FIG.
0 is an inverter basic circuit 220 composed of N-type transistors Q11, Q12, Q13 and a capacitor C1.
And an inverter basic circuit 230 composed of N-type transistors Q14, Q15, Q16 and a capacitor C2.

In the inverter basic circuit 220, the input signal (IN) is input to the gate of the N-type transistor Q12 and the inverted input signal ($ IN) is input to the gate of the N-type transistor Q13 via the N-type transistor Q11. The inverter basic circuit 230 includes N-type transistors Q15 and Q15.
The input signal (IN) and the inverted input signal (￣IN) input to the 16 gates are input in reverse to the inverter basic circuit 220.

The input terminals of the transistors Q12 and Q15 and the gate electrodes of the transistors Q11 and Q14 are
A high-level signal is always supplied from the power supply. The input terminals of the transistors Q13 and Q16 are grounded, and a low-level signal is always input.

FIG. 11 shows a known path logic circuit 200.
11 is connected to the N-type inverter circuit 210 of FIG. The path logic circuit 200 is a circuit recently developed for the purpose of low power consumption, high processing capability, and high integration, and includes a large number of N-type transistors Qaα and Q (￣aα) arranged in a network in the column and row directions. )
., Qmλ, Q (￣mλ),... Qzω, Q (￣zω). Each N-type transistor has its gate connected to one of the row address lines a, (￣a),... M, (￣m),... Z, (￣z), and the column address lines α, (￣).
α),... λ, (￣λ),... ω, (￣ω) are connected to input terminals. Each of the N-type transistors has a pair of two output terminals connected to a row address line to which a predetermined signal is input and a row address to which an inverted signal is input. For example, an N-type transistor Qaα
And the output terminals of Q (￣aα) are connected, the output terminals of N-type transistors Qmλ and Q (￣mλ) are connected, and the N-type transistors Qzω and Q (￣zω) are connected.

The N-type inverter circuit 210 is connected to the output terminals (SI) and (￣SI) of such an N-type pass transistor logic network.

FIGS. 12A and 12B are diagrams showing simulation results of the circuit of FIG. FIG.
FIG. 12A shows the waveforms at the output terminals (SI) and (@SI) of the path logic circuit 200 in FIG. 11, and FIG.
Is the output terminal (SO) of the N-type inverter circuit 210, (￣
5 shows the waveform of the signal SO). As shown in FIG.
In the waveform output from the die path logic circuit 200, the high potential Vdd is reduced from 5V. This is a potential drop caused by the output terminals of the N-type transistors constituting the network circuit of the N-type path logic circuit 200 being connected to each other, and is a drop corresponding to the threshold value of the N-type transistor. . However, in the output waveform of the N-type inverter circuit 210, the high potential Vdd has recovered to 5V. Thus, it can be confirmed that the N-type inverter circuit 210 has an effect of preventing the reduction of the high potential Vdd.

Various configurations are conceivable for the configuration of the inverter circuit 210 composed of the N-type transistors shown in FIG. 10, and these are shown in FIGS .

FIGS. 13 to 15 are diagrams showing circuit configuration examples obtained by modifying the inverter circuit 210 of FIG. FIG.
Similarly to 0, N-type transistors Q11 to Q16 and capacitors C1 and C2 are used, but the connection relationship between the input terminals or gates of each N-type transistor is changed.

That is, the inverter circuit 210 shown in FIG.
The transistor Q12 turns on to output a high level when the input signal (IN) is at a high level.
Therefore, the input terminal of the transistor Q12 connected to the power supply need not always be at the high level, and only needs to be high when the input signal (IN) is at the high level.

Therefore, as shown in FIG. 13, the input terminal of transistor Q12 is not
When the switch 12 is turned on, there is no problem even if it is connected to the input terminal (IN) which is at a high level, and the same operation is performed.

For the transistor Q15 in FIG. 13, for the same reason as described above, the input terminal connected to the power supply is changed to the inverted input terminal (端 IN) which becomes high when the transistor Q15 turns on. , The number of connection points to the power supply is reduced, the wiring is simplified, and power consumption can be reduced.

Similarly, the inverter circuit 2 shown in FIG.
The ten transistors Q13 are turned on to output a low level when the inverted input signal (￣IN) is at a high level. Therefore, the electrode at the input terminal where the transistor Q13 is grounded does not need to be always at the low level, and only needs to input high when the inverted input signal (信号 IN) is at the high level. Become.

Next, as shown in FIG. 14 , the input terminals of the transistors Q12, Q13, Q15 and Q16 are connected to the input terminal (IN) and the inverted input terminal (￣IN) for the same reason as described above. Even if they are connected, there is no problem, and the same operation as that in FIG. 10 can be performed.

Further, the inverter circuit 2 shown in FIG.
In FIG. 10, the gate electrodes of the bootstrap transistors Q11 and Q14 for compensating the gate voltages of the transistors Q12 and Q15 and reliably outputting a high-level signal are connected to the power supply.
The transistor Q14 does not need to be always on, and when the transistor Q12 or Q15 is turned on, a high level may be input to the gate electrode of the N-type transistor Q11 or Q14 to be turned on.

Therefore, as shown in FIG. 15 , instead of connecting the gate electrode of the transistor Q11 or Q14 to the power source, the transistor Q12 is connected to a high level when the transistor Q12 is turned on.
11 are connected to each other and the transistor Q15
The inverting input end (￣
Even if the gate electrode of the transistor Q14 is connected to IN), there is no problem and the same operation can be performed.

As described above, also in the case of the inverter circuit 210 composed of N-type transistors, the configuration shown in FIGS. 13 to 15 can further reduce the number of connection points of the transistors to the ground and the power supply. Wiring is simplified, and power consumption can be reduced.

(Latch Circuit) FIG. 16 is a configuration diagram of a latch circuit 51 for temporarily holding data by combining the inverter basic circuit shown in FIG.

First, the configuration will be described.

A latch circuit 51 shown in FIG . 16 has a switching element between an inverter circuit formed by using two inverter basic circuits 52 and 53 and an input terminal (I) and an inverting input terminal (￣I). P-type transistor Q2
1 and Q22, and the gates of the P-type transistors Q21 and Q22 receive an inverted clock signal (信号 clk) for switching from an inverted control signal input terminal (端 L).

The output (￣OUT) from the output terminal (￣O) of the inverter basic circuit 52 is supplied to the drain side of the P-type transistor Q22 by the feedback loop, and the P-type transistor Q2
4 are connected.

The output (OUT) from the output terminal (O) of the inverter basic circuit 53 is connected to the drain of the P-type transistor Q21 through a P-type transistor Q23 as a switching element by a feedback loop. Have been.

The above-mentioned P-type transistors Q23 and Q24
Is configured to receive a clock signal (clk) for controlling switching from a control signal input terminal (L).

As described above, the latch circuit 51 shown in FIG.
Is obtained by newly adding four P-type transistors Q21 to Q24 to the inverter circuit shown in FIG. The P-type transistors Q21 to Q24 operate the latch circuit 51 in a through operation or in a latch operation according to an external control signal input terminal (入 力 L) and a control signal from the control signal input terminal (L). Is switched.

FIG . 17 is a diagram showing symbols of the latch circuit 51 shown in FIG. 16, in which an input signal (IN) is applied to an input terminal (I) and an inverted input signal (（I) is applied to an inverted input terminal (￣I). ￣
IN) is input, the clock signal (clk) input to the control signal input terminal (L) and the inverted clock signal (Δclk) input to the inverted control signal input terminal (ΔL) An output signal (OUT) and an inverted output signal (￣OUT) corresponding to the selected through operation and latch operation are output from the output terminal (O) and the inverted output terminal (￣O).

Next, the operation will be described.

FIG . 18 is a diagram showing a simulation result of input / output signals when the latch circuit 51 is operated.
FIG. 3A shows a clock signal (cl) input to a control signal input terminal (L) and an inverted control signal input terminal (￣L).
k) and an inverted clock signal (￣clk). FIG. 2B shows the input signal (IN) input to the input terminal (I) and the inverted input terminal (￣I) and the inverted input signal. Signal (@IN)
FIG. 2C is a diagram showing an output signal (OUT) and an inverted output signal (￣OUT) output from the output terminal (O) and the inverted output terminal (￣O).

In the latch circuit 51 of this embodiment, the clock signal (clk) input to the control signal input terminal (L) is high “1”, and the inverted clock signal of the inverted control signal input terminal (￣L) is output. When (@clk) is low "0", a through state is established. Conversely, the clock signal (clk) input to the control signal input terminal (L) is low "0" and the inverted control signal input terminal. When the inverted clock signal (￣clk) of (￣L) is high “1”, the latch state is established.

The above-mentioned through state means that the input end (I)
Is output as an output signal (OUT) of the output terminal (O) as it is, and the inverted input terminal (￣
The state in which the inverted input signal (信号 IN) from I) is output as it is as the inverted output signal (￣OUT) at the inverted output end (￣O).

The above-mentioned latch state means that the output state before the latch is maintained.

More specifically, as shown in FIG.
When the clock signal (clk) is high “1” and the inverted clock signal (￣clk) is low “0”, the through state is established, and the P-type transistors Q23 and Q24 of FIG. Q22 is turned on.

Therefore, as shown in FIG. 18B, when the input signal (IN) is "0" and the inverted input signal (@IN) becomes "1", the P-type transistors Q27 and Q29 are turned off. , P-type transistors Q26 and Q30 are turned on, so that a through state is output, and "0" is output as the output signal (OUT) and "1" is output as the inverted output signal (@OUT).

Next, the clock signal (clk) is low "0" and the inverted clock signal (@clk) is high "1".
In the case of, the latch state is established, and the P-type transistors Q23 and Q24 in FIG. 16 are turned on, and the P-type transistors Q21 and Q22 are turned off.

Therefore, regardless of the input signals at the input terminal (I) and the inverted input terminal (端 I), “0” of the output signal (OUT) in the conventional through state shown in FIG. Through the P-type transistor Q23, the P-type transistor Q26
18 and Q30 are turned on, and the inverted output signal (反 転 OUT) “1” turns off the P-type transistors Q27 and Q29 via the P-type transistor Q24 .
As shown in (1), the previous output state is maintained, the output signal (IN) is "0", and the inverted input signal (@IN) "1" is output as it is.

As described above, the latch circuit shown in FIG.
The gates of the four P-type transistors Q21 to Q24 are switched between a through operation and a latch operation according to an external control signal. This circuit has two logics, positive logic and negative logic.
Inverter circuit composed of two inverter basic circuits 52 and 53 (see FIG. 2)
The latch function can be realized by using only one.

Further, the latch circuit according to the above-described embodiment is similar to that of FIG.
, The loss of the output level is eliminated, the DC leakage current is eliminated, and the power consumption can be reduced.

In the latch circuit 51, the circuit is constituted by P-type transistors. However, the present invention is not limited to this. The circuit may be constituted by N-type transistors instead of P-type transistors.

FIG . 19 is a circuit diagram of FIG. 1 using a P-type transistor .
6 is a circuit diagram in which the inverter circuit of the latch circuit 51 of FIG.

A latch circuit 51 shown in FIG . 19 has a P-type transistor Q
21 to Q24, and the clock L and the inverted clock {
The gate is controlled by L.

Here, as a variation having a circuit configuration other than the latch circuit 51 shown in FIG. 16 , the inverter circuit 21 shown in FIG. 19 may be configured using the inverter circuits shown in FIGS. Good.

When the above configuration is adopted, the number of connection points between the power supply and the ground for each P-type transistor of the inverter circuit 21 is reduced, so that the circuit wiring is simplified and the power consumption can be reduced. .

FIG. 20 is a circuit diagram in which a latch circuit 61 is formed using N-type transistors and an inverter circuit is replaced with a symbol.

In the latch circuit 61 shown in FIG . 20 , N-type transistors Q21 to Q24 are provided at the input / output terminals of the inverter circuit 210 shown in FIG. 10, respectively, and the gate is controlled by the clock L and the inverted clock $ L. Things.

Here, as a variation of the circuit configuration of the latch circuit 61 using an N-type transistor, FIG.
13 to 1 described above in the inverter circuit 210 of FIG.
The configuration may be made using up to five inverter circuits.

In the latch circuit 61 employing the inverter circuit having the above configuration, the number of connection points between the power supply and the ground for each N-type transistor of the inverter circuit 210 is reduced, so that the wiring of the circuit is simplified and the consumption is reduced. Power can now be reduced.

(And Circuit) FIG. 21 is a block diagram of an AND circuit for generating a logical product and its negation by combining the inverter basic circuit of FIG. 1 and a P-type transistor.

First, the configuration will be described.

The AND / NAND circuit 62 shown in FIG . 21 includes a logic circuit 55 and inverter basic circuits 52 and 53.

The logic circuit 55 uses the four P-type transistors Q31 to Q34 to generate a logical product of the input and its negation. That is, when there are two inputs a and b, the inversions a (￣a) and b (￣
Also enter b). P-type transistors Q21 and Q22 are connected in series between the input end of a and ground, and a P-type transistor is connected between the input end of inverted a and the power supply (Vdd). Q33 and Q34 are connected in series.

The gate of each of the P-type transistors Q32 and Q34 receives the signal "b" and performs switching.
Inversion b is input to the gates of the type transistors Q31 and Q33 to perform switching. Then, according to the result of the switching, the P-type transistors Q31 and Q31
32, and between the P-type transistors Q33 and Q34, a high-level "1" or low-level "0" signal is output.

However, with only the P-type transistors Q31 to Q34, a low-level output is lost by the amount corresponding to the threshold voltage of the transistor. Therefore, in the AND circuit 61 of the present embodiment, the inverter basic circuit 52,
The output level is corrected by adding the same inverter circuit as that shown in FIG. That is, the basic inverter circuits 52 and 53, FIG. 16
Has the same configuration as that of the inverter basic circuits 52 and 53 shown in FIG. 1, and has a function of lowering the output low potential until it becomes equal to the ground potential VGND.

Next, the operation will be described.

The input a is "0" (the inverted a is "1")
When b is "0" (the inverted b is "1"), as shown in FIG. 21 , the P-type transistors Q31 and Q33 are turned off and Q32 and Q34 are turned on. The type transistors Q26 and Q30 are turned off, but the P-type transistors Q27 and Q29 are turned on, so that the AND output is "0" and the NAND output is "1".

Similarly to the above, if the input a is "0" (a inverted "1") and b is "1" (b inverted "0"), the AND output is "0", The NAND output becomes “1”.

When the input a is "1" (the inverted a is "0") and b is "0" (the inverted b is "1"),
The AND output is “0” and the NAND output is “1”.

Further, when the input a is "1" (the inverted a is "0") and b is "1" (the inverted b is "0"),
The AND output is “1” and the NAND output is “0”.

[0174] Figure 22 is a diagram showing a symbol of the AND circuit 61 of FIG. 21, FIG. 23, the AND circuit 6 of FIG. 22
FIG. 3 is a diagram showing a simulation result of AND output and NAND output for each input pattern in FIG.

As shown in FIG . 23 , the AND circuit determines a predetermined logical product (AND) and its negation (NAN) according to the combination of the input a, inverted a, b, and inverted b.
D) is output. Then, when a low level is output by an AND output or a NAND output, the output level is corrected by combining the inverter basic circuits 52 and 53 as in the present embodiment . Therefore, as shown in FIG. A potential equivalent to the ground potential (VGND) can be reliably output.

Further, the AND circuit 61 of the above embodiment is
Since the inverter basic circuit shown in FIG. 1 is employed, DC leakage current is eliminated and power consumption can be reduced.

In the AND circuit 61, a circuit is formed using P-type transistors. However, an N-type transistor may be used instead of the P-type transistor.

[0178] Figure 24 is a circuit diagram showing a modification of the AND circuit consisting of P-type transistor shown in FIG. 21.

The AND circuit 61 shown in FIG . 21 comprises inverter basic circuits 52 and 53, and a logic circuit 55 including P-type transistors Q31 to Q34 at the preceding stage. The AND circuit 310 of FIG. 24 has the same inverter circuit portion as the AND circuit 62 and the inverter circuit 53 of the AND circuit 62 of FIG. 21 , but differs in the connection relationship of the preceding logic circuit.

That is, the transistor Q3 shown in FIG.
1 and Q32, the source and the drain of which are connected in series between the input terminal a and the ground, and the transistors Q31 and Q32
By applying the inverted input signal ￣b and the input signal b to the 32 gate electrodes, the output signal a or the low level ground output signal is input to the inverter circuit. Also,
The transistors Q33 and Q34 have a source and a drain connected in series between an inverting input terminal #a and a power supply, and have an inverting input signal #b connected to the gate electrodes of the transistors Q33 and Q34.
And the input signal b, the inverted input signal ￣a or the high-level power supply input signal is input to the inverter circuit.

However, the input terminal of the transistor Q32 in the logic circuit shown in FIG. 24 does not need to be always at a low level, and it is sufficient that a low level is input only when the transistor Q32 is turned on. Therefore, as shown in FIG. 24 , there is no problem even if the input terminal of the transistor Q32 is connected not to the ground but to the input terminal b which becomes a low level when the transistor Q32 is turned on . It can be performed.

The transistor Q in the logic circuit shown in FIG.
The input terminal of the input terminal 34 does not need to be always at a high level, but may be any input terminal that is input at a high level only when the transistor Q34 is turned on. Therefore, as shown in FIG. 24 , there is no problem if the input terminal of the transistor Q34 is connected not to the power supply but to the inverting input terminal #b which becomes a high level when the transistor Q34 turns on .
1 can perform exactly the same operation.

[0183] AND circuit 320 in FIG. 25 is a circuit diagram showing another modification of the AND circuit consisting of P-type transistor shown in FIG. 21.

[0184] When the FIG. 25 were compared between FIG. 24, the configuration of the logic circuit of the preceding stage portion of the inverter circuit is similar to Figure 24, the circuit arrangement of FIG. 25, P-type transistor of the inverter circuit Q26 May be connected to the input terminal from the logic circuit which goes to a high level when the transistor Q26 is turned on, instead of the power supply connected to the input terminal. Further, instead of the power supply connected to the input terminal of the P-type transistor Q29 of the inverter circuit, a transistor Q
What is necessary is just to connect to the input terminal from the logic circuit which becomes high level when 29 turns on.

FIG . 26 is a circuit diagram of an AND circuit 330 composed of N-type transistors.

The AND circuit 330 shown in FIG . 26 comprises an N-type inverter circuit composed of inverter basic circuits 220 and 230 and a logic circuit composed of transistors Q31 to Q34 in the preceding stage.

The input terminal of the transistor Q13 of the inverter basic circuit 220 is normally grounded so that a low level is input. However, for the same reason as described above, the low level is set only when the transistor Q13 is turned on. Even if it is connected to the input end of a logic circuit, the operation does not change.

In the logic circuit of the AND circuit 330 shown in FIG. 26 , the input terminal of the transistor Q32 in the logic circuit shown in FIG.
32 is connected to the input terminal b so that a low level is input when the transistor 32 turns on. Instead of the input terminal of the transistor Q34 being connected to the power supply, the transistor Q34
Is connected to the inverting input terminal #b so that a high level is input when the switch turns on.

[0189] (OR circuit) 27 shows the OR / NOR circuit for outputting the negative logical and logical sum constituted only P-type transistor, FIG.
FIG. 28 is a diagram showing symbols of the OR / NOR circuit.

The OR / NOR circuit 64 includes a logic circuit 56,
It is composed of inverter basic circuits 52 and 53,
The circuit configuration of the inverter basic circuits 52 and 53 is shown in FIG.
Inverter basic circuits 52 and 5 of latch circuit 51 of No. 6
3, and it is the same as the basic inverter circuits 52 and 53 of the AND / NAND circuit 61 of Figure 21. Logic circuit 5
The circuit 6 is configured to output a logical sum signal of the signals a, #a, b, and #b and its inverted signal by four transistors Q41 to Q44. Output terminals of P-type transistors Q43 and Q44 of the logic circuit 56 are connected to the source of the P-type transistor Q25 of the inverter basic circuit 52 and the gate of the P-type transistor Q29 of the inverter basic circuit 53. The output terminals of P-type transistors Q41 and Q42 are connected to the gate of P-type transistor Q26 of inverter basic circuit 52 and the source of P-type transistor Q28 of inverter basic circuit 53.

In the output waveform output from such an OR / NOR circuit 64, the potential on the low potential side can be made substantially the same as the ground potential. In this case, the inverter basic circuits 52 and 53 constituting the OR / NOR circuit 64 can also be modified as shown in FIGS.

(Exclusive OR Circuit) FIG. 29 shows an EXOR / EXNOR which outputs an exclusive OR composed of only P-type transistors and its NOT logic.
FIG. 30 is a diagram showing symbols of the EXOR / EXNOR circuit.

EXOR / EXNOR circuit 6 shown in FIG .
5 has the inverter basic circuits 52 and 53 shown in FIG . 21 and FIG . This EXOR / EXNO
R circuit 65 is connected to AND / NAND circuit 61 and O
The only difference from the R / NOR circuit 64 is the logic circuit 57. The logic circuit 57 has four P-type transistors Q45 to Q48, and each of the P-type transistors Q45 to Q48 is controlled by the signal a input to the gate or the inverted signal ￣a thereof. In any of the P-type transistors Q45 to Q48, the signal b or .SIGMA.b is input to the source, the signal a is input to the gate, and the signal b is input to the source.
The inverted signal ￣a is input to the drain and the gate of
Transistor Q45 having inverted signal ￣b input to its source
Is the source of transistor 25 in inverter basic circuit 52 and Q in inverter basic circuit 53.
29, the signal a is input to the gate,
Transistor Q47 having inverted source ￣b input to source
The inverted signal ￣a is input to the drain and the gate of
The drain of the transistor Q 46 to which the signal b is input is connected to the transistor Q in the inverter basic circuit 52.
26 and the gate of the transistor Q28 in the inverter basic circuit 53.

Such an EXOR / EXNOR circuit 65
The output waveform output from the low-potential side can be made substantially the same potential as the ground potential VGND. EXOR /
Inverter basic circuit 52 constituting EXNOR circuit 65
And 53 can also be modified in this case as shown in FIGS.

(Tristate circuit) FIG. 31 shows a tristate circuit 7 for generating an AC voltage .
FIG. 1 is a diagram showing an example of the configuration of FIG. The tri-state circuit 71 is used, for example, when driving a liquid crystal by a liquid crystal driving device or the like, because a liquid crystal deteriorates when a DC voltage is applied, so that an AC drive voltage is generated.

First, the configuration will be described.

As shown in FIG . 31 , eight P-type transistors Q51 to Q58 have a predetermined logic based on four input signals a, a (反 転 a), b and b (￣b). Is configured to generate a logical part. The tristate circuit 71 inputs positive logic and negative logic to a and b, respectively, and outputs an AC voltage generated by switching three types of power supply voltages VH, VC and VL from an output c ( (VH>VC> VL). Here, a pass-transistor logic method is used as in the AND circuit of the above embodiment.

For example, when this tri-state circuit is used in a liquid crystal driving device, the input signal a indicates the presence / absence of write data, that is, whether the liquid crystal is driven or not, and b indicates the liquid crystal driving device. It can be used to indicate positive / negative of voltage.

Next, the six P-type transistors Q59 to Q64 and the capacitors C31 and C32 constitute two inverter basic circuits 72 and 73 shown in FIG.
P-type transistors Q65 and Q that actually output a drive voltage
In order to obtain a proper output voltage by sufficiently driving the transistor 66, it functions to correct the output of the logic section constituted by the P-type transistors Q51 to Q58.

The P-type transistors Q65, Q66,
Q67 is a switching transistor for switching the power supply voltages VH, VL, and VC.

FIG . 32 shows the tri-state circuit 7 of FIG.
FIG. 33 shows two input signals a and b input to the tri-state circuit 71 of FIG. 32 and an AC output signal c generated based on the two signals.
FIG. 9 is a diagram showing a simulation result of FIG.

Next, the operation will be described.

The tri-state circuit 71 shown in FIG .
By inputting either positive logic or negative logic to each of a and b, one of VH, VC, and VL is output from c. Actually, as shown in FIGS. 33 (a) and (b), when the inputs a and b change, (c) in FIG.
This generates an alternating signal as shown in FIG.

First, when the input signals a and b are "0", the P-type transistors Q65 and Q66 are turned off,
Since the type transistor Q67 is turned on, Vc is output from c. The input signal a is “0” and b is “1”.
In this case, Vc is output from c in the same manner as described above. This is because if a is “0”, the P-type transistor Q
Since the transistors 51, Q53, Q55, and Q57 are turned off, the P-type transistor Q67 is not affected by the input signal of b.
Is turned on, and Vc is output from c.

When the input signal a is "1", the switching transistor Q67 is turned off, and the logic unit P67 is turned off.
Type transistors Q52, Q54, Q56, Q58 are turned off, and conversely, P-type transistors Q51, Q5
3, Q55 and Q57 are turned on. For this reason, the output voltage from c changes based on the input signal of b.

Therefore, when b is "0", Q61 and Q
63 is turned on, the ground potential VGND is supplied to the gate, and the P-type transistor Q66 is turned on and Q65 is turned off, so that VL is output from c.

When b is "1", Q60 and Q6
4 is turned on, the ground potential VGND is supplied to the gate, and the P-type transistor Q65 is turned on and Q66 is turned off, so that VH is output from c.

As described above, since the tri-state circuit 71 of this embodiment can be constituted only by the P-type transistor and the capacitor, the structure is simplified and the number of steps can be reduced, so that the cost can be reduced.

Further, the tri-state circuit 71 of the above embodiment corrects the output of the logic section composed of the P-type transistors Q51 to Q58 by using the same inverter basic circuits 72 and 73 as in FIG. FIG. 33 (c)
As shown in (1), the problem that the output voltage c, particularly the low level output voltage VL, cannot be sufficiently reduced is solved, and the voltage level in a state where the output voltage c has always been reduced to a predetermined voltage can be output. Became.

FIG. 34 is a block diagram showing another embodiment in which the tristate circuit of FIG. 31 is modified .
The same reference numerals as those in 1 denote the same or corresponding parts.

Therefore, for example, when a tristate circuit of a liquid crystal drive circuit is formed, if the voltage relationship between the output power supply VH and VL is VH> VL, the high (VH) side switching transistor Q65 is sufficient. Even if it is not turned on, the liquid crystal drive is practically acceptable, but it is more problematic that the output voltage level on the low (VL) side does not drop sufficiently without turning on Q66 sufficiently. Become. Under such circumstances, the high side (VH)
It is conceivable to omit the inverter basic circuit 72 shown in FIG. 31 provided for correcting the voltage level applied to the gate of the switching transistor Q65. Figure
Reference numeral 34 denotes a tristate circuit 81 configured based on the above idea.

Since the tri-state circuit of FIG . 34 is configured according to the purpose of use as described above, it does not affect the practical characteristics as compared with the tri-state circuit 71 of FIG. P-type transistors Q53, Q
54, Q59, Q60, Q61 and one capacitor C
31 can be omitted, the circuit configuration can be simplified, and the cost can be reduced.

The tri-state circuits 71 and 81
Now, the circuit is configured using P-type transistors,
An N-type transistor may be used instead of the P-type transistor.

(Liquid Crystal Driving Circuit) FIG. 35 shows a driving circuit integrated TFT-L according to this embodiment .
FIG. 2 is a schematic configuration diagram of a CD 91. This drive circuit integrated type TF
The T-LCD 91 is an LCD (Liquid Crystal Display)
In the display area, a TFT (Thin Film Transistor) serving as a switching element is formed for each pixel on a glass substrate, and a liquid crystal driving circuit including a drain driver (data line driving circuit) and a gate driver (scanning line driving circuit) Are also integrally formed on a glass substrate.

First, the configuration will be described.

As shown in FIG . 35 , the drive circuit integrated type TF
The T-LCD 91 is a liquid crystal display panel (TFT-L) that forms a TFT for each pixel in a display area on a glass substrate 92.
CD) 93, a gate driver 94 for applying a scanning signal to the gate of each TFT of the liquid crystal display panel 93 to create a selected state and a non-selected state, and the gate driver 94
And a drain driver 95 that drives a liquid crystal of each pixel by applying a display signal to the TFT that has been selected.

The above-mentioned liquid crystal display panel 93, gate driver 94 and drain driver 95 are
2 are integrally formed.

[0218] Figure 36 is a partial circuit diagram configured with a drain driver 95 shown in FIG. 35 the latch circuit formed of inverter basic circuit and P-type transistors, AND circuits, and a tristate circuit, FIG. 37, FIG. 36 5 is a timing chart showing signal waveforms of respective units.

The drain driver 95 shown in FIG . 36 includes latch circuits 101, 102, 103,.
1, 112,..., Latch circuits 121, 122,..., Latch circuits 131, 132,.
1, 142....

The latch circuits 101, 102 and 103 are connected to a horizontal clock (X) input from a controller (not shown).
SCL) and the inverted horizontal clock (￣XSCL) are input to the control signal input terminal (L) and the inverted control signal input terminal (￣L) every other phase with opposite phases. When "1" enters the section (L), the input signal is output as a through signal,
When "0" is entered, the previous input signal is latched.

As the input signals to the latch circuit 101, the horizontal synchronizing signal XD and the horizontal synchronizing signal 、 XD are input, and the output signals corresponding to the through state and the latch state are output from the output terminal (O) and the inverted output terminal (￣). O), and is input to the input terminals of the AND circuit 111 and the next-stage latch circuit 102.

Similarly, the output signal of latch circuit 102 is
The signals are input to the input terminals of the AND circuits 111 and 112 and the next-stage latch circuit 103.

The AND circuit 111 receives the output (OUT) of the latch circuit 101 and the inverted output (￣OUT) of the latch circuit 102, and calculates the logical product and its negation by the control signal input of the latch circuit 121. It is input to the end (L) and the inverted control signal input end (） L). AND circuit 112
Similarly, the inverted output (￣OUT) of the latch circuit 102 and the output (OUT) of the latch circuit 103 are input, and the logical product and its negation are inverted with the control signal input terminal (L) of the latch circuit 122. The signal is input to the control signal input terminal (￣L).

The latch circuit 121 and the latch circuit 122
In accordance with the timing of the output signals from the AND circuits 111 and 112, data for each pixel input from a data conversion circuit (not shown) is latched, and the latched data is stored in next-stage latch circuits 131 and 132, respectively. Output.

The latch circuits 131 and 132 output the clock O
The data for each pixel input at the timing of P is latched, and the output is latched to the respective tri-state circuits 141.
And 142.

The tri-state circuits 141 and 142 generate VH, VC and V according to the combination of the input signals from the latch circuits 131 and 132 and the AC signal WF.
By appropriately selecting the three types of power supply voltage L, an alternating display signal is generated. The converted display signal output from the tri-state circuit 141 is:
The AC-converted display signal output to the drain line D1 and output from the tristate circuit 142 is output to the drain line D2.

FIG. 36 only illustrates a part of the configuration of the drain driver 95 that supplies two drain lines. Actually, the above circuits are connected in the horizontal scanning direction according to the number of pixels. It is arranged. This allows
A display signal corresponding to the position can be supplied to each drain line.

As described above, the drain driver 95 composed of the latch circuit, the AND circuit, and the tristate circuit can be composed only of the inverter basic circuit and the P-type transistor, and therefore is composed of complementary transistors. Compared to the case, the transistor structure is simpler, the number of manufacturing steps is reduced, and if a P-type transistor is used for the TFT transistor of the pixel, the drive circuit integrated type TFT-LCD is simultaneously created on the same plane of the glass substrate Therefore, there is an advantage that cost can be reduced.

Further, the drain driver 95 according to the present embodiment
Has a low DC leakage current as in the complementary type,
There is an advantage that it has low power consumption and can keep an appropriate output level, particularly a low level output, sufficiently low.

[0230] FIG. 38 is a detailed block diagram of the gate driver 94 of FIG. 35. The gate driver 94 includes latch circuits 151, 152,..., NOR circuits 161, 162,.
Inverter circuits 171, 172,..., Inverter circuit 18
, 182, and inverter circuits 191, 192,.

A vertical clock YSCL from a controller (not shown) is supplied to each of the cascade-connected latch circuits 151, 1
52 are alternately input to the control terminal L and the inversion control terminal $ L, and the inverted vertical clock @YSCL from the controller (not shown) is supplied to the latch circuits 151 connected in cascade.
152 are alternately connected to the inversion control terminal $ L and the control terminal L, in other words, to the control terminal L or the inversion control terminal $ L to which the vertical clock YSCL is not connected. Each of the latch circuits 151, 152,... Outputs an input signal through when "1" is input to the control terminal L.
When "0" is input, the previous input signal is latched.

The input terminal I of each latch circuit 151 is supplied with a vertical synchronizing signal YD. The vertical synchronizing signal YD is supplied to the vertical clock YSCL and the inverted vertical clock ￣YSCL.
Are sequentially output from the output terminals O of the latch circuits 151, 152,... To the next-stage latch circuits 152, 153,.
61, 162... And the preceding NOR
Are output to the other input terminals of the circuits 161 162.
Are output from the respective NOR circuits 161, 162,... To the corresponding inverter circuits 171, 172,..., And further passed through the corresponding inverter circuits 181, 182,. Are output as gate signals G1, G2,.

FIG . 39 is a diagram showing the timing of the vertical clock YSCL, the inverted vertical clock @YSCL, the vertical synchronizing signal YD, and the gate signals G1, G2,.

As described above, the gate driver 94 constituted by the latch circuit, the NOR circuit and the inverter circuit
As in the case of the drain driver 95, the transistor structure can be simplified by using only the P-type transistor by using the inverter basic circuit of the present invention as compared with the case of using the complementary transistor. Thus, the number of manufacturing steps can be reduced. In particular, if a P-type transistor is used as the TFT transistor of the pixel, the driving circuit integrated TFT-
Since an LCD can be manufactured, cost reduction can be achieved.

Further, the gate driver 94 of this embodiment
Has the advantages of low power consumption similar to the complementary type, and the ability to keep the output at an appropriate level, especially at a low level, sufficiently low.

[0236]

According to the semiconductor device of the first aspect, an appropriate high-potential or low-potential output signal is output according to the signals input from the non-inverting signal supply means and the inversion signal supply means, respectively. Therefore, malfunction can be prevented even when a circuit is formed using this semiconductor device. Further, since the first transistor and the second transistor are formed of one conductivity type, the number of manufacturing steps is reduced, high integration is possible, and cost reduction and high density can be achieved. Further, since the first transistor and the second transistor are alternately switched by the non-inverting signal supply means and the inversion signal supply means, the leakage current is reduced.

[0237] Also, the first or second transistor consisting of one conductivity type, because the output potential is a characteristic that weakens by a threshold amount, the third transistor and the capacitor means, the proper output voltage Compensate.

[0238] According to the semiconductor device according to claims 2 to 5, first, when the second and third transistors are P-type, the input terminal of the first transistor, before the second transistor Since the input terminal or the gate of the third transistor is connected to the inverted signal supply means,
The input terminal and the gate need not always input a high potential or a low potential, and only need to input a high potential or a low potential at a predetermined timing. Can be simplified, and power consumption can be reduced.

[0239] According to the semiconductor device according to claims 6 to 9, first, when the second and third transistors are N-type, the input terminal of the first transistor, the input transistor of Layer 2 Since the end or the gate of the third transistor is connected to the non-inverted signal supply means,
Since the input terminal and the gate need not always input a high potential or a low potential, and only need to input a high potential or a low potential at a predetermined timing, by connecting to the non-inverting signal supply means, Wiring can be simplified and power consumption can be reduced.

According to the semiconductor device of the tenth aspect , the output means and the inverted output are provided by the first and second output voltage compensating circuits in accordance with the signals input from the non-inverted signal supply means and the inverted signal supply means, respectively. Since an appropriate high-potential or low-potential output signal can be output from the means, malfunction can be prevented even if a circuit is formed using this semiconductor device. Further, since the first to fourth transistors are of the same conductivity type, the number of manufacturing steps is reduced, high integration is possible, and low cost and high density can be achieved. In addition, the first and second
The third transistor and the third and fourth transistors are alternately switched by the non-inverted signal supply means and the inverted signal supply means, respectively, so that the leakage current is reduced.

According to the semiconductor device described in the eleventh aspect, the first to fourth transistors each having one conductivity type have a characteristic that the output potential thereof becomes dull by the threshold value. And the first and second capacitance means, an appropriate output potential can be compensated.

[0242] According to the semiconductor device according to claim 12 or claim 16, when the transistor of the first to sixth is a P-type, connected to the input ends of the first and second transistors to the inverted signal supply means In addition, since the input terminals of the third and fourth transistors are connected to the non-inverting signal supply means, it is not necessary to always input a high potential or a low potential to each of the input terminals. , A high potential or a low potential may be input, and by connecting to the inversion signal supply means or the non-inversion signal supply means, wiring can be simplified and power consumption can be reduced.

According to the semiconductor device of the seventeenth aspect , the output means and the inverted output are provided by the first and second output voltage compensating circuits in accordance with the signals input from the non-inverted signal supply means and the inverted signal supply means, respectively. Since an appropriate high-potential or low-potential output signal can be output from the means, malfunction can be prevented even if a circuit is formed using this semiconductor device. Further, since the first to fourth transistors are formed of the same conductivity type, the number of manufacturing steps is reduced, high integration is possible, and low cost and high density can be achieved. Furthermore, the first
The second transistor and the third and fourth transistors are alternately switched by the non-inverting signal supply means and the inversion signal supply means, respectively, so that the leakage current can be reduced.

According to the semiconductor device of the eighteenth aspect, since the first to fourth transistors of the same conductivity type have the characteristic that the output potential becomes dull by the threshold value,
The fifth and sixth transistors and the first and second capacitance means compensate for an appropriate output potential.

[0245] According to the semiconductor device according to claim 19 or claim 23, when the transistor of the first to sixth is an N-type, the input ends of the first and second transistors to a non-inverted signal supply means In addition to the connection, the input terminals of the third and fourth transistors are connected to the inverted signal supply means. Therefore, it is not necessary to always input a high potential or a low potential to each of the input terminals. , A high potential or a low potential may be input, and by connecting to the inversion signal supply means or the non-inversion signal supply means, wiring can be simplified and power consumption can be reduced.

According to the semiconductor device of the twenty-fourth aspect, since the semiconductor device is constituted by transistors of the same conductivity type, the number of manufacturing steps can be reduced, the cost can be reduced, and high-density mounting can be performed. Can be obtained as a latch circuit.

According to the semiconductor device of the twenty- fifth to twenty- eighth aspects, in the semiconductor device of the tenth or seventeenth aspect , AND, NAND, OR, NOR, EXOR are formed by a plurality of transistors of the same conductivity type. , EX
Since a logic circuit such as a NOR circuit is provided, by using transistors of the same conductivity type, the number of manufacturing steps can be reduced, cost can be reduced, high-density mounting can be performed, and an appropriate output potential can be obtained. Logic circuit.

According to the semiconductor device of the twenty- ninth aspect, by using the output potential from the output means or the inverting output means of the semiconductor device and further switching the fifth transistor, for example, a tri-state circuit or the like can be realized. Can be applied.

According to the display driving device of the thirtieth aspect ,
Since the display driving device is configured by using the latch circuit including the semiconductor device of the present invention, the display driving can be reliably and accurately performed with an appropriate output potential.

According to the display driving device of the thirty- first aspect,
Since the display driving device is formed using the inverter circuit including the semiconductor device of the present invention, the display driving can be performed reliably and accurately with an appropriate output potential.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic circuit configuration of an inverter of a semiconductor device of the present invention.

FIG. 2 is a diagram illustrating a configuration of an inverter circuit that combines two of the inverter basic circuits of FIG. 1 and outputs a negative of both positive logic and negative logic;

FIG. 3 is a diagram showing symbols of the inverter circuit of FIG. 2;

FIG. 4 is a diagram showing a state where three symbols of the inverter circuit shown in FIG. 3 are continuously connected;

FIG. 5 is a diagram showing a result of simulation of a signal waveform when the three inverter circuits of FIG. 4 are connected in series and operated.

FIG. 6 is a diagram showing a circuit configuration example in which the inverter circuit of FIG. 2 is modified.

7 is a diagram showing an example of a circuit configuration in which the inverter circuit of FIG. 2 is modified.

FIG. 8 is a diagram showing a circuit configuration example in which the inverter circuit of FIG. 2 is modified.

FIG. 9 is a diagram showing a circuit configuration example in which the inverter circuit of FIG. 2 is modified.

10 is a circuit diagram in the case where the inverter circuit of the P-type transistor illustrated in FIG. 2 is configured by an N-type transistor.

FIG. 11 is a diagram showing a circuit in which the inverter circuit and the pass logic circuit of FIG. 2 are connected.

12 is a diagram showing waveforms of an input signal and an output signal of the inverter circuit of FIG.

FIG. 13 is a diagram showing a circuit configuration example in which the inverter circuit of FIG. 10 is modified.

FIG. 14 is a diagram showing a circuit configuration example in which the inverter circuit of FIG. 10 is modified.

FIG. 15 is a diagram showing a circuit configuration example in which the inverter circuit of FIG. 10 is modified.

FIG. 16 is a configuration diagram of a latch circuit that temporarily holds data by combining the basic circuits of FIG. 1;

FIG. 17 shows a symbol of a latch circuit shown in FIG. 16.

FIG. 18 is a diagram showing a simulation result of input / output signals when a latch circuit is operated.

FIG. 19 is a circuit diagram in which the inverter circuit of the latch circuit of FIG. 16 using a P-type transistor is replaced with a symbol.

FIG. 20 is a circuit diagram in which a latch circuit is formed using N-type transistors and an inverter circuit is replaced with a symbol;

21 is a configuration diagram of an AND circuit that generates a logical product and its negation by combining the basic circuit of FIG. 1 and a P-type transistor.

FIG. 22 is a diagram showing symbols of the AND circuit in FIG . 21 ;

FIG. 23 is a diagram showing simulation results of AND output and NAND output for each input pattern in the AND circuit of FIG . 22 ;

Figure 24 is a circuit diagram showing a modification of the AND circuit consisting of P-type transistor shown in FIG. 21.

FIG. 25 is a circuit diagram showing another modified example of the AND circuit composed of the P-type transistor shown in FIG . 21 ;

FIG. 26 is a circuit diagram of an AND circuit including N-type transistors.

FIG. 27: OR-NOR composed of N-type transistors
Circuit schematic

FIG. 28 is a view showing symbols of the OR / NOR circuit of FIG . 27 ;

FIG. 29 shows an EXOR · E composed of N-type transistors
FIG. 3 is a circuit diagram of an XNOR circuit.

FIG. 30 is a diagram showing symbols of the EXOR / EXNOR circuit of FIG . 29 ;

FIG. 31 is a diagram illustrating a configuration example of a tri-state circuit that generates an AC voltage.

FIG. 32 is a view showing symbols of the tri-state circuit of FIG . 31 ;

FIG. 33 is a diagram illustrating a simulation result of two input signals a and b input to the tri-state circuit of FIG . 32 and an alternating voltage output c generated based on the input signals.

FIG. 34 is a configuration diagram according to another embodiment in which the tri-state circuit of FIG . 31 is modified.

FIG. 35 is a drive circuit-integrated TFT-L according to the present embodiment.
FIG. 1 is a schematic configuration diagram of a CD.

36 is a partial circuit diagram in which the drain driver shown in FIG . 35 includes a latch circuit including a basic circuit and a P-type transistor, an AND circuit, and a tri-state circuit.

FIG. 37 is a timing chart showing signal waveforms at various parts in FIG . 18 ;

38 is a diagram showing the basic circuit and the gate driver shown in FIG .
A latch circuit composed of a type transistor, an AND circuit,
FIG. 3 is a partial circuit diagram including an inverter circuit.

FIG. 39 is a timing chart showing signal waveforms at various points in FIG . 37 ;

FIG. 40 illustrates a structure of a complementary inverter circuit.

FIG. 41 is a non-ratio type in which two PMOSs are used.
The figure which shows the ratioless inverter circuit comprised combining the basic circuit of the bat.

FIG. 42 is a diagram showing signal waveforms at various points during the operation of FIG . 41 .

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Semiconductor device 12, 13, 14 P-type transistor 15 Capacitor 21, 31, 41 Inverter circuit 22, 23 Inverter basic circuit 51 Latch circuit 52, 53 Inverter basic circuit 55, 56, 57 Logic circuit 61 Latch circuit 62 AND circuit 64 OR・ NOR circuit 65 EXOR ・ EXNOR circuit 71,81 Tri-state circuit 72,73 Inverter basic circuit 91 Drive circuit integrated TFT-L
CD 92 Glass substrate 93 Liquid crystal display panel 94 Gate driver 95 Drain driver 101, 102, 103 Latch circuit 111, 112 AND circuit 121, 122 Latch circuit 131, 132 Latch circuit 141, 142 Tristate circuit 151, 152, 153 Latch circuit 161 , 162 NOR circuit 171, 172 Inverter circuit 181, 182 Inverter circuit 191, 192 Inverter circuit 210 Inverter circuit 220, 230 Inverter basic circuit 310, 320, 330 AND circuit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-37336 (JP, A) JP-A-4-357710 (JP, A) JP-A-4-207629 (JP, A) JP-A-3-307 163911 (JP, A) JP-A-62-200820 (JP, A) JP-A-54-87430 (JP, A) JP-A-7-193486 (JP, A) JP-A-4-57924 (JP, U) (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 17/00-17/70 H03K 19/01-19/017 H03K 19/094-19/096

Claims (31)

(57) [Claims] A first transistor having a high potential input to an input terminal thereof; a second transistor having the same conductivity type as the first transistor having a low potential input to an input terminal; Output means connected to the output terminals of the first and second transistors; non-inverted signal supply means connected to the gate of the first transistor; and inversion connected to the gate of the second transistor Input to the signal supply means and the inversion signal supply means or the non-inversion signal supply means
The same as the first and second transistors whose ends are connected.
A third transistor of one conductivity type and the third transistor
And the output of the first and second transistors.
And an output voltage compensating circuit having a capacitance means connected to the input terminal.The output voltage compensating circuit suppresses an increase in a low potential or a decrease in a high potential output from the output means. Characteristic semiconductor device. 2. The method according to claim 1, wherein
And the second transistor is P-type.
Semiconductor device. 3. The method according to claim 2, wherein the first
The input terminal of the transistor is connected to the inverted signal supply means.
A semiconductor device characterized by being performed. 4. The invention according to claim 2, wherein the second
The input terminal of the transistor is connected to the inverted signal supply means.
A semiconductor device characterized by being performed. 5. The invention according to claim 1, wherein the third
The gate of the transistor is connected to the inverted signal supply means.
A semiconductor device characterized by being performed. 6. The method according to claim 1, wherein
And the second transistor is N-type.
Semiconductor device. 7. The method according to claim 6, wherein the first
An input terminal of the transistor is connected to the non-inverting signal supply means.
A semiconductor device characterized by being connected. 8. The invention according to claim 6, wherein the second
An input terminal of the transistor is connected to the non-inverting signal supply means.
A semiconductor device characterized by being connected. 9. The method according to claim 1 , wherein the third
The gate of the transistor is connected to the non-inverting signal supply means.
A semiconductor device characterized by being connected. 10. One conductivity type in which a high potential is input to an input terminal.
And a low potential at the input end of the first and third transistors
Input, same as the first and third transistors
Second and fourth transistors of conductive type , connected to the output terminals of the first and second transistors;
Output means connected to the output terminals of the third and fourth transistors.
Output means for outputting a signal having a polarity opposite to that of the output means.
Means, non-inverting signal supply means connected to the gates of the first and fourth transistors, and means connected to the gates of the second and third transistors
Inverted signal supply means, and output terminals of the first and second transistors and the inverted signal
A first output voltage compensating circuit connected to the signal supply means;
And the output terminals of the third and fourth transistors and the non-
Output voltage compensation connected between the inverter and the inverted signal supply means
A semiconductor device comprising: a circuit . 11. The first output voltage compensating circuit according to claim 10, wherein the first output voltage compensating circuit has an input terminal connected to the inverted signal supply means.
To the fourth same conductivity type as transistor capacitor of the fifth transitional
And the output terminal of the fifth transistor and the first and second transistors.
Of the measure 1 connected to the output terminal of the transistor
Wherein the second output voltage compensation circuit is input to the non-inverted signal supply means is connected, the first
A sixth transistor having the same conductivity type as the first to fourth transistors.
And registers, and said second output terminal of the sixth transistor 3 and a fourth
Second capacitance means connected to the output terminal of the transistor
A semiconductor device comprising: 12. The invention according to claim 10 or claim 11.
Wherein the first to fourth transistors are P-type.
A semiconductor device, comprising: 13. The method according to claim 12, wherein:
The input terminals of the two transistors are connected to the inverted signal supply means.
A semiconductor device characterized by being connected. 14. The invention according to claim 12, wherein
The input terminal of the first transistor is connected to the inverted signal supply means.
A semiconductor device characterized by being connected. 15. The method according to claim 12, wherein
4 is connected to the non-inverting signal supply means.
A semiconductor device which is connected. 16. The method according to claim 12, wherein
3 is connected to the non-inverting signal supply means.
A semiconductor device which is connected. 17. One conductivity type in which a high potential is input to an input terminal.
And the first and third transistors, each having a low potential input to an input terminal.
Second and fourth transistors of the same conductivity type as the transistor
And data, is connected to the output of the first and second transistors
Connected to the inverted output means and the output terminals of the third and fourth transistors.
An output for outputting a signal having a polarity opposite to that of the inversion output means.
Means connected to the gates of the first and fourth transistors
Connected to the non-inverted signal supply means and the gates of the second and third transistors.
Inverted signal supply means, and output terminals of the first and second transistors and the non- inverted signal
First output voltage compensation connected between the inverted signal supply means
A circuit; an output terminal of the third and fourth transistors;
A second output voltage compensation circuit connected to the signal supply means;
And a road . 18. The invention according to claim 17, wherein said first output voltage compensating circuit has an input terminal connected to said non-inverting signal supply means.
A fifth transistor having the same conductivity type as the first to fourth transistors.
And register, the fifth output terminal and said first and second transistors
The first capacitance means connected to the output terminal of the transistor
Wherein the second output voltage compensation circuit is input to the inverted signal supply means is connected, the first
To a sixth transistor of the same conductivity type as the fourth transistor
And the output terminal of the sixth transistor and the third and fourth transistors.
The second capacitance means connected to the output terminal of the transistor
A semiconductor device characterized by including: 19. The invention according to claim 17 or claim 18.
Wherein the first to fourth transistors are N-type.
A semiconductor device, comprising: 20. The invention according to claim 19, wherein:
The input terminal of the first transistor is connected to the non-inverting signal supply means.
A semiconductor device which is connected. 21. The invention according to claim 19, wherein:
The input terminal of the third transistor is connected to the inverted signal supply means.
A semiconductor device characterized by being connected. 22. The invention according to claim 19, wherein:
2 is connected to the non-inverting signal supply means.
A semiconductor device which is connected. 23. The invention according to claim 19, wherein:
4 is connected to the inverted signal supply means.
A semiconductor device characterized by being integrated. (24) The invention according to (10) or (17).
, Connected between the non-inverting input means and the output means.
In addition, the first to fourth transistors have the same conductivity type as the first to fourth transistors.
7 and the connection between the inverting input means and the inverting output means.
In addition, the first to fourth transistors have the same conductivity type as the first to fourth transistors.
8. A semiconductor device, comprising: (25) The invention according to (10) or (17).
In the semiconductor device, the semiconductor device may include a plurality of transistors of the same conductivity type as the first to fourth transistors.
Features a logic circuit composed of transistors
Semiconductor device. 26. The invention according to claim 25, wherein:
The logical circuit includes an AND or NAND circuit.
Semiconductor device. 27. The invention according to claim 25, wherein:
The logical circuit includes an OR or NOR circuit
Semiconductor device. 28. The invention according to claim 25, wherein:
The logic circuit includes an EXOR or EXNOR circuit.
Semiconductor device. (29) The invention according to (10) or (17).
In the ninth aspect, the semiconductor device has a ninth conductivity type of the same conductivity type as the first to fourth transistors.
Having a transistor, at least one of the output means or the inverted output means
Is connected to the gate of the ninth transistor
A semiconductor device characterized by the above-mentioned. 30. A plurality of latches formed on an insulating substrate.
A display drive device including a path, wherein each of the latch circuits includes a first transistor of one conductivity type to which a high potential is input to an input terminal.
A first transistor having a low potential input to an input terminal of the transistor;
And a second transistor of the same conductivity type as the first transistor and the output terminal of the first and second transistors.
Output means, and a non-inverting signal connected to the gate of the first transistor.
Signal supply means and an inverted signal connected to the gate of the second transistor.
Supply means; output terminals of the first and second transistors;
Between the signal supply means or the first and second
Between the output terminal of the transistor and the non-inverting signal supply means.
Output voltage compensating circuit connected to any
The output voltage compensating circuit includes the inverting signal supply unit or
The first and the second terminals having their input terminals connected to the non-inverting signal supply means.
And a third transistor of the same conductivity type as the second transistor
And the output terminal of the third transistor and the first and second transistors.
And a capacitance means connected to the output terminal of the second transistor;
A display driving device comprising: 31. Each formed on an insulating substrate is connected
Display drive device including a plurality of inverter circuits
Te, wherein each inverter circuit, a high potential is input to the input terminal, one conductivity type first Trang
A first transistor having a low potential input to an input terminal of the transistor;
And a second transistor of the same conductivity type as the first transistor and the output terminal of the first and second transistors.
Output means, and a non-inverting signal connected to the gate of the first transistor.
Signal supply means and an inverted signal connected to the gate of the second transistor.
Supply means; output terminals of the first and second transistors;
Between the signal supply means or the first and second
Between the output terminal of the transistor and the non-inverting signal supply means.
Output voltage compensating circuit connected to any
The output voltage compensating circuit includes the inverting signal supply unit or
The first and the second terminals having their input terminals connected to the non-inverting signal supply means.
And a third transistor of the same conductivity type as the second transistor
And the output terminal of the third transistor and the first and second transistors.
And a capacitance means connected to the output terminal of the second transistor;
A display driving device comprising: