JP2002198800A - Level shift circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem in a conventional level shift circuit that a size of MOS transistors(TRs) employed for the level shift circuit is inevitably increased because the performance of the MOS TRs needs to be enhanced. SOLUTION: N channel MOS TRs are newly added to the conventional level shift circuit so as to always bring the gate potential for the N channel MOS TRs in cross connection a Vtn or over when it is turned on, independently of the capability of the MOS TRs so as to permit state transition even when P channel MOS TRs with an extremely high capacity are not employed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a level shift circuit for converting a low-voltage signal level into a high-voltage signal level. In particular, the present invention relates to a level shift circuit built in an LCD driver IC integrated on a semiconductor substrate.

[0002]

2. Description of the Related Art A level shift circuit plays a role of converting a low-voltage signal level into a high-voltage signal level. For the level shift circuit, the LCD driver IC is an LCD
When driving a panel, a low-voltage signal from a CPU or the like is input, predetermined signal processing is performed by a shift register, etc., and the output is converted to a high-voltage signal for driving a liquid crystal. Used.

FIG. 5 shows a circuit diagram of a conventional level shift circuit integrated on a semiconductor substrate. In FIG. 5, Tr
1 and Tr2 are P-channel MOS transistors, and Tr3
And Tr4 are N-channel MOS transistors. VDD is a high-voltage power supply voltage, and VEE is a low-voltage power supply voltage. Here, VDD or VSS is applied to the gates of Tr1 and Tr2.
Is supplied. This VSS is VDD as much as possible to turn on Tr1 and Tr2.
The lower the better, the few V used in the control system (eg 5
V) is lower than VDD.

[0004] The DC operation of the conventional level shift circuit will be described below. If the initial value of the input signal is VDD, Tr1 is OF
F and Tr2 are ON, Tr3 is ON, and Tr4 is OFF. At this time, the node A is at the VEE potential, the node B is at the VDD potential, and the output is VEE potential.
(State A).

In state A, a ground voltage VSS is input as an input signal. At the moment when the input signal is switched from VDD to VSS, Tr
1 changes from OFF to ON, and Tr2 changes from ON to OFF. At this time, since the Tr1 and Tr3 are ON, the node A
And the potential divided by the resistance of Tr3. Node B is Tr
VDD potential (floating) to turn off 2 and Tr4
(State B).

In state B, the potential at node A is Tr4 ON
Voltage Vtn or more, Tr4 turns on, and node B
DD potential and stable operation as level shift (state
C).

[0007] The transition from state C to state A is the same as described above.

[0008]

In order for the above-mentioned level shift circuit to operate as a level shift, a state shift is required.
B to Tr4 must be turned on. For this purpose, the potential of the node A, which is obtained by dividing the resistance of Tr1 and Tr3, must be equal to Tr4.
It needs to be higher than the ON voltage Vtn. However, in the conventional level shift circuit, the voltage between VDD and VSS is applied to Vgs (gate-source voltage) of Tr1, and the voltage between VDD and VEE is applied to Vgs of Tr3. A voltage difference of up to several tens of times occurs in Vgs. Generally, when a C-MOS transistor is used in the saturation region, the ON resistance value is Vg
Since it decreases in proportion to the square of s, depending on the voltage used, in order to make the resistance division potential of Tr1 and Tr3 higher than the voltage Vtn for turning on Tr4, the capability of Tr1 is extremely large, and Tr3 The capacity must be designed to be extremely small. Due to the characteristics of such a circuit, in the conventional level shift circuit, the size of the MOS transistor used in the level shift circuit is inevitably increased in order to create a difference in performance between the MOS transistors. As a result, the area of the IC including the level shift circuit is squeezed.

Therefore, an object of the present invention is to provide a level shift circuit which can solve the above-mentioned problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous embodiments of the present invention.

In the conventional level shift circuit, a high withstand voltage process is used to handle a high voltage. At this time, the input of the level shift (the gates of Tr1 and Tr2) receives only a low voltage, so that Tr1 and Tr2 have extremely low capability compared to other MOS transistors to which a high voltage is applied to the gate. From this, when the level shift is designed in consideration of the balance of the capability of each MOS transistor, Tr1 and Tr2 are compared with other MOS transistors constituting the level shift.
MOS transistor size becomes very large.

[0011]

According to a first aspect of the present invention, a level shift circuit according to the present invention is a level shift circuit configured between a first potential and a second potential. A first P-channel MOS transistor to which an input signal is applied, a second P-channel MOS transistor to which an inverted signal obtained by inverting the input signal is applied to a gate, and first and second P-channel MOS transistors A first power supply for applying a first potential to the source of the transistor, a gate and a drain are cross-connected to each other, and first and second power supplies are respectively connected to the drains of the first and second P-channel MOS transistors. A drain connected to a source of the N-channel MOS transistor and a source of the first N-channel MOS transistor, a drain of the first P-channel MOS transistor;
The drain of the first N-channel MOS transistor and the second
The first to which the gate of the N-channel MOS transistor is connected
A third N-channel MOS transistor having a gate connected to the drain of the first N-channel MOS transistor
The drain is connected to the source of the transistor and the second N-channel MOS transistor, the drain of the second P-channel MOS transistor, the drain of the second N-channel MOS transistor, and the third N-channel MOS transistor A fourth N-channel MOS transistor having a gate connected between the second node connected to the gate of the second N-channel MOS transistor and a third and fourth N-channel MOS transistor; A second power supply for applying a second potential to the source of the MOS transistor.

Further, the level shift circuit of the present invention has a first
And the second, third, and fourth N-channel MOS transistors have gate oxide thicknesses of the first, second, third, and fourth P-channel MOS transistors.
It is characterized in that it is thinner than the gate oxide film thickness of the OS transistor.

In the inverter receiving the output from the level shift circuit of the present invention, an input signal is applied to a gate and a first potential is applied to a source. 3 P-channel MO
A fifth N-channel MOS transistor connected to the S transistor, having a gate to which an output signal from the level shift circuit is applied, and a source to which a second potential is applied;

[Operation] By adding third and fourth N-channel MOS transistors to the conventional level shift circuit as in the present invention, the N-channel MOS transistors which are cross-connected become ON. When the gate potential becomes MOS
Regardless of the capacity of the transistor, it can be always set to Vtn or more. This can significantly reduce the size of the P-channel MOS transistor and contribute to cost reduction.

Further, first and second P-channel MOSs
By reducing the gate oxide film thickness of the transistor,
By improving the capability of the MOS transistor, it is not necessary to increase the size of the MOS transistor. This
IC chips can be reduced and costs can be reduced.

By providing the inverter of the present invention, for example, when level conversion is performed between 3 V and 30 V, the leak current can be reduced to about 1/100.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described through embodiments of the present invention. However, the following embodiments do not limit the claimed invention and have the features described in the embodiments. Not all combinations are essential to the solution of the invention.

[First Embodiment] First, as a first embodiment, a level shift circuit of the present invention will be described. FIG. 1 is a circuit diagram of a level shift circuit integrated on a semiconductor substrate according to the first embodiment of the present invention.

The level shift circuit according to the present embodiment includes a first P-channel MOS transistor (Tr1) in which an input signal is applied to a gate and a second P-channel MOS transistor (Tr1) in which an inverted signal of the input signal is applied to a gate. Channel type MOS transistor (Tr
2), a first power supply (VDD) for applying a first potential to the sources of the first and second P-channel MOS transistors, and a gate and a drain cross-connected to each other.
The first and second N-channel MOS transistors (Tr1 and Tr2, respectively) connected to the drain of the P-channel MOS transistor, and the drain of the first N-channel MOS transistor connected to the source; The drain of one P-channel MOS transistor and the first N-channel MOS
The first node connected to the drain of the S transistor and the gate of the second N-channel MOS transistor has a first node.
A third N-channel MOS transistor having a gate connected to the drain of the N-channel MOS transistor (Tr
5), the drain is connected to the source of the second N-channel MOS transistor, the drain of the second P-channel MOS transistor, the drain of the second N-channel MOS transistor, and the third N-channel MOS transistor A fourth node having a gate connected between the second node to which the gate of the transistor is connected and the drain of the second N-channel MOS transistor
, And a second power supply (VEE) for applying a second potential to the sources of the third and fourth N-channel MOS transistors.

If the initial value of the input signal is VDD, Tr1 is OF
F, Tr2 ON, Tr3 ON, Tr4 half ON, Tr5 half ON, T
r6 turns ON. Here, “half ON of Tr4 and Tr5” means that the node A is lifted by Vtn of Tr5 with respect to VEE due to the self-bias of Tr5, so that it is in a state close to OFF as much as possible. Node B is at the VDD potential and the output is VD
It becomes D (state A).

In state A, VSS is input as an input signal. At the moment when the input signal switches from VDD to VSS, Tr
1 changes from OFF to ON, and Tr2 changes from ON to OFF.
At this time, node A turns on Tr1, Tr3 because Tr1 and Tr3 are ON.
Potential divided by resistance of Tr3 and Tr5 (VDD × R (Tr1) / (R (T (T
r1) + R (Tr3) + R (Tr5))). However, since Tr5 is self-biased, node A is not below Vtn of Tr5.
Also, in node B, Tr2 and Tr4 are OFF (Tr4 is infinitely OFF)
, And is maintained at the VDD potential (close to floating) (state B).

In state B, the potential at node A is
Since it does not fall below tn, Tr4 turns on and node B
Is the potential of VEE + (voltage Vtn for turning on Tr6) (output is VDD
become). When the node B approaches VEE, Tr3 approaches OFF, the node A becomes the VDD potential, and operates stably as a level shift (state C).

As described above, in the state A, the potential of the node A is higher by the self-bias of the transistor Tr5 (Vtn5).
Therefore, when the state transitions to the state B, Tr4 is reliably turned on, and the transition to the state C is performed stably. The same applies to the transition from state C to state A.

[Embodiment 2] Next, Embodiment 2 of the present invention shown in FIG. 2 is one in which the above-described level shift circuit of Embodiment 1 is integrated on a semiconductor substrate, and gate oxidation of Tr1 and Tr2 is performed. The film is characterized in that it is thinner than the gate oxide films of Tr3, Tr4, Tr5, and Tr6.

For Tr1 and Tr2, a gate electrode 13 is formed on a P-type Si substrate 11 via a gate oxide film 12 having a thickness of tox (300 °), and a source layer 14 and a drain layer 15 are formed on both sides thereof. Have been. The drain layer 15 includes a low-concentration N ⁻ layer 15A self-aligned with the gate electrode 12, and a high-concentration N ⁺ layer 15B offset from the gate electrode. In the above transistor, only a voltage (for example, about 5 V) from a control circuit is applied to the gate electrode 12,
Since no high voltage is applied, the problem of gate breakdown voltage deterioration does not occur.

In order to accommodate transistors having different thicknesses of gate oxide films in one chip as in this embodiment, a configuration as described in JP-A-8-70247 is required. Is preferred.

As described above, by making the gate oxide films of Tr1 and Tr2 thinner than the gate oxide films of Tr3, Tr4, Tr5 and Tr6, the capabilities of Tr1 and Tr2 are improved. Can be reduced.
Further, when the sizes of Tr1 and Tr2 are made equal to those of the related art, the operation speed is increased, and high-speed data transfer can be supported.

[Embodiment 3] FIG. 3 is a circuit diagram in which a normal CMOS inverter is connected to the level shift circuit of the present invention. In the level shift circuit of the present invention, when the output level is VE
When the output is received by a conventional CMOS-inverter or the like, there is a possibility that a leak current may occur for some reason because the voltage does not fall to the E potential (becomes higher than VEE by Vtn of Tr6). Since the output of the level shift is a high voltage, when a leak occurs, the amount thereof becomes so large that it cannot be ignored.

Therefore, in order to solve the above problem, an inverter useful for the level shift circuit of the present embodiment has been devised. FIG. 4 is a circuit diagram of a level shift circuit having an inverter 20 according to the third embodiment of the present invention.

In the inverter 20 of the present embodiment, a third P-channel MOS transistor (Tr7) in which an input signal is applied to a gate and a first potential (VDD) is applied to a source.
And the drain is connected to the third P-channel MOS transistor, the output signal from the level shift circuit is applied to the gate, and the second potential (VEE) is applied to the source.
N-channel MOS transistor (Tr8).

As described above, in this embodiment, the voltage applied to the gate of Tr7 is a low voltage of the same control system as that applied to Tr1 and Tr3. That is, it is VDD or VSS. As a result, a high voltage is not applied to the gate of the MOS transistor Tr7 subjected to the level shift. For example, V
The potential difference between DD and VSS is 3V. Since the current flowing through the CMOS transistor increases in proportion to the square of the gate voltage,
When the level is converted to 30V, the leakage current is about 1/100
To decrease. In recent years, as the labor saving of mobile devices and the like progresses, it is essential to reduce the leak current, and the present invention is very effective as a countermeasure.

Although the present invention has been described with reference to the embodiment, the technical scope of the present invention is not limited to the scope described in the above embodiment. Various changes or improvements can be added to the above embodiment. It should be noted that such modified or improved embodiments may be included in the technical scope of the present invention.
It is clear from the description of the claims.

[0033]

As is apparent from the above description, according to the present invention, the size of the level shift circuit can be reduced. Further, the operation speed of the transistor can be increased, and the level shift can be performed at high speed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a level shift circuit 10 according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a structure of a MOS transistor according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram in which a normal CMOS inverter is connected to the level shift circuit of the present invention.

FIG. 4 is a circuit diagram of a level shift circuit having an inverter 20 according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional level shift circuit integrated on a semiconductor substrate.

[Explanation of symbols]

 10 level shift circuits, 20 inverters.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Eiji Seibu 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Shuichi Kikuchi 2-5-1 Keihanhondori, Moriguchi-shi, Osaka No. 5 F-term (reference) in Sanyo Electric Co., Ltd. 5F048 AB10 AC03 BA01 BB16 BC05 BC06 BG12 5J056 AA00 AA32 BB57 CC21 DD13 DD29 EE07 FF08

Claims (3)

[Claims] 1. A level shift circuit configured between a first potential and a second potential, wherein: a first P-channel MOS transistor having an input signal applied to a gate; and the input signal being inverted at a gate. A second P-channel MOS transistor to which the inverted signal applied is applied; a first power supply for applying the first potential to the sources of the first and second P-channel MOS transistors; And a first and a second N-channel MOS transistor respectively connected to the drains of the first and second P-channel MOS transistors, and a drain and a source connected to the source of the first N-channel MOS transistor. Are connected, the drain of the first P-channel MOS transistor, the drain of the first N-channel MOS transistor, and the second N-channel MOS transistor A third N-channel MOS transistor having a gate connected to a first node to which a gate is connected, and a drain of the first N-channel MOS transistor; and a second N-channel MOS transistor. The drain of the second P-channel MOS transistor, the drain of the second N-channel MOS transistor and the gate of the third N-channel MOS transistor are connected. A fourth N-channel MOS transistor having a gate connected to a drain of the second N-channel MOS transistor at a node of the second N-channel MOS transistor; and a source connected to the third and fourth N-channel MOS transistors. And a second power supply for applying a second potential. 2. The level shift circuit according to claim 1, wherein said first and second P-channel MOS transistors have gate oxide thicknesses of said first, second, third and fourth gate transistors.
A level shift circuit characterized in that the thickness of the gate oxide film is smaller than that of an N-channel MOS transistor. 3. The level shift circuit according to claim 1, further comprising: a third P-channel MOS transistor in which the input signal is applied to a gate and the first potential is applied to a source. A drain connected to the third P-channel MOS transistor, an output signal from the level shift circuit applied to a gate, and a second potential applied to a source;
And an N-channel MOS transistor.