JPH05199101A - Level shift circuit - Google Patents

Abstract

PURPOSE:To reduce the chip size by using a resistor between a PMOS transistor(TR) and an NMOS TR in the level shift circuit employing CMOS TRs for a gate resistor of a TR of a next-stage. CONSTITUTION:A resistor R1 (R2) is arranged between drains of TRs P1, N1 (TRs P2, N2) respectively, a gate of the TR P1 connects to a connecting point B and a gate of the TR P2 connects to a connecting point A respectively, a gate of the TR N2 is connected to an output of an invereter INV.3 and a gate of the TR N1 is connected to an input of an invereter INV.3. In the level shift circuit connected as above, the gate resistor of the inverter INV.1 connecting point A employs the resistor R1 and the gate resistor of the inverter INV.2 connecting point B employs the resistor R2 respectively. Thus, the chip size of the circuit shifting the level of multi-signals is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift circuit, and more particularly to a level shift circuit using CMOS transistors.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional level shift circuit of this type has PMOS transistors P1, P2, N.
MOS transistors N1, N2, resistors R1, R2, and inverter INV. 1, INV. 2, INV. 3 and has a resistor R1 between the drains of the transistors P1 and N1.
A resistor R2 is arranged between the drains of the transistors P2 and N2, and the sources of the transistors P1 and P2 are the first power source V1.
The sources of the transistors N1 and N2 are connected to the second power source VSS, respectively, and the gate of the transistor P1 is at the contact B between the drain of the transistor N2 and the resistor R2, and the gate of the transistor P2 is at the drain of the transistor N1 and the resistor R1. And an inverter INV. Connected to a contact A between the third power supply VCC and the second power supply VSS. 3 is connected to the gate of the transistor N1 and its output is connected to the gate of the transistor N2.

Further, as an output of the level shift circuit, for example, as shown in FIG. 2, an inverter INV. 1, INV. 2 are the drain of the transistor N1 and the transistor N2, respectively.
The structure is connected to the drain of.

[0004]

In the conventional level shift circuit described above, for example, when the input IN changes from high level to low level, the transistor N1 changes from ON to OF.
Although the F state is set and the transistor N2 is changed from OFF to ON state, the potential of the gate of the transistor P1 is controlled by the transistors P2 and N2. Therefore, when the capability of the PMOS transistor is increased (for example, the channel width is large), The gate potential is transistor P
Since it is difficult to attain a low level due to the capacity ratio of 2 and N2, it takes time for the gate potential of the transistor P2 to reach the power supply VDD level, and the rise time of the contact A and the fall time of the contact B are several tens of times that of the inverter circuit. ~ Delayed by several hundred times and transmitted to outputs Q1 and Q2.

On the contrary, when the capacity of the PMOS transistor is reduced (for example, the channel width is small), the fall of the contact point B becomes faster and the transistor P1 is turned on. However, the rise time of the contact point A is small because the ability is small. It cannot be made as fast as the fall time of the contact B, but in consideration of the speed balance of the rise and fall times, it is usual to design so that PMOS transistor capability <NMOS transistor capability.

However, when the channel width of the PMOS transistor is made small, the manufacturing variation has a large influence on the channel width and affects the characteristics, so that it cannot be made so small. Therefore, as shown in FIG. 2, between the transistors P1 and N1 or between the transistors P2 and N1.
By inserting resistors R1 and R2 between the two,
Although the configuration is equivalent to reducing the channel width of the transistor to reduce the performance, the layout of the resistors R1 and R2
Has a large occupied area and level-shifts multiple signals,
It will also affect the chip size.

Also, instead of inserting the resistors R1 and R2, if the capacity of the NMOS transistor is increased, that is, if the channel width is increased, the same characteristics as the above method can be obtained, but the channel width of the NMOS transistor is increased. The effect on the chip size due to the increase of is also the same.

[0008]

The structure of the level shift circuit of the present invention comprises a first PMOS transistor and a first NM.
Between the drain or the source of the OS transistor, and the second
First and second resistors are respectively arranged between the drains and sources of the PMOS transistor and the second NMOS transistor, and the sources and drains of the first and second PMOS transistors are used for the first power source and The sources or drains of the first and second NMOS transistors are connected to a second power supply, the gate of the first PMOS transistor is connected to the second resistor and the drain or source of the second NMOS transistor, and the second The gate of the second PMOS transistor is commonly connected to the first resistor and the drain or source of the first NMOS transistor, and the gate of the second NMOS transistor is connected between the third power source and the second power source. Connected to the output of the arranged inverter, and the gate of the first NMOS transistor connected to the input of the inverter In the level shift circuit, the first, the second resistor, and having a structure that utilizes the resistance of the gate of each of the next-stage transistor.

[0009]

1A is a circuit diagram of a level shift circuit according to an embodiment of the present invention.

In FIG. 1A, the present embodiment is different from the conventional configuration of FIG. 2 in that the next-stage inverters INV. 1, INV. The gate resistance of 2 is used as the resistances R1 and R2.

For example, the inverter IN shown in FIG.
V. 1, or INV. 2 {shown in FIG. 1 (a)) is a simple layout diagram showing the transistor P1 or P2.
To the point a, and the transistor N1 or N
By connecting the drains of 2 to the points b,
The resistance of the gate between b is R1 and R2.

In FIG. 1B, the drain (Dra
in) 10, source (Source) 11, gate (G)
ate) 12, each area is connected to the power supplies VDD and VSS, and the output Q1 (or Q2) is taken out from the right side. A gate 12 is provided between the points a and b, and this serves as the resistor R1 (or R2).

As a result, the circuit configuration becomes the same as the conventional circuit configuration as shown in FIG. 2, so that the operation becomes the same as the conventional one.

In addition, the inverter INV. 1, INV. The input signal of 2 is
Transistors P1 and N1 of the conventional circuit shown in FIG. 2 respectively.
Since it is the same as the signal at the contact A at the contact A and the signal at the contact B between the transistors P2 and N2, the logical transmission delay times to the outputs Q1 and Q2 are the same.

In the present embodiment, the configuration using the gate of the inverter is shown, but it goes without saying that the gate of another circuit such as a NAND gate or a transfer gate may be used.

[0016]

As described above, in the level shift circuit according to the present invention, the gate resistance of each succeeding stage transistor is used as the first and second resistances, and it is not necessary to insert a new resistance. Therefore, since the area occupied by the level shift circuit on the layout can be reduced, there is an effect that the chip size can be reduced, especially in the case of level shifting multiple signals.

[Brief description of drawings]

1A and 1B are a circuit diagram and a partial layout diagram of a level shift circuit according to an embodiment of the present invention, respectively.

FIG. 2 is a circuit diagram showing a conventional level shift circuit.

[Explanation of symbols]

P1, P2 PMOS transistor N0, N2 NMOS transistor R1, R2 resistance INV. 1, INV. 2, INV. 3 Inverter circuit VDD, VCC, VSS Power supply IN input Q1, Q2 output

Claims (1)

[Claims] 1. A first PMOS transistor and a first N transistor.
First and second resistors are arranged between the drains and sources of the MOS transistors and between the drains and sources of the second PMOS transistor and the second NMOS transistor, respectively, and the first and second PMOS transistors have the same structure. The source or drain is connected to the first power source, and the first and second
The source or drain of the NMOS transistor is connected to a second power supply, the gate of the first PMOS transistor is connected to the second resistor and the drain or source of the second NMOS transistor, and the gate of the second PMOS transistor is connected to the second resistor. The gate is commonly connected to the first resistor and the drain or source of the first NMOS transistor,
In the level shift circuit, the gate of the second NMOS transistor is connected to the output of the inverter arranged between the third power supply and the second power supply, and the gate of the first NMOS transistor is connected to the input of the inverter. A level shift circuit having a structure in which the resistance of the gate of each subsequent-stage transistor is used as the first and second resistances.