JPH10190435A - Semiconductor output circuit, cmos output circuit, terminal potential detection circuit and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a backflow from a first power supply to a second power supply by driving a pre-buffer by the first power supply, and at the time of detecting that the potential of an output node is set to a first power supply level, turning OFF the supply of the second power supply to the well substrate of a pull-up transistor and turning it to a floating state. SOLUTION: When an output pad 20 is raised to 5V by an external circuit, DRAM for instance, a P-MOS transistor 31 for setting a base panel potential is turned OFF and the N well substrate of the P-MOS transistor 11 for pull-up is turned to the floating state. The detection signal G13 of 5V raises the output G11 of the NAND gate 21 of a first pre-buffer to 5V through an OR gate 23 and an inverter 24 and turns OFF the P-MOS transistor 11 for the pull-up. Thus, the backflow from the output pad 20 of 5V through the P-MOS transistor 11 for the pull-up to a 3.3V power supply is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor output circuit and a CMO capable of interfacing between different voltage levels.
The present invention relates to an S output circuit, a terminal potential detection circuit used for these circuits and the like, and a semiconductor device having the semiconductor output circuit and the CMOS output circuit mounted on an I / O unit.

[0002]

2. Description of the Related Art In recent years, as the process of a MOS transistor is miniaturized, the allowable gate oxide film breakdown voltage has been lowered, and accordingly, the voltage of an LSI has been reduced. It is thought that this trend will continue in the future, but in this transition period of lowering the voltage, LS with different voltages
Mixing of I is inevitable.

FIG. 6 is a circuit diagram of a conventional general CMOS output circuit.

This CMOS output circuit has a P-channel MO
An S transistor (hereinafter, referred to as a P-MOS transistor) 101 and an N-channel MOS transistor (hereinafter, referred to as a P-MOS transistor)
, And these transistors 101 and 102 are connected in series between the 3.3 V power supply and the ground. An input signal IN is simultaneously applied to the gates of the transistors 101 and 102, and an output OUT is obtained from a connection node between the drains of the transistors 101 and 102.

In a case where an output circuit for outputting 5V is directly connected to such an output circuit for outputting 3.3V, if these output circuits are simply connected, a current flows from the 5V system to the 3.3V system. The problem of inflow arises.

[0006] Therefore, an interface between different levels is required, and recently a transition from a 5V power supply to a 3V power supply has recently been performed, and various 5V / 3V interface technologies have been studied as a bridge role.

FIG. 7 is a circuit diagram of a conventional CMOS output circuit (3V output corresponding to 5V).

This CMOS output circuit is composed of a single 3.3V power supply, and a P-MOS transistor 201, a P-MOS transistor 202 and an NM
The main output circuit 200 includes an OS transistor 203 connected in series. P-MOS transistor 20
2 and N-MOS transistor 203 connection node N11
Is connected to the output pad 211.

On the other hand, a NAND gate 221 and a NOR gate 222 are provided on the input side of the main output circuit 200. An input signal IN is supplied to one of two input terminals of the NAND gate 221 and an enable signal is supplied to the other. EN
Is supplied to the inverter 223 after being inverted. Also, N
The input signal IN is supplied to one of the two input terminals of the OR gate 222, and the enable signal EN is directly supplied to the other. Then, the output G of the NAND gate 221
1 is connected to the gate of the P-MOS transistor 201;
The output G2 of the OR gate 222 is supplied to the gate of the N-MOS transistor 203, respectively.

[0010] Further, the P-
P- for turning on / off the supply of power to the substrate (N-well base) N12 of the MOS transistor 202
A MOS transistor 231 is provided, and the gate thereof is supplied with the potential of the output pad 211.

A P-MOS transistor 241 for detecting a 5V input to the output pad 211 and an N-MO
An S transistor 242 is provided, and its P-MO
A P-MOS transistor 243 and an N-MOS transistor 244 for applying a reference voltage to the gate of the S transistor 241 are provided. And the P-MOS
A detection signal G3, which is a detection result of the 5V input by the transistor 241 and the N-MOS transistor 242, is supplied to the gate of the P-MOS transistor 202 of the main circuit 200.

FIG. 8 is a schematic sectional view of the main output circuit 200 in the CMOS output circuit shown in FIG.

The P-MOS transistors 201, 202,
In a predetermined region for forming 231, a P-type layer 252 is formed in the N-type layer 251, and further, in the P-type layer 252,
N-well substrate 253 for P-MOS transistor 201
And an N-well substrate 254 for the P-MOS transistors 202 and 231 are formed. Each P-type diffusion layer serving as a source / drain region is formed on the main surface side in each of the N-well substrates 253 and 254.

On the other hand, in a predetermined region where the N-MOS transistor 203 is formed, the P-type layer 25 is
5 is formed, and the source / side is formed on the main surface side in the P-type layer 255.
Each N-type diffusion layer serving as a drain region is formed.

Next, the conventional circuit shown in FIGS.
The operation corresponding to v will be described.

When 5V (high level) is input from the output pad 211, the P-MOS transistor 231 is turned off, and 3.3V to the N-well substrate 254 (node N12) is turned on.
Supply stops. As a result, the N-well substrate 254 of the P-MOS transistors 202 and 231 is brought into a floating state, and the P-MOS transistor 202
-It is possible to prevent the backflow of the current flowing to the 3V power supply via the MOS transistors 202 and 201.

On the other hand, when 5v is input from the output pad 211, the P-MOS transistor 241 turns on,
The detection signal G3 of 5v is output. As a result, P-MOS
The gate-source voltage VGS of the transistor 202 is 0
v, the P-MOS transistor 202 is completely turned off, and the above-described current backflow can be reliably prevented.

[0018]

However, in the above-mentioned conventional CMOS output circuit (3v output corresponding to 5v), the main output circuit is constituted by three MOS transistors, and in particular, two pull-up side outputs for 3.3v are provided. P-MOS transistors 201 and 202 are connected in series. 5
A normal CMOS output circuit that does not require v support (FIG. 6)
Since only the P-MOS transistor 101 is used as a pull-up transistor, the CMOS output circuit corresponding to 5V shown in FIG. The problem is that it is required twice.

A specific description will be given. Assuming that the P-MOS transistor 101 and the P-MOS transistors 201 and 202 of the output circuits of FIGS. 6 and 7 are of the same size, in the output circuit of FIG.
-Since the MOS transistors 201 and 202 are connected in series, the output current amount is 1 compared to the output circuit of FIG.
/ 2. Therefore, in order to flow the same amount of current as the output circuit of FIG. 6, in the output circuit of FIG. 7, the area of each of the P-MOS transistors 201 and 202 is doubled (that is, FIG.
(Four times as large as the P-MOS transistor 101 of the output circuit of FIG. 1), and the driving force has to be increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor device capable of interfacing between different voltage levels and greatly reducing the circuit area. An output circuit and a CMOS output circuit are provided. Other objectives are semiconductor output circuits that achieve low power consumption and high-speed operation,
A CMOS output circuit and a terminal potential detection circuit are provided. Still another object is to provide a semiconductor device in which the area of an I / O section is significantly reduced.

[0021]

According to a first aspect of the present invention, there is provided a semiconductor output circuit which is connected between a first power supply and an output node, and is controlled by a first control signal. A pull-up transistor that operates on / off,
A prebuffer for generating the first control signal based on input data; and a second buffer when the potential of the output node is set to a level of a second power supply higher than the level of the first power supply by an external circuit. A potential detection circuit that outputs a detection signal of a potential corresponding to the power supply of the semiconductor device, wherein the pre-buffer is driven by the second power supply, and A transistor for setting a base potential, which turns on / off the supply of the power supply 1 according to the potential of the output node;
A logic circuit that receives the detection signal from the potential detection circuit and outputs a second control signal for setting the first control signal to the level of the second power supply to the pre-buffer. It is in.

According to the first aspect, when the level of the second power supply is input from the output node, the substrate potential setting transistor is turned off, and the N-well substrate of the pull-up transistor is brought into a floating state. In addition, a backflow of a current flowing from the output node to the first power supply via the pull-up transistor is prevented. On the other hand, the potential detection circuit outputs a detection signal, and the logic circuit receives the detection signal and outputs a second control signal to the prebuffer. As a result, the first control signal output from the prebuffer becomes the level of the second power supply, and the pull-up transistor is completely turned off. This makes it possible to prevent the reverse flow of current from the second power supply to the first power supply by using only the pull-up transistor without connecting two transistors in series on the pull-up side unlike the conventional circuit.

A semiconductor output circuit according to a second aspect of the present invention is characterized in that, in the first aspect, the potential detection circuit includes a potential detection transistor connected between the output node and a detection result node; Resistance means connected between a detection result node and ground, wherein the potential detection transistor is turned off when the output node is at or below the level of the first power supply and turned on when the output node is at the level of the second power supply. A reference voltage generation circuit for generating a reference voltage to be supplied to a control electrode of the potential detection transistor, connected between the detection result node and ground, and turned on when the potential of the output node is at the level of the first power supply And a charge adjusting transistor that is turned off when the second power supply is at the level.

According to the second aspect, when the level of the second power supply is input from the output node, the charge adjusting transistor is turned off, and the current flowing from the route of the potential detecting transistor and the resistance means is reduced. Reduce. When the output node goes to the ground level, the charge adjusting transistor is turned on, and the potential of the detection signal is quickly brought to the ground level.

The CMOS output circuit according to the third invention is characterized in that it is connected between a first power supply and an output node and is turned on / off by a first control signal.
P-channel MOS transistor, and a pull-down N-channel MOS that is connected between the output node and the ground and that is turned on / off complementarily to the first P-channel MOS transistor by a second control signal A transistor; first and second pre-buffers for respectively generating the first and second control signals based on input data; and a third circuit in which the potential of the output node is higher than the level of the first power supply by an external circuit. And a potential detection circuit for outputting a detection signal of a potential corresponding to the second power supply when the power supply is set to the level of the second power supply. And a first power supply to the N-well substrate of the first P-channel MOS transistor. And a second P-channel MOS transistor for setting a substrate potential which is turned on / off in response to the detection signal from the potential detection circuit, and sets the first control signal to the level of the second power supply. And a logic circuit for outputting a third control signal for setting the second control signal to the ground level to the first and second pre-buffers.

According to the third aspect, when the level of the second power supply is input from the output node, the second P-channel MOS transistor is turned off and the N-well of the first P-channel MOS transistor is turned off. The board is set in a floating state to prevent a backflow of current flowing from the output node to the first power supply via the first P-channel MOS transistor. On the other hand, the potential detection circuit outputs a detection signal, and the logic circuit receives the detection signal and outputs a third control signal to the first and second pre-buffers. As a result, the first control signal output from the first pre-buffer is at the level of the second power supply, and the first P-channel MOS transistor is completely turned off. This makes it possible to prevent the reverse flow of current from the second power supply to the first power supply by using only the pull-up transistor without connecting two transistors in series on the pull-up side unlike the conventional circuit. Further, the second control signal output from the second pre-buffer goes to the ground level and turns off the pull-down N-channel MOS transistor, so that a backflow of current to the ground side can be prevented.

A fourth aspect of the present invention is a CMOS output circuit according to the third aspect, wherein the potential detecting circuit is replaced by a third potential detecting circuit connected between the output node and a detection result node. A P-channel MOS transistor, a resistor connected between the detection result node and ground, and turning off the third P-channel MOS transistor when the output node is lower than the level of the first power supply. A reference voltage generating circuit for generating a reference voltage to be supplied to the gate of the third P-channel MOS transistor so as to be turned on at the time of the level of the second power supply, and connected between the detection result node and ground; And an N-channel MOS transistor for charge adjustment, which is turned on when the potential of the first power supply is turned on and turned off when the potential of the second power supply is turned on. In the door.

According to the fourth aspect, when the level of the second power supply is input from the output node, the N-channel MOS transistor for charge adjustment is turned off, and the third P-channel MOS transistor and the resistance of the resistance means are turned off. Reduce the current flowing from the route. When the output node goes to the ground level, the charge adjustment N-channel MOS transistor is turned on, and the potential of the detection signal is quickly brought to the ground level.

The fifth invention is characterized in that the terminal potential detecting circuit is characterized in that a first MOS transistor connected between a terminal of an external circuit and a detection result node, and a first MOS transistor connected between the detection result node and ground. And the first MOS transistor so as to turn off when the terminal of the external circuit is lower than the level of the first power supply and to turn on when the level of the second power supply is higher than the first power supply. A terminal potential detection circuit including a reference voltage generation circuit for generating a reference voltage to be supplied to a gate, the terminal potential detection circuit being connected between the detection result node and a ground, wherein a potential of a terminal of the external circuit is the first potential;
A second MOS transistor which is turned on at the time of the power supply level and turned off at the level of the second power supply.

According to the fifth aspect, when the level of the second power supply is input from the terminal of the external circuit, the second MOS
The transistor is turned off, and the current flowing from the route of the first MOS transistor and the resistance means is reduced.
When the output node goes to the ground level, the second M
The OS transistor is turned on, and the potential of the detection result node is quickly brought to the ground level.

A semiconductor device according to a sixth aspect of the present invention is characterized in that the semiconductor device includes an I / O section for connecting to an external circuit, and an internal function block connected to the I / O section. The / O unit is connected between an output terminal connected to the external circuit and a first power supply, and has a pull-up transistor that is turned on / off by a first control signal, and a level of the first power supply. A pre-buffer, which is driven by a second power supply of a higher level and generates the first control signal based on input data from the internal function block, and the potential of the output terminal is set to the second level by the external circuit. A potential detection circuit for outputting a detection signal of a potential corresponding to the second power supply when set to a power supply level; and an output terminal for supplying the first power supply to the N-well substrate of the pull-up transistor. A second transistor for setting a first control signal to a level of the second power supply upon receiving the detection signal from the potential detection circuit; A logic circuit for outputting a control signal to the pre-buffer.

According to the sixth aspect, the semiconductor output circuit provided in the I / O section has the same function as the first aspect.

A semiconductor device according to a seventh aspect of the present invention is characterized in that, in the semiconductor device having an I / O section for connecting to an external circuit, and an internal function block connected to the I / O section, A first P-channel MOS transistor for pull-up, which is connected between an output terminal connected to the external circuit and a first power supply and is turned on / off by a first control signal; An N-channel MOS transistor for pull-down, which is connected between the output terminal and the ground and which is turned on / off complementarily to the first P-channel MOS transistor by a second control signal;
First and second pre-drives driven by a second power supply having a higher level than the first power supply and generating the first and second control signals based on input data from the internal function block, respectively A buffer; a potential detection circuit that outputs a detection signal of a potential corresponding to the second power supply when the potential of the output terminal is set to the level of the second power supply by the external circuit; A second P-channel MOS transistor for setting a substrate potential for turning on / off the first power supply to the N-well substrate of the channel MOS transistor in accordance with the potential of the output terminal; and the detection signal from the potential detection circuit. Receiving the third control signal for setting the first control signal to the level of the second power supply and the third control signal for setting the second control signal to the ground level. In further comprising a CMOS output circuit and a logic circuit for outputting to the second pre-buffer.

According to the seventh aspect, the CMOS output circuit provided in the I / O section exhibits the same operation as the third aspect.

[0035]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a CMOS output circuit (semiconductor output circuit) according to the first embodiment of the present invention. FIG. 2 is a block diagram showing a schematic configuration of a system in which the CMOS output circuit of the present invention is mounted.

First, referring to FIG. 2, on a board 50, for example, LSs each composed of a D-RAM, a CPU, etc.
I chips 51 and 52 are mounted. LSI chip 5
1 is driven by a single 5V power supply, and the LSI chip 52 is
It is configured to be driven by both power supplies of v / 3.3v. The 5v / 3.3v power supply is connected to the 5v / 3.3v
It is supplied from a 3.3v power supply circuit (not shown).

FIG. 3 shows the LSI chip 5 shown in FIG.
2 is a block diagram showing a configuration of FIG. This LSI chip 5
2 is roughly composed of three parts. That is, the I / O unit 5 that connects to an external circuit (LSI chip 51)
This LSI chip 52 is composed of 2A, a random logic section 52B in which a plurality of logic gate cells are connected in series, and a macroblock 52C composed of a memory or the like. Here, the random logic section 52B and the macro block 52C are configured as internal function blocks of the LSI chip 52, and the CMOS output circuit of the present invention is implemented by an LS
It is incorporated in the I / O unit 52A of the I chip 52.

Hereinafter, the CMO of this embodiment will be described with reference to FIG.
The configuration and operation of the S output circuit (3v output corresponding to 5v) will be described.

In FIG. 1, this CMOS output circuit is
Both power supplies of 5v / 3.3v are used as power supplies. 3.3
The main output circuit 10 of the v power supply has a pull-up PM
An OS transistor 11 and an N-MOS transistor 12 for pull-down are connected in series. PM
An output pad 20 is connected to a connection node N1 between the OS transistor 11 and the N-MOS transistor 12.

On the other hand, on the input side of the main output circuit 10,
A two-input NAND gate 21, a two-input NOR gate 22,
And a two-input OR gate 23 connected to a 5V power supply. An enable signal EN is supplied to one of two input terminals of the OR gate 23, and the other input terminal is connected to a terminal 5 to be described later.
The detection signal G13 from the v detection circuit 40 is supplied. Further, an input signal IN is supplied to one of two input terminals of the NAND gate 21, and an output of the OR gate 23 is supplied to the other input terminal after being inverted by an inverter 24. Also,
The input signal IN is supplied to one of the two input terminals of the NOR gate 22, and the output of the OR gate 23 is directly supplied to the other.

Then, the output G11 of the NAND gate 21
(Amplitude of 0v to 5v) is the P-MOS transistor 1
The output G12 of the NOR gate 22 (0 V to
5V) is supplied to the gates of the N-MOS transistors 12 respectively.

Further, the PM of the main output circuit 10
A P-MOS transistor 31 for supplying or stopping 3.3 V to the substrate (N-well base) N2 of the OS transistor 11 is provided. The source of the P-MOS transistor 31 is connected to the 3.3 V power supply, the drain is connected to the substrate of the P-MOS transistor 11 in common with the substrate of the P-MOS transistor 31, and the output is connected to the gate. The potential of pad 20 is applied.

A 5V detection circuit 40 (3.3V power supply system) for detecting a 5V input to the output pad 20 is provided. The 5v detection circuit 40 has a P for 5v detection.
A MOS transistor 41 and an N-MOS transistor 42, and a P-MOS transistor 43 for generating a reference voltage
And an N-MOS transistor 44.
P-MOS transistor 41 and N-MOS for 5V detection
The transistor 42 is connected in series between the output pad 20 and the ground, and the reference voltage generation P-MOS transistor 43 and the N-MOS transistor 44
It is connected in series between the power supply and the ground. Note that N
The gates of the MOS transistors 42 and 44 are 3.3v
It is fixed at.

The gate and drain of the P-MOS transistor 43 are connected in common, and the reference voltage is applied to the P-MOS transistor 43 from this connection point.
This is applied to the gate of the MOS transistor 41. That is,
P-MOS transistor 43 and N-
The MOS transistor 44 has the output pad 20 of 3.3 V
A reference voltage to be supplied to the gate of the P-channel MOS transistor 41 is generated so that the P-channel MOS transistor 41 is turned off at the following time and turned on at 5 V. Then, a detection signal G13, which is a detection result, is output from a connection point between the P-MOS transistor 41 and the N-MOS transistor 42.

As described above, the 5v detection circuit 40 is configured to output 5v as the detection signal G13 when 5v is input from the output pad 20.

FIG. 4 is a schematic sectional view of the main output circuit 10 in the CMOS output circuit shown in FIG.

In a predetermined region where the P-MOS transistors 11 and 31 are to be formed, a P-type layer 62 is formed in the N-type layer 61, and an N-well substrate 63 is formed in the P-type layer 62. Then, on the main surface side in the common N-well substrate 63, the sources / sources of the P-MOS transistors 11 and 31 are connected.
P-type diffusion layers 64a, 64b, 65 serving as drain regions
a and 65b are respectively formed. And PM
P-type diffusion layers 64a, 65 of OS transistors 11, 31
A power supply of 3.3 V is connected to a, and the P-type diffusion layer 65b of the P-MOS transistor 31 is connected to the N-well substrate 62 via the N-type diffusion layer 65c.

On the other hand, in a predetermined region where N-MOS transistor 12 is to be formed, a P-type layer 66 is formed in N-type layer 61, and an N-type diffusion layer 67 is formed on the main surface side of P-type layer 66.
a, 67b and a P-type diffusion layer 67c.

Next, the operations (A) and (B) of the first embodiment will be described.
Will be described.

(A) Normal Operation First, the case where the output pad 20 is at a low level (3.3 V) is considered. At this time, the detection signal G13 is 0v, the enable signal EN is at the "0" level, and the input signal IN at the "1" level is input, and the pull-up signal G11 has the potential of 0v. 11 turns on, and a potential of 3.3 V is transmitted to the output pad 20 together with the node N1. At this time, since the signal G12 is at the “0” level, the N-MOS transistor 12 is off.

On the other hand, when the enable signal EN is at the “0” level, the input signal IN at the “0” level is
At the time of pull-down at which the potential becomes 5V, the N-MOS transistor 12 is turned on, and the potential of 0V is transmitted to the output pad 20 together with the node N1. At this time, the signal G1
Since 1 is 5V, the P-MOS transistor 11 is off.

(B) Operation corresponding to 5v When the output pad 20 is raised to 5v (high level) from the external circuit, for example, the DRAM 51, the P-MOS transistor 31 is turned off and the N-well substrate 63 (node N
3.3v supply to 2) is stopped. As a result, PM
Since the N-well substrate 63 of the OS transistors 11 and 31 is in a floating state, the P-MOS transistor 1
No channel is formed between the first P-type diffusion layer 64a and the P-type diffusion layer 64b, and backflow of current flowing from the 5V output pad 20 (OUT) to the 3V power supply via the P-MOS transistor 11 is prevented. I do.

At this time, the node N1 (P-type diffusion layer 64b) also becomes 5v by the 5v input from the output pad 20, and
5 V is supplied to the N-well substrate 63 of the P-MOS transistors 11 and 31 which have been in a floating state.

On the other hand, when 5V is input from the output pad 20, the voltage between the gate and the source of the P-MOS transistor 41 of the 5V detection circuit 40 exceeds the threshold voltage.
The P-MOS transistor 41 is turned on, and outputs a 5V detection signal G13. As a result, the OR gate 23 outputs 5V, and the next-stage inverter 24 outputs 0V. By the output of the inverter 24, the output G11 of the NAND gate 21 becomes 5V, and the P-MOS transistor 11
Turns off.

When the output G11 supplied to the gate of the P-MOS transistor 11 becomes 5V, the N-well substrate 63 of the P-MOS transistor 11 also has 5V.
Gate-source voltage V of P-MOS transistor 11
GS becomes 0v, the P-MOS transistor 11 is completely turned off, and the above-mentioned current backflow is reliably prevented.

As described above, the 5 V output pad 20 (OU
The backflow of the current flowing from T) to the 3V power supply via the P-MOS transistor 11 can be completely prevented only by the P-MOS transistor 11.

On the other hand, when the OR gate 23 outputs 5V as a result of the input of 5V from the output pad 20, NO
The output G12 of the R gate 22 becomes 0V, and the N-MOS transistor 12 is also turned off. Thereby, the output pad 2
5v from 0 does not flow back to the ground side.

In short, when 5V is input from the output pad 20, the detection signal G13 becomes 5V via the P-MOS transistor 41, whereby the OR gate 23
Output 5v. As a result, regardless of the input signal IN and the enable signal EN, the signal G11
12 becomes 0V, and the P-MOS transistor 11 and N-
The MOS transistors 12 are both turned off. This P-MO
By turning off the S transistor 11 and the N-MOS transistor 12, 5V from the output pad 20 does not flow back to the 3.3V power supply side or the ground side.

This embodiment has the following advantages.

In the conventional output circuit shown in FIG. 7, a 3V output corresponding to 5V is realized with a 3.3V power supply.
As described above, there is a problem that the circuit area becomes four times as large as that of a normal output circuit (FIG. 6). Therefore, the present embodiment newly adds 5 v to the conventional technology of 3.3 v alone.
By using a power supply, an area of the main output circuit 10 on the pull-up side is reduced to 1/4 of that of the conventional circuit, thereby realizing an output circuit corresponding to 5V.

As a result, the area of each I / O section 52A on which the CMOS output circuit of this embodiment is mounted can be significantly reduced, which can greatly contribute to miniaturization of an LSI chip.

Next, a second embodiment of the present invention will be described.

In the second embodiment, when 5 v is input from the output pad 20 in the first embodiment, PM
The point where a leak current flows from the root of the OS transistor 41 and the N-MOS transistor 42 to the ground and the detection signal G13 is quickly 0 V due to the action of the P-MOS transistor 41 even when the output pad 20 changes from 5V to 0V. It is intended to reduce the power consumption and increase the speed of operation by improving the problem of not becoming a problem.

FIG. 5 shows a CM according to the second embodiment of the present invention.
FIG. 3 is a circuit diagram of an OS output circuit.

In the present embodiment, in order to achieve the low power consumption and high-speed operation in the first embodiment, in the configuration of FIG. 1, a 5V detection circuit 40 is newly added, and an inverter 45 and an N-MOS transistor 46 are newly added. It is replaced with the added 5v detection circuit 40A. In other words, the inverter 45 inverts the potential of the output pad 20 and performs N-MOS
It is supplied to the gate of the transistor 46. This N-MOS
The transistor 46 is connected in parallel with the N-MOS transistor 42 between the drain of the P-MOS transistor 41 and the ground.

According to the output circuit of this embodiment, when 5 V is input from the output pad 20, the inverter 45 outputs 0V.
And the N-MOS transistor 46 is turned off.
Thereby, the P-MOS transistor 41 and the N-MOS
The current flowing from the route of the transistor 42 can be reduced, and the power consumption of the circuit can be reduced.

Further, when the output pad 20 becomes 0 V,
As a result of the inverter 45 outputting 5v, the N-MOS 46
Turns on, and quickly sets 5v of the detection signal G13 to 0v.
Thereby, the operation of the circuit can be sped up.

[0068]

As described above in detail, according to the semiconductor output circuit of the first aspect, even if two transistors are not connected in series on the pull-up side as in the conventional circuit,
Backflow of current from the second power supply to the first power supply can be prevented only by the pull-up transistor. This allows
The circuit area can be greatly reduced as compared with the conventional circuit.

According to the semiconductor output circuit of the second aspect, in the first aspect, low power consumption and high-speed operation can be realized.

According to the CMOS output circuit of the third aspect, the same effect as that of the first aspect can be obtained, and the backflow of the current to the ground side can be prevented.

According to the CMOS output circuit of the fourth aspect, the third aspect has the same effect as the second aspect.

According to the terminal potential detection circuit of the fifth invention, the power consumption of the circuit can be reduced and the high-speed operation can be performed.

According to the semiconductor device of the sixth aspect, the area of the I / O section on which the semiconductor output circuit is mounted can be significantly reduced, which can greatly contribute to miniaturization of the LSI chip.

According to the semiconductor device of the seventh invention, C
The area of the I / O section on which the MOS output circuit is mounted can be significantly reduced, which can greatly contribute to miniaturization of the LSI chip.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a CMOS output circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a system in which a CMOS output circuit of the present invention is mounted.

FIG. 3 is a block diagram showing a configuration of an LSI chip 52 shown in FIG.

FIG. 4 is a schematic sectional structural view of a main output circuit 10 in the CMOS output circuit shown in FIG.

FIG. 5 is a circuit diagram of a CMOS output circuit according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram of a conventional general CMOS output circuit.

FIG. 7 shows a conventional CMOS output circuit (3V output corresponding to 5V).
FIG.

8 is a schematic sectional structural view of a main output circuit 200 in the CMOS output circuit shown in FIG.

[Description of Signs] 10 Main output circuit 11 P-MOS transistor for pull-up 12 N-MOS transistor for pull-down 20 Output pad 21 NAND gate (first pre-buffer) 22 NOR gate (second pre-buffer) 23 OR gate (logic circuit) 24 Inverter (logic circuit) 40 5v detection circuit G13 detection signal 31 P-MOS transistor for substrate potential setting 41 P-MOS transistor for potential detection 42 N-MOS transistor (resistance means) 43 Reference voltage P-MOS transistor for generation 44 N-MOS transistor for reference voltage generation 46 N-MOS transistor for potential adjustment 51, 52 LSI chip 52A I / O section 52B Random logic section 52C Macro block

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/8238 H03K 19/094 B 27/092 H03K 19/0948

Claims (7)

[Claims] 1. A pull-up transistor connected between a first power supply and an output node, the pull-up transistor being turned on / off by a first control signal, and a transistor for generating the first control signal based on input data. A buffer and a potential detector that outputs a detection signal of a potential corresponding to the second power supply when the potential of the output node is set to a level of a second power supply higher than the level of the first power supply by an external circuit. Wherein the pre-buffer is driven by the second power supply, and the first power supply to the N-well substrate of the pull-up transistor is supplied according to the potential of the output node. A base potential setting transistor to be turned on / off; and receiving the detection signal from the potential detection circuit, setting the first control signal to the level of the second power supply. And a logic circuit for outputting a second control signal to the pre-buffer. 2. The potential detection circuit, comprising: a potential detection transistor connected between the output node and a detection result node; a resistance means connected between the detection result node and a ground; A reference voltage for generating a reference voltage to be supplied to a control electrode of the potential detection transistor so that the potential detection transistor is turned off when the node is at or below the level of the first power supply and turned on at the level of the second power supply; And a charge adjustment transistor connected between the detection result node and ground and turned on when the potential of the output node is at the level of the first power supply and turned off when the potential of the second power supply is at the level of the second power supply. 2. The semiconductor output circuit according to claim 1, wherein: 3. A first P-channel MOS transistor for pull-up, which is connected between a first power supply and an output node and is turned on / off by a first control signal, is connected between the output node and ground. An N-channel MOS transistor for pull-down, which is connected between the first and second P-channel MOS transistors in a complementary manner with respect to the first P-channel MOS transistor according to a second control signal;
First and second pre-buffers for generating a second control signal and a second control signal, respectively, when the potential of the output node is set to a level of a second power supply higher than the level of the first power supply by an external circuit. A CMOS output circuit including a potential detection circuit that outputs a detection signal of a potential corresponding to the second power supply, wherein the first and second pre-buffers are driven by the second power supply; A second P-channel MOS transistor for setting a substrate potential for turning on / off the first power supply to the N-well substrate of one P-channel MOS transistor in accordance with the potential of the output node; In response to the detection signal, a third control signal for setting the first control signal to the level of the second power supply and setting the second control signal to the ground level, respectively. CMOS output circuit, characterized in that a logic circuit for outputting to the first and second pre-buffer. 4. The potential detection circuit, wherein: a third P-channel MOS transistor for potential detection connected between the output node and a detection result node; and a potential detection circuit connected between the detection result node and ground. And a third P-channel MOS transistor so as to turn off the third P-channel MOS transistor when the output node is lower than the level of the first power supply and to turn on the third P-channel MOS transistor when the output node is at the level of the second power supply. A reference voltage generating circuit for generating a reference voltage to be supplied to the gate of the second power supply, connected between the detection result node and ground, and turned on when the potential of the output node is at the level of the first power supply 4. The CMOS output circuit according to claim 3, wherein the CMOS output circuit comprises an N-channel MOS transistor for charge adjustment which is turned off at the level of the signal. 5. A first MOS transistor connected between a terminal of an external circuit and a detection result node, a resistor connected between the detection result node and ground, and a terminal of the external circuit. A reference voltage generator for generating a reference voltage to be supplied to the gate of the first MOS transistor so as to turn off when the level of the first power supply is lower than the level of the first power supply and to turn on when the level of the second power supply is higher than the first power supply. A potential between the detection result node and the ground, wherein the potential of the terminal of the external circuit is turned on when the potential of the first power supply is at the level of the first power supply and when the potential of the second power supply is at the level of the second power supply. Second MOS to be turned off
A terminal potential detection circuit including a transistor. 6. A semiconductor device comprising: an I / O unit for connecting to an external circuit; and an internal function block connected to the I / O unit, wherein the I / O unit is connected to the external circuit. A pull-up transistor connected between an output terminal to be operated and a first power supply and turned on / off by a first control signal; and a second power supply having a level higher than the level of the first power supply. A pre-buffer that is driven and generates the first control signal based on input data from the internal function block; and a second buffer when the potential of the output terminal is set to the level of the second power supply by the external circuit. And a potential detection circuit that outputs a detection signal of a potential corresponding to the power supply of the second power supply, and turning on / off the first power supply to the N-well substrate of the pull-up transistor in accordance with the potential of the output terminal.
A base potential setting transistor to be turned off, and a second control signal for receiving the detection signal from the potential detection circuit and setting the first control signal to the level of the second power supply. A semiconductor device comprising: a semiconductor output circuit having a logic circuit that outputs to a semiconductor device. 7. A semiconductor device comprising: an I / O section for connecting to an external circuit; and an internal function block connected to the I / O section, wherein the I / O section is connected to the external circuit. A first P-channel MOS transistor for pull-up, which is connected between the output terminal to be turned on and a first power supply and is turned on / off by a first control signal, and connected between the output terminal and ground. An N-channel MOS transistor for pull-down, which is turned on / off complementarily to the first P-channel MOS transistor by a second control signal; and a second transistor having a higher level than the level of the first power supply. The first and second pre-buffers, which are driven by the power supply of the first embodiment and generate the first and second control signals based on the input data from the internal functional block, respectively, and the potential of the output terminal is A potential detection circuit for outputting a detection signal of a potential corresponding to the second power supply when the level is set to the level of the second power supply by an external circuit; A second P-channel MOS transistor for setting a base potential to turn on / off the supply of one power supply in accordance with the potential of the output terminal; and receiving the detection signal from the potential detection circuit to perform the first control. A logic circuit for outputting a signal to the level of the second power supply and a third control signal for setting the second control signal to the ground level to the first and second pre-buffers. A semiconductor device comprising an output circuit.