JP3402947B2 - Address decoder - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for decoding an address signal in a semiconductor MOS memory,
In particular, the present invention relates to a technique for increasing the speed of the address decoder when the power supply voltage is lowered.

[0002]

2. Description of the Related Art A conventional logic gate used for increasing the speed of a MOS LSI when the power supply voltage is low is described in, for example, Japanese Patent Laid-Open No. 6-329823. When the power supply voltage is low, it is necessary to increase the size of the MOS transistor in order to secure the driving force of the MOS transistor. However, in this case, the parasitic capacitance increases and the speed decreases. Therefore, for example, when the driving power of the p-channel MOS transistor is smaller than that of the n-channel MOS transistor, the threshold voltage of the p-channel MOS transistor is set to the n-channel M transistor.
The driving force is increased by setting it lower than that of the OS transistor, and the size thereof is reduced to reduce the parasitic capacitance and speed up.

Conventional n using the logic gate as described above
The structure of the bit address decoder is shown in FIG. Also,
FIG. 6 shows details of the main part surrounded by the broken line in FIG. 1 is an address buffer, 2 ″ is an n-input NAND gate, 3 is an address bus connecting the n-th input contact of the address buffer 1 and the n-input NAND gate 2 ″,
C1 represents the parasitic capacitance of the address bus 3. V _DD is a positive power supply. In FIG. 6, n-input NAN
An address buffer similar to the address buffer 1 is connected to the 1st to n-1th input contacts of the D gate 2 ″ through an address bus similar to the address bus 3.

The address buffer 1 has a low threshold voltage and a small size (the ratio of the size compared to the n-channel transistor is smaller than that of a conventional one).
S-transistor QP ₁ and high threshold voltage n-channel M
It is composed of an OS transistor QN ₁ . Also, n
The input NAND gate 2 ″ has n p-channel MOS transistors QP ₂₁ , ..., Q, which are connected in parallel between the power supply contact and the output contact and have a low threshold voltage and a small size.
P _2n-1 , QP _2n and n n-channel MOS transistors QN ₂₁ , connected in series between the output contact and the ground,
.., QN _2n-1 , and QN _2n . In this way, the address buffer 1 and the n-input NAND gate 2 ″ are
Lowers the threshold voltage of the P-channel MOS transistor and reduces the size thereof to reduce the parasitic capacitance while increasing the driving force, thereby achieving higher speed.

When the threshold voltage of the MOS transistor is lowered, the subthreshold leakage current increases, so that in the n-input NAND gate 2 ", n connected in series is used.
Channel MOS transistor QN ₂₁ , ..., QN
And to increase the threshold voltage of _2n-1, QN _2n. As a result, at least one of the n-channel MOS transistors is
P-channel M with low threshold voltage as long as
OS transistors QP ₂₁ , ..., QP _2n-1 , QP _2n
Leakage current does not pose a problem.

[0006]

In the meantime, in the standby mode, the output of the address buffer 1 is controlled to the "L" level (low level voltage) in order to cut off the leak current of the n-input NAND gate 2 ", and the n-channel MOS transistor is controlled. It is necessary to cut off the transistors QN ₂₁ , ..., QN _2n-1 , QN _2n . However, in this case, the low threshold P channel MOS transistor QP _{1 of the} address buffer 1 is formed.
Since the voltage V _DD is applied between the source and drain of, the leakage current becomes a problem.

That is, in the conventional address decoder,
When using a low threshold voltage MOS transistor to increase the speed, the leak current of the address buffer 1 increases during standby, and especially when the address width is large,
There is a problem that the ratio of power consumption due to the leakage current increases.

The present invention has been made in view of the above points, and an object thereof is to increase the driving force and increase the speed by reducing the threshold voltage and the size of a MOS transistor having a small driving force. Another object of the present invention is to provide an address decoder capable of reducing the leak current of the address buffer during standby.

[0009]

Means for Solving the Problems To this end, the first invention, n input logic gates and, n number of address buffers connected via individual address bus for each input contact of the n-input logic gates And an n-input logic gate having a power contact, an output contact, and n p-channel MOS transistors of low threshold voltage connected in parallel between the power contact and the output contact. A low threshold voltage or a high threshold voltage n-1 n-channel MOS transistors connected in series to the output contact, and the first to nth of the input contacts.
The -1st input contact is individually connected to the gates of the 1st to n-1th transistors of the n p-channel MOS transistors, and is individually connected to the gates of the n-1 n-channel MOS transistors. The n-th input contact is connected to the source of a transistor on the opposite side of the n-1 n-channel MOS transistors from the side connected to the output contact, and the n-th input contact is connected via an inverter. Connected to the gate of the n-th transistor of the p-channel MOS transistor, and the p-channel MOS transistors of the n address buffers are transistors of low threshold voltage, and the potential of the n address buses is , The high level voltage is controlled during standby.

A second invention is an n-input logic gate and the n-input logic gate.
An address decoder comprising n address buffers connected to each input contact of an input logic gate via an individual address bus, wherein the n input logic gate comprises a power contact, an output contact and the power contact. A resistor element connected between the output contact and n-1 n-channel MOS transistors of low threshold voltage or high threshold voltage connected in series to the output contact, and Among the input contacts, the first to n-1th input contacts are
And individually connected to a gate of -1 n-channel MOS transistor, the n-th input contact, on the opposite side of the transistor and the side connected to the output contact of said n-1 n-channel MOS transistor Connected to the source,
The p channel MOS transistors of the n address buffers are composed of low threshold voltage transistors, and the potentials of the n address buses are controlled to a high level voltage during standby.

A third invention is an n-input logic gate and the n-input logic gate.
An address decoder comprising n address buffers connected to each input contact of an input logic gate via an individual address bus, wherein the n input logic gate comprises a ground contact, an output contact, and the ground contact. low threshold value and n pieces of n-channel MOS transistor of the voltage, n-1 series-connected low threshold voltage or the high threshold voltage to the output contacts are connected in parallel between the output contact P-channel MOS transistor, and the 1st to n-1th input contacts of the input contacts are connected to the 1st to n-1th transistors of the n n-channel MOS transistors. Gates of the n-1 p-channel MOS transistors, and an n-th input contact of the n-1 p-channel MOS transistors. The transistor is connected to the source of the transistor on the opposite side of the transistor connected to the output contact and to the gate of the n-th transistor of the n n-channel MOS transistors via an inverter. The n-channel MOS transistor of each address buffer is composed of a low threshold voltage transistor,
The potentials of the n address buses are controlled to a low level voltage during standby.

A fourth invention is an n-input logic gate and the n-input logic gate.
An address decoder comprising n address buffers connected to each input contact of an input logic gate via an individual address bus, wherein the n input logic gate comprises a ground contact, an output contact, and the ground contact. A resistance element connected between the output contact and n-1 p-channel MOS transistors of low threshold voltage or high threshold voltage connected in series to the output contact, and Among the input contacts, the first to n-1th input contacts are
Each of the n-th p-channel MOS transistors is connected to the gate of one of the p-channel MOS transistors, and the n-th input contact of the n-th p-channel MOS transistor is connected to the output contact. Connected to the source,
The n channel MOS transistors of the n address buffers are composed of low threshold voltage transistors, and the potentials of the n address buses are controlled to a low level voltage during standby.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIG. 1 is a diagram showing an address decoder according to a first embodiment of the present invention. The address buffer 1 and the address bus 3 are the same as those shown in FIG. 2 is an n-input logic gate according to the present embodiment. The n-input logic gate 2 has a small threshold voltage and a small size (small in comparison with the size of a conventional n-channel MOS transistor), and n p-channel MOS transistors Q connected in parallel.
_{P 21, ····, QP 2n-} 1, QP 2n and size at high threshold voltage of the n-1 of the series connection of the same degree as the conventional n-channel MOS transistor QN _21, · · · ·, QN
It is composed of _2n-1 and an inverter 4. The address buffer 1 is connected to the n-th input contact of the n-input logic gate 2 via the address bus 3.
An address buffer similar to the address buffer 1 is also connected to the first input contact via an address bus similar to the address bus 3.

In the conventional circuit shown in FIG. 6, the n-channel MOS transistor QN _2n in FIG. 6 is deleted, the address bus 3 is connected to the source of the _n- channel MOS transistor QN _2n-1 , and the inverter 4 generates the circuit. The difference is that the inverted signal of the address bus 3 is applied to the gate of the p-channel MOS transistor QP _2n . That is, of the first to nth input contacts, the nth input contact is connected to the source of the _n- channel MOS transistor QN _2n-1 .
Moreover, it is different in that it is connected to the gate of the n-channel MOS transistor QP _2n via the inverter 4.

In the first embodiment, the potential of the address bus 3 is controlled to the "H" level (high level voltage) (the potentials of other address buses are the same), so that the n-input logic gate 2 is in the standby state. Leakage current can be reduced. That is, at this time, the n-channel MOS transistor Q
Although N _{2n to} QN _2n-1 are turned on, the source of the _n- channel MOS transistor QN _2n-1 is cut off from the ground.
The leak current of the channel MOS transistors QP _{21 to} QP _2n-1 can be reduced. The output contact of the n-input logic gate 2 is
P than channel MOS transistor QP _2n conducts,
It becomes "H" level. At this time, since the n-channel MOS transistor QN _{1 of} the address buffer 1 is cut off, the leak current of the p-channel MOS transistor QP _{1 having} a low threshold voltage does not increase. That is, the leak current of the address buffer does not pose a problem even if the threshold voltage of the p-channel MOS transistor having a small driving force is lowered to increase the driving force and the size is reduced to achieve high speed. .

[Second Embodiment] FIG. 2 is a diagram showing an address decoder according to a second embodiment of the present invention. The same components as those described in FIG. 1 are designated by the same reference numerals. 2'is an n-input logic gate,
Series-connected n-channel MOS transistors QN _{21 to} QN
Gate Ru is connected to the n-1 th input contact of the _2n-1
Connect the door transistor QN _2n-1 of the address bus 3 to a source, and a resistor element R1 as a load between the drain and the positive power supply V _DD of the transistor QN _21. As the resistance element R1, it is also possible to use a MOS transistor having a predetermined internal resistance and controlled to be in a conductive state.

In the second embodiment, the above-mentioned first embodiment is used.
Besides the leakage current can be reduced the effect of as well as the address buffer for implementation in the form of, for parallel connection p-channel M
Since the OS transistor is not used, the input capacitance of the n-input logic gate 2'can be halved. Therefore, even if the address width is large, the parasitic capacitance of the address bus can be significantly reduced and the speed can be increased. There is also an effect that the chip area can be reduced.

[Third Embodiment] FIG. 3 shows a third embodiment, in which an address buffer 5, an n-input logic gate 6 and an address bus 7 connecting both of them are used. It is a figure. This embodiment is the one in which the polarity of the power supply and the polarity of the transistor of the circuit shown in FIG. 1 are inverted, and is suitable when the driving power of the P-channel MOS transistor is larger than that of the n-channel MOS transistor. That is, here, the n-channel MOS transistors QN ₅ and QN _{61 to} QN _6n are made small in size with a low threshold voltage to increase the driving force and speed up the P-channel MOS transistors QP ₅ and QP ₆₁ to. QP _6n-1 has a high threshold voltage and a normal size. C2 is a parasitic capacitance of the address bus 7. The address buffer 5 is connected to the nth input contact of the n-input logic gate 6 via the address bus 7. However, the same address buffer has the same address for the 1st to n-1th input contacts. Connected via a bus.

In the third embodiment, the address bus 7 connected to the nth input contact of the n-input logic gate 6 is used.
And controlling the potential of the same address bus connected to the 1st to (n-1) th input contacts to the "L" level so that the leak current of the n-input logic gate 6 at the standby time and the address buffer at the standby time thereof Leakage current can be reduced.

[0020] Figure 4 [Fourth Embodiment of] shows a fourth embodiment, the address buffer 5, n input logic gates 6 ', and an example of using the address bus 7 for connecting both FIG. This embodiment is the one in which the polarity of the power supply and the polarity of the transistor of the circuit shown in FIG. 2 are inverted, and is suitable when the driving power of the P channel MOS transistor is larger than that of the n channel MOS transistor. That is, here, n
The channel MOS transistor QN ₅ has a low threshold voltage and a small size to increase its driving force and speed up, and the P channel MOS transistors QP ₅ and QP ₆₁
.About.QP _6n-1 has a normal size of high threshold voltage. Although the address buffer 5 is connected to the nth input contact of the n-input logic gate 6'through the address bus 7, the same address buffer is also used for the first to n-1th input contacts. Connected via an address bus.

In the fourth embodiment, the above-mentioned third embodiment is used.
As in the case of the embodiment described above, in addition to the effect that the leak current of the address buffer can be reduced by controlling the potential of the address bus to the “L” level, since n-channel MOS transistors connected in parallel are not used, Since the input capacity of the input logic gate 6'can be halved, the parasitic capacity of the address bus can be significantly reduced and the speed can be increased even when the address width is large. There is also an effect that the chip area can be reduced.

[Other Embodiments] In the circuits shown in FIGS. 1 and 2 described above, n inputs are used.
N-channel MOS transistor Q of logic gates 2 and 2 '
_{N 21, ····, QN 2n-} 1 may be a transistor of a low threshold voltage. Further, in the circuits shown in FIGS. 3 and 4 , the n-channel MOS transistors QP ₆₁ , ..., QP _6n-1 of the n-input logic gates 6 and 6 ′ may be low threshold voltage transistors. .

[0023]

As described above, according to the first aspect of the present invention, the threshold voltage of the p-channel MOS transistor having a small driving force is set to be low to increase the driving force and the size thereof is reduced to achieve high speed operation. In the standby mode, the leak current of the n-input logic gate and the leak current of the address buffer can be reduced at the same time.

According to the second aspect of the invention, the threshold voltage of the p-channel MOS transistor having a small driving force is set low to increase the driving force and reduce the size to increase the speed, and at the time of standby. it is possible to reduce the leakage current of the address buffer, the input capacitance reduction of n input logic gates further, it is possible to chip area reduction.

According to the third aspect of the invention, the threshold voltage of the n-channel MOS transistor having a small driving force is set to be low to increase the driving force and reduce the size to achieve high speed, and at the time of standby. It is possible to reduce the leak current of the n-input logic gate and simultaneously reduce the leak current of the address buffer.

According to the fourth aspect of the invention, the threshold voltage of the n-channel MOS transistor having a small driving force is set to a low value to increase the driving force and reduce the size to increase the speed, and at the time of standby. The leak current of the address buffer can be reduced, and the input capacitance of the n-input logic gate and the chip area can be reduced.

As described above, according to the present invention, when applied to a low voltage semiconductor MOS memory having a large address width, it is effective in speeding up the address decoder and reducing power consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a circuit configuration of a part of an address decoder according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a partial circuit configuration of an address decoder according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a partial circuit configuration of an address decoder according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a partial circuit configuration of an address decoder according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of an n-bit address decoder.

FIG. 6 is a circuit diagram showing a partial circuit configuration of a conventional address decoder.

[Explanation of symbols]

1, 5: Address buffer 2, 2 ': n-input logic gate 2 ": n-input NAND gate 3, 7: Address bus 4, 8 : Inverter 6, 6': n-input logic gate C1, C2: Parasitic capacitance R1, R2: resistance element _{QP 1, QP 21, QP 2n} -1, QP 2n: p -channel MOS transistor QN _1, QN ₂₁ of the low threshold _{voltage, QN 2n-1, QN 2n} : n -channel high threshold voltage MOS transistors QP ₅ , QP ₅₁ , QP _5n-1 , QP _5n : high threshold voltage p-channel MOS transistors QN ₅ , QN ₅₁ , QN _5n-1 , QN _5n : low threshold voltage n-channel MOS transistors

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11C 11/413 G11C 11/4063

Claims (4)

(57) [Claims] 1. A and n input logic gates, in the address decoder comprising an n-number of address buffers connected via a respective address bus to each input contact of the n-input logic gates, said n input logic gate A power contact, an output contact, and n p-channel MOS transistors of low threshold voltage connected in parallel between the power contact and the output contact,
A low threshold voltage or high threshold voltage n-1 n-channel MOS transistor connected in series to the output contact, and the 1st to n-1th input of the input contacts The contact is one of the n p-channel MOS transistors.
The gates of the nth to n-1th transistors are individually connected to the gates of the n-1 n-channel MOS transistors, and the nth input contact is connected to the n-1 n-channel MOS transistors. The transistor is connected to the source of the transistor on the side opposite to the side connected to the output contact of the transistors and is connected to the gate of the n-th transistor of the n p-channel MOS transistors through an inverter, An address decoder characterized in that the p-channel MOS transistors of the address buffers are composed of low threshold voltage transistors, and the potentials of the n address buses are controlled to a high level voltage during standby. 2. A n input logic gates, in the address decoder comprising an n-number of address buffers connected via a respective address bus to each input contact of the n-input logic gates, said n input logic gate A power contact, an output contact, a resistance element connected between the power contact and the output contact, and a low threshold voltage or high threshold voltage n-1 connected in series to the output contact. And n-1 channel MOS transistors, and the first to n-1th input contacts of the input contacts are individually connected to the gates of the n-1 n-channel MOS transistors. And the n-th input contact is connected to the n-1
The n-channel MOS transistors are connected to the source of the transistor on the side opposite to the side connected to the output contact, and the p-channel MOS transistors of the n address buffers are transistors of low threshold voltage. An address decoder characterized in that the potentials of the n address buses are controlled to a high level voltage during standby. 3. A n input logic gates, in the address decoder comprising an n-number of address buffers connected via a respective address bus to each input contact of the n-input logic gates, said n input logic gate , a ground contact, an output contact, and the n n-channel MOS transistor connected in parallel, low threshold voltage between the ground contact and the output contact,
A n-th p-channel MOS transistor having a low threshold voltage or a high threshold voltage connected in series to the output contact, and the first to n-1th inputs of the input contact A contact is one of the n n-channel MOS transistors
The nth to n-1th transistors are individually connected to the gates of the n-1 p-channel MOS transistors, and the nth input contact is connected to the n-1 p-channel MOS transistors. The transistor is connected to the source of the transistor on the side opposite to the side connected to the output contact of the transistors, and is also connected to the gate of the n-th transistor of the n n-channel MOS transistors via an inverter, An address decoder characterized in that the n-channel MOS transistors of the address buffers are composed of transistors having a low threshold voltage, and the potentials of the n address buses are controlled to a low level voltage during standby. 4. A n input logic gates, in the address decoder comprising an n-number of address buffers connected via a respective address bus to each input contact of the n-input logic gates, said n input logic gate A ground contact, an output contact, a resistance element connected between the ground contact and the output contact, and a low threshold voltage or a high threshold voltage n-1 connected in series to the output contact. N p-channel MOS transistors, and the first to n-1th input contacts of the input contacts are individually connected to the gates of the n-1 p-channel MOS transistors, respectively. The input contact of n-1
Of the p-channel MOS transistors, the n-channel MOS transistors of the n address buffers are connected to the source of a transistor on the side opposite to the side connected to the output contact. An address decoder characterized in that the potentials of the n address buses are controlled to a low level voltage during standby.