JPH1031889A - Address decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the leakage current of an address decoder at the time of a standby by controlling the potential of (n) pieces of address busses to a high level voltage at the time of the stand by to lower threshold voltages of MOSFETs whose driving powers are small. SOLUTION: An n-input NAND gate 2 is provided with (n) pieces of p-channel MOSFETs QP21 ,... QP2-1 ,... QP2n which have low threshold value voltage and which are small in size and are connected on parallel and (n-1) piece of n- channel MOSFETs QN21 ,... QN2n-1 which have high threshold voltages and whose size are the same order as conventional sizes and which are connected in series and an inverter 4. An awddress buffer 1 is connected to the nth input junction point of the n-input NAND gate 2 via an address busses 3, however, the same address bufferes as the address buffer 1 are also connected to 1st-(n-1) th input junctions via the same address busses as the address busses 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for decoding an address signal in a semiconductor MOS memory.
In particular, the present invention relates to a technique for increasing the speed of an address decoder when a power supply voltage is lowered.

[0002]

2. Description of the Related Art A conventional logic gate used to increase the speed of a MOS LSI when a power supply voltage is low is described in, for example, Japanese Patent Application Laid-Open No. 6-329823. When the power supply voltage is low, it is necessary to increase the size of the MOS transistor in order to secure the driving force of the MOS transistor. However, in this case, the parasitic capacitance increases and the speed decreases. Therefore, for example, when the driving power of a p-channel MOS transistor is smaller than that of an n-channel MOS transistor, the threshold voltage of the p-channel MOS transistor is set to n channel M
Driving force is increased by setting it lower than that of the OS transistor, and by reducing its size, parasitic capacitance is reduced to achieve higher speed.

A conventional n using a logic gate as described above
FIG. 5 shows the configuration of the bit address decoder. Also,
FIG. 6 shows details of a main portion surrounded by a broken line in FIG. 1 is an address buffer, 2 "is an n-input NAND gate. 3 is an address bus connecting the address buffer 1 and the n-th input contact of the n-input NAND gate 2".
C1 represents the parasitic capacitance of the address bus 3. V _DD is a positive polarity power supply. In FIG. 6, n input NAN
An address buffer similar to the address buffer 1 is connected to the first to (n-1) th input contacts of the D gate 2 "via an address bus similar to the address bus 3.

The address buffer 1 has a low threshold voltage and a small size (the ratio of size is smaller than that of a conventional n-channel transistor).
N-channel M of S transistor QP ₁ and the high threshold voltage
And an OS transistor QN _1. Also, n
Input NAND gate 2 ", n pieces of p-channel MOS transistor QP _{2 1} small size parallel connected low threshold voltage between the power contacts and the output contact, · · · ·, Q
P _2n-1, QP _2n and, n pieces of n-channel MOS transistor QN _{2 1} connected in series between the output contact and the ground, ...
.., QN _2n-1 and QN _2n . Thus, the address buffer 1 and the n-input NAND gate 2 ″
Reduces the threshold voltage and the size of the p-channel MOS transistor, thereby reducing the parasitic capacitance and increasing the driving speed while increasing the driving force.

When the threshold voltage of the MOS transistor is lowered, the sub-threshold leakage current increases.
Channel MOS transistor QN _{2 1,} ····, QN
And to increase the threshold voltage of _2n-1, QN _2n. As a result, at least one of the n-channel MOS transistors
Low threshold voltage p-channel M
OS transistor _{QP 2 1, ····, QP 2n} -1, QP 2n
Leakage current does not pose a problem.

[0006]

By the way, at the time of stabilization, the output of the address buffer 1 is controlled to the "L" level (low level voltage) in order to cut off the leak current of the n-input NAND gate 2 ". transistor QN _{2 1,} ····, it is necessary to cut off the QN _2n-1, QN _2n. However, in this case, the low threshold p-channel MOS transistor QP _{1 of the} address buffer 1 is formed.
Since the voltage V _DD is applied between the source and the drain, the leakage current becomes a problem.

That is, in the conventional address decoder,
When the operation speed is increased by using a MOS transistor having a low threshold voltage, the leakage current of the address buffer 1 increases at the time of stabilization, and particularly when the address width is large,
There is a problem that the ratio of power consumption due to leakage current increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to reduce the threshold voltage of a MOS transistor having a small driving force and reduce the size thereof to increase the driving force and increase the speed. Another object of the present invention is to provide an address decoder capable of simultaneously reducing the leakage current of the address buffer during standby.

[0009]

For this purpose, a first aspect of the present invention provides an n-input NAND gate and n address buffers connected to respective input contacts of the n-input NAND gate via individual address buses. An n-input NAND gate comprising: a power contact;
An output contact, n low threshold voltage p-channel MOS transistors connected in parallel between the power supply contact and the output contact, and a low threshold voltage or a high threshold voltage connected in series to the output contact; N-1 n-channel MOs with threshold voltage
S transistor and one of the input contacts
The n th to n−1 th input contacts are individually connected to the gates of the first to n−1 th transistors of the n p channel MOS transistors, and Gates, and the n-th input contact is connected to the (n-1) n-channel M
Connected to the source of the transistor on the opposite side of the OS transistor from the side connected to the output contact and connected to the gate of the n-th transistor of the n p-channel MOS transistors via an inverter; The p-channel MOS transistors of the n address buffers are constituted by transistors having a low threshold voltage, and the potentials of the n address buses are controlled to a high level voltage at the time of standby.

A second invention is an n-input NAND gate,
An address decoder comprising: n address buffers connected to respective input contacts of the n-input NAND gate via respective address buses;
A gate connected to a power contact, an output contact, a resistance element connected between the power contact and the output contact, and a low threshold voltage or a high threshold voltage n connected in series to the output contact. -1 n-channel MOS transistors, and the first to n-1st input contacts among the input contacts are individually connected to the n-1 n-channel MOS transistor gates, respectively. The n-th input contact
The n-channel MOS transistor is connected to the source of the transistor on the side opposite to the side connected to the output contact, and the p-channel MOS transistors of the n address buffers are connected to a low threshold voltage transistor. And the potentials of the n address buses are controlled to a high level voltage at the time of stabilization.

According to a third aspect of the present invention, there is provided an address decoder comprising an n-input NOR gate and n address buffers connected to respective input contacts of the n-input NOR gate via individual address buses. An input NOR gate is connected in series with the ground contact, the output contact, n low threshold voltage n-channel MOS transistors connected in parallel between the ground contact and the output contact, and the output contact. N-1 p-channel MOS transistors having a low threshold voltage or a high threshold voltage, and the first to n-1st input contacts among the input contacts are connected to the n
First to n-th of the n-channel MOS transistors
It is individually connected to the gate of the first transistor and individually connected to the gates of the n-1 p-channel MOS transistors. The n-th input contact is connected to the n-1 p-channel MOS transistors. The n n-channel MOS transistors connected to the source of the transistor on the side opposite to the side connected to the output contact and via an inverter
Connected to the gate of the n-th transistor of the n-channel transistors, and
The S-transistor is constituted by a transistor having a low threshold voltage, and the potentials of the n address buses are controlled to a low-level voltage at the time of stabilization.

According to a fourth aspect of the present invention, there is provided an address decoder comprising an n-input NOR gate and n address buffers connected to respective input contacts of the n-input NOR gate via individual address buses. An input NOR gate having a ground contact, an output contact, a resistance element connected between the ground contact and the output contact, and a low threshold voltage or a high threshold voltage connected in series to the output contact; N-
One p-channel MOS transistor, and the first to (n-1) th input contacts of the input contacts are
The n-th input contacts are individually connected to the gates of the n-1 p-channel MOS transistors, and the n-th input contact is connected to the output contact of the n-1 p-channel MOS transistors on the opposite side. An n-channel MOS of the n address buffers connected to the source of the transistor
The transistors are constituted by transistors having a low threshold voltage, and the potentials of the n address buses are controlled to a low level voltage at the time of stabilization.

[0013]

[First Embodiment] FIG. 1 is a diagram showing an address decoder according to a first embodiment of the present invention. The address buffer 1 and the address bus 3 are the same as those shown in FIG. Reference numeral 2 denotes an n-input NAND gate according to the present embodiment. The n-input NAND gate 2 is composed of n parallel-connected n-channel p-channel MOS transistors QP _{2 1} ,... With a low threshold voltage and a small size (small compared to the size of a conventional n-channel MOS transistor). Q
And _{P 2n-1, QP 2n,} n -channel MOS transistor QN _{2 1} high threshold voltage series connection size comparable to conventional (n-1) in, ..., a QN _2n-1, And an inverter 4. The address buffer 1 is connected to the n-th input contact of the n-input NAND gate 2 via the address bus 3, and the same address buffer as the address buffer 1 is used for the first to (n−1) th input contacts. It is connected via an address bus similar to the bus 3.

6 differs from the conventional circuit shown in FIG. 6 in that the n-channel MOS transistor QN _2n in FIG. 6 is deleted, the address bus 3 is connected to the source of the _n- channel MOS transistor QN _2n-1 and the inverter 4 generates the circuit. Ile points so as to apply an inverted signal of the address bus 3 to the gate of the p-channel MOS transistor QP _2n. That is, the n-th input contact among the first to n-th input contacts is connected to the source of the _n- channel MOS transistor QN _2n-1 ,
The difference is that the transistor is connected to the gate of the n-channel MOS transistor QP _2n via the inverter 4.

In the first embodiment, the potential of the address bus 3 is controlled to the "H" level (high-level voltage) (the potentials of the other address buses are also the same), so that the n-input NA is set.
The leakage current of the ND gate 2 during standby can be reduced. That is, at this time, although the n-channel MOS transistor QN _{2 1} ~QN _2n-1 is turned on n-channel MO
Since the source of the S transistor QN _2n-1 is isolated from the ground, it can reduce the leakage current of the p-channel MOS transistor QP _{2 1} ~QP _2n-1. Since the p-channel MOS transistor QP _2n conducts, the output contact of the n-input NAND gate 2 is at the “H” level as in the conventional case. At this time, since the n-channel MOS transistor QN ₁ of the address buffer 1 is cut off, the leakage current of the low p-channel MOS transistor QP ₁ threshold voltage is not increased. That is, although the threshold voltage of the p-channel MOS transistor having a small driving force is lowered to increase the driving force and reduce the size to increase the speed, the leak current of the address buffer does not cause a problem. .

[Second Embodiment] FIG. 2 shows a second embodiment of the present invention.
FIG. 6 is a diagram showing an address decoder according to the embodiment. FIG.
The same components as those described in (1) are denoted by the same reference numerals.
2 'is a NAND gate of the n-input, n channel MOS series transistor QN _{2 1} ~QN _2n-1 of the inner n-
Connect the address bus 3 to the transistor QN _2n-1 of the source of the gate is connected to the first input contact, the resistance element as a load between the transistor QN _{2 1} of the drain and the positive power supply V _DD R1 Are connected. Incidentally, as the resistance element R1, a MOS transistor having a predetermined internal resistance and controlled in a conductive state can be used.

In the second embodiment, the first
In addition to the effect that the leak current of the address buffer can be reduced as in the case of the embodiment, the n-input NAND
Since the input capacitance of the gate 2 'can be halved, the parasitic capacitance of the address bus can be greatly reduced and the speed can be increased even when the address width is large. Also, there is an effect that the chip area can be reduced.

[Third Embodiment] FIG. 3 shows a third embodiment, in which an address buffer 5 and an n-input NOR are connected.
FIG. 3 is a diagram showing an example in which a gate 6 and an address bus 7 for connecting both are used. This embodiment is obtained by inverting the polarity of the power supply and the polarity of the transistor in the circuit shown in FIG. 1, and is suitable when the p-channel MOS transistor has a larger driving force than the n-channel MOS transistor. That is, here, n-channel MOS transistor QN _5, the QN _{6 1} ~QN _6n achieving its driving force increase and acceleration as having a small size at a low threshold voltage, p-channel MOS transistor QP _5, QP _{6 1} to
QP _6n-1 has a high threshold voltage and a normal size. C2 is a parasitic capacitance of the address bus 7. In addition,
The address buffer 5 is connected to the n-th input contact of the n-input NOR gate 6 via the address bus 7,
Similar address buffers are also connected to the first to (n-1) th input contacts via similar address buses.

In the third embodiment, an n-input NOR
By controlling the potentials of the address bus 7 connected to the n-th input contact of the gate 6 and the similar address buses connected to the first to (n-1) -th input contacts to "L" level, the n-input NOR The leakage current of the gate 6 during standby and the leakage current of the address buffer during standby can be reduced.

[Fourth Embodiment] FIG. 4 shows a fifth embodiment, in which an address buffer 5 and an n-input NOR are provided.
A gate 6 'and an address bus 7 connecting them
It is a figure which shows the example which used. This embodiment is shown in FIG.
In this case, the polarity of the power supply and the polarity of the transistor in the circuit shown in FIG. In other words, in this case, the n-channel MOS transistor QN ₅ aims to the driving force increases and the speed as having a small size at a low threshold voltage, a p-channel MOS transistor _{QP 5, QP 6 1 ~QP 6n} -1 The size of the high threshold voltage is normal. Note that n
The address buffer 5 is connected to the n-th input contact of the input NOR gate 6 ′ via the address bus 7.
Similar address buffers are also connected to the first to (n-1) th input contacts via similar address buses.

In the fourth embodiment, the third embodiment
By controlling the potential of the address bus to the "L" level in the same manner as in the embodiment of the third embodiment, the leak current of the address buffer can be reduced. In addition, since n-channel MOS transistors connected in parallel are not used, n Since the input capacitance of the input NOR gate 6 'can be reduced by half, even if the address width is large, the parasitic capacitance of the address bus can be greatly reduced and the speed can be increased. Also, there is an effect that the chip area can be reduced.

[0022] [Other Embodiments] Incidentally, FIG. 1, in the circuit shown in FIG. 2, n input n-channel MOS transistor QN _{2 1} of NAND gate 2, 2 'described above, ...
.. QN _2n-1 may be a low threshold voltage transistor. Further, FIG. 3, in the circuit shown in FIG. 3, n input n-channel MOS transistor QP _{6 1} of NOR gate 6,6 ', ···· QP _{6n -1} may be a transistor of a low threshold voltage .

[0023]

As described above, according to the first aspect of the present invention, the threshold voltage of a p-channel MOS transistor having a small driving force is set low to increase the driving force and to reduce the size to increase the speed. In addition, the leak current of the address buffer can be reduced simultaneously with the leak current of the n-input NAND gate during standby.

Further, according to the second aspect of the present invention, the threshold voltage of the p-channel MOS transistor having a small driving force is set low to increase the driving force and reduce the size to increase the speed. The leak current of the address buffer can be reduced, and the n-input NAND
The input capacity of the gate and the chip area can be reduced.

According to the third aspect of the present invention, while the threshold voltage of the n-channel MOS transistor having a small driving force is set low to increase the driving force and reduce the size to increase the speed, the standby time is reduced. The leak current of the address buffer can be reduced simultaneously with the leak current of the n-input NOR gate.

Further, according to the fourth aspect of the present invention, the threshold voltage of the n-channel MOS transistor having a small driving force is set low to increase the driving force and reduce the size to increase the speed. The leak current of the address buffer can be reduced, the input capacity of the n-input NOR gate can be reduced, and the chip area can be reduced.

As described above, according to the present invention, by applying the present invention to a low-voltage semiconductor MOS memory having a large address width, the effect of increasing the speed of an address decoder and reducing power consumption is significant.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a partial circuit configuration of an address decoder according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a partial circuit configuration of an address decoder according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a partial circuit configuration of an address decoder according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a partial circuit configuration of an address decoder according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of an n-bit address decoder.

FIG. 6 is a circuit diagram showing a partial circuit configuration of a conventional address decoder.

[Explanation of symbols]

1, 5: address buffer, 2, 2 ', 2 ": n input N
AND gates, 3,7: address bus, 4: inverter, 6,6 ': n-input NOR gate, C1, C2: parasitic capacitance, R1, R2: resistance _{elements, QP 1, QP 2 1,} QP
_2n-1, QP _2n: p-channel MOS transistors of low threshold _{voltage, QN 1, QN 2 1,} QN 2n-1, QN 2n: n -channel MOS transistor having a high threshold voltage, QP _5, Q
_{P 5 1, QP 5n -1,} QP 5n: p -channel MOS transistor having a high threshold _{voltage, QN 5, QN 5 1,} QN 5n-1, QN
_5n : Low threshold voltage n-channel MOS transistor.

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[Procedure amendment]

[Submission date] August 29, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Name of invention

[Correction method] Change

[Correction contents]

[Title of the Invention] Address decoder

Claims (4)

[Claims] An n-input NAND gate and an n-input NAN
An address decoder comprising n address buffers connected to each input contact of a D-gate via an individual address bus, the n-input NAND gate being connected to a power contact, an output contact, the power contact and the power contact. Low threshold voltage n p-channel MOS transistors connected in parallel between the output contact and n-1 low threshold voltage or high threshold voltage n-1 MOS transistors connected in series to the output contact; an n-channel MOS transistor, and the first to (n-1) th input contacts among the input contacts are connected to one of the n p-channel MOS transistors.
Connected to the gates of the nth to n-1st transistors and individually connected to the gates of the (n-1) n-channel MOS transistors. The nth input contact is connected to the (n-1) n-channel MOS transistors. Connected to the source of the transistor on the side opposite to the side connected to the output contact of the transistors, and connected to the gate of the n-th transistor of the n p-channel MOS transistors via an inverter; An address decoder, wherein the p-channel MOS transistors of the address buffers are constituted by transistors having a low threshold voltage, and the potentials of the n address buses are controlled to a high level voltage at the time of standby. 2. An n-input NAND gate and said n-input NAN
An address decoder comprising n address buffers connected to each input contact of a D-gate via an individual address bus, the n-input NAND gate being connected to a power contact, an output contact, the power contact and the power contact. A resistance element connected between the output contact and a low threshold voltage or a high threshold voltage n-1 n-channel MOS transistors connected in series to the output contact; The first to (n-1) th input contacts of the contacts are individually connected to the (n-1) n-channel MOS transistor gates, and the nth input contact is connected to the (n-1) n-channel MOS transistors. Connected to the source of a transistor on the side opposite to the side connected to the output contact, and connecting the p-channel MOS transistors of the n address buffers to a low threshold voltage. Address decoder constituted by pressure of the transistor, the potential of the n address bus, characterized in that so as to control the high voltage during Sutaibai. 3. An address decoder comprising an n-input NOR gate and n address buffers connected to respective input contacts of the n-input NOR gate via respective address buses, wherein the n-input NOR gate is , Ground contact, output contact,
N n-channel MOS transistors of low threshold voltage connected in parallel between the ground contact and the output contact;
A low-threshold voltage or a high-threshold voltage n-1 p-channel MOS transistor connected in series to the output contact, and a first to (n-1) -th input of the input contact The contact is connected to one of the n n-channel MOS transistors.
To the gates of the (n-1) -th transistors and to the gates of the (n-1) p-channel MOS transistors, respectively, and connect the n-th input contact to the (n-1) p-channel MOS transistors. A transistor connected to a source of a transistor on a side opposite to a side connected to the output contact of the transistors, and connected to a gate of an n-th transistor of the n n-channel MOS transistors via an inverter; An address decoder, wherein the n-channel MOS transistors of the address buffers are constituted by low-threshold-voltage transistors, and the potentials of the n address buses are controlled to a low-level voltage at the time of standby. 4. An address decoder comprising an n-input NOR gate and n address buffers connected to respective input contacts of the n-input NOR gate via individual address buses, wherein the n-input NOR gate is , Ground contact, output contact,
Consisting of a resistance element connected between the ground contact and the output contact, and n-1 p-channel MOS transistors of low threshold voltage or high threshold voltage connected in series to the output contact And the first to (n-1) th input contacts of the input contacts are individually connected to the gates of the n-1 p-channel MOS transistors, and the nth input contact is connected to the n-1
The n-channel MOS transistors of the n address buffers are connected to a source of a transistor on a side opposite to a side connected to the output contact of the p-channel MOS transistors. An address decoder, wherein the potentials of the n address buses are controlled to a low level voltage at the time of stabilization.