JP3070373B2 - Level shifter circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shifter circuit which is essential when connecting circuits having different power supply voltages.

[0002]

2. Description of the Related Art A conventional level shifter circuit will be described.

FIG. 2 shows a conventional level shifter circuit.
Reference numerals 1 and 2 denote low power supply voltage operation inverters, 3 denotes a high power supply voltage operation inverter, 4 denotes a high power supply voltage source, 5 and 6 denote N-channel (hereinafter referred to as Nch) MOS transistors, and 7 and 8 denote P-channel (hereinafter referred to as Pch). MOS transistors 9 are input signal terminals from a low power supply voltage operation circuit, 10
Is an output terminal to the high power supply voltage operation circuit, and 11 is an NchMO
A node where the drain of the S transistor 5 and the drain of the PchMOS transistor 7 are connected, and 12 is an NchMO
This is a node where the drain of the S transistor 6 and the drain of the PchMOS transistor 8 are connected.

The operation of the level shifter circuit configured as described above will be described below.

[0005] Input signal terminal 9 from low power supply voltage operation circuit
When a signal that changes from a lower level to a higher level is input, the output signal of the low power supply voltage operation inverter 1 changes from a higher level to a lower level. At that time, the on-resistance of the NchMOS transistor 6 gradually increases,
The voltage between the source and the drain of the S transistor 6 increases. Almost simultaneously, the output signal from the low power supply voltage operation inverter 2 changes from the low level to the high level, and the NchMOS
When the transistor 5 is turned on, the on-resistance gradually decreases,
The source-drain voltage of the NchMOS transistor 5 decreases.

[0006] By the operation of the NchMOS transistors 5 and 6 as described above, the gate voltage of the PchMOS transistor 8 decreases and the drain voltage of the PchMOS transistor 8 increases. As a result, the gate voltage of the PchMOS transistor 7 increases, and when the signal of the input signal terminal 9 from the low power supply voltage operation circuit eventually becomes high,
NchMOS transistor 5 is completely turned on, and node 1
The voltage of 1 becomes 0V. NchMOS transistor 6 is completely turned off, and the voltage at node 12 becomes equal to high power supply voltage source 4. At this time, the PchMOS transistor 7 becomes non-conductive, and the PchMOS transistor 8
Is conducted, and the potential of the output terminal to the high power supply voltage operation circuit becomes equal to the high power supply voltage by the high power supply voltage operation inverter 3.

On the other hand, when a signal that changes from a high level to a low level is input from the input signal terminal 9 from the low power supply voltage operation circuit, the output signal of the low power supply voltage operation inverter 1 changes from the low level to the high level. I do. At that time, Nch
The MOS transistor 6 conducts, and the on-resistance gradually decreases, so that the voltage between the source and the drain of the Nch MOS transistor 6 decreases. Almost simultaneously, the output signal from the low power supply voltage operation inverter 2 changes from high level to low level, the on-resistance of the NchMOS transistor 5 gradually increases, and the source-drain voltage of the NchMOS transistor 5 increases.

[0008] By the operation of the NchMOS transistors 5 and 6 as described above, the gate voltage of the PchMOS transistor 7 decreases, and the drain voltage of the PchMOS transistor 7 increases. Thereby, the gate voltage of PchMOS transistor 8 increases. When the signal at the input signal terminal 9 from the low power supply voltage operation circuit eventually goes low, the NchMOS transistor 5 is completely turned off, and the voltage at the node 11 becomes equal to the high power supply voltage source 4.
Further, the NchMOS transistor 6 is completely turned on, and the voltage of the node 12 becomes 0V. At that time, PchMOS
The transistor 7 conducts, and the PchMOS transistor 8
Is non-conductive, and the potential of the output terminal to the high power supply voltage operation circuit becomes 0 V by the high power supply voltage operation inverter 3.

[0009]

With the conventional level shifter circuit, it has been possible to input an output signal from a low power supply voltage operation circuit to a high power supply voltage operation circuit.

However, in the above-described conventional configuration, for example, when the input signal to the input signal terminal 9 changes from a high level to a low level, the NchMOS transistor 6
Is turned on, the PchMOS transistor 7 is turned on, and two steps are required for the operation such that the node 11 changes from a low level to a high level. On the other hand, when the input signal of the input signal terminal 9 changes from the low level to the high level, similarly, two steps are required for the node 12 to change from the low level to the high level, and it is difficult to operate at high speed.

In the present invention, the above-mentioned conventional problem is solved.
It is an object of the present invention to provide a level shifter circuit in which conversion of a signal level from a low power supply voltage operation circuit to a high power supply voltage operation circuit is speeded up by making it possible to change the potential of 1 or the node 12 in one step. .

[0012]

In order to achieve this object, a level shifter circuit according to the present invention has a drain connected to a high power supply voltage source, a gate connected to an output of a low power supply voltage operation inverter, and two sources connected. Among the PchMOS transistors, the drain of the first PchMOS transistor, the gate of the second PchMOS transistor, and the second NchM
An NchMOS transistor connected to the drain of the OS transistor and an NchMOS transistor whose source is connected to the gate of the first PchMOS transistor, the drain of the second PchMOS transistor, and the drain of the first NchMOS transistor are added to the conventional level shifter circuit. Circuit configuration.

[0013]

Function: NchMO with drain connected to high power supply voltage source
With the S transistor, the PchMOS transistor can directly start to turn off without waiting for the other PchMOS transistor to turn on, so that the drain voltage of the PchMOS transistor can be reduced at a high speed. The conversion of the signal level to the operation circuit becomes faster.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of a level shifter circuit according to an embodiment of the present invention. 1, 2 are inverters operating at a low power supply voltage, 3 is an inverter operating at a high power supply voltage, 4 is a high power supply voltage source, 5, 6, 13, and 14 are Nch MOS transistors,
7, 8 are PchMOS transistors, 9 is an input signal terminal from the low power supply voltage operation circuit, 10 is an output terminal to the high power supply voltage operation circuit, 11 is a node connecting the drain of the NchMOS transistor 5 and the PchMOS transistor 7, 12 Is the drain of NchMOS transistor 6 and P
This is a node to which the drain of the chMOS transistor 8 is connected.

The operation of the level shifter circuit configured as described above will be described below.

Input signal terminal 9 from low power supply voltage operation circuit
When a signal that changes from a lower level to a higher level is input, the output signal of the inverter 1 that operates at a lower power supply voltage changes from a higher level to a lower level. At that time, NchMOS
The on-resistance of the transistors 6 and 14 gradually increases, and Nc
The source-drain voltages of the hMOS transistors 6 and 14 increase. Almost simultaneously, the output signal from the low power supply voltage operation inverter 2 changes from the low level to the high level, and N
The on-resistance of the channel MOS transistors 5 and 13 is gradually reduced and the NchMOS transistors 5 and 13 are turned on.
3, the source-drain voltage decreases. NchMOS
When the transistor 13 is turned on, the gate potential of the PchMOS transistor 7 rises to the intermediate potential, and the on-resistance increases. Thereby, the potential of node 11 is reduced by NchMOS transistor 5. At the same time, the on-resistance of the PchMOS transistor 8 decreases due to the decrease in the potential of the node 11, and the potential of the node 12 increases. When the input signal terminal from the low power supply voltage operation circuit becomes completely high, the NchMOS transistors 5, 13
Is on, NchMOS transistors 6 and 14 are off, P
The chMOS transistor 7 is turned off and the PchMOS transistor 8 is turned on, so that the potential of the high power supply voltage operation circuit output terminal 10 becomes equal to the high power supply voltage and is stabilized.

On the other hand, when a signal that changes from a high level to a low level is input from the input signal terminal 9 from the low power supply voltage operation circuit, the output signal of the low power supply voltage operation inverter 1 changes from the low level to the high level. . At that time, NchM
The on-resistances of the OS transistors 6 and 14 gradually decrease, and the source-drain voltages of the NchMOS transistors 6 and 14 decrease. At substantially the same time, the output signal from the low power supply voltage operation inverter 2 changes from the high level to the low level, the NchMOS transistors 5 and 13 conduct, the on-resistance thereof gradually decreases, and the source / drain of the NchMOS transistors 5 and 13 increase. Voltage rises. Nc
When the hMOS transistor 14 is turned on, the PchM
The gate potential of the OS transistor 8 rises to the intermediate potential, and its on-resistance increases. Thereby, NchM
The potential of the node 12 is reduced by the OS transistor 6. At the same time, Pc
The on-resistance of the hMOS transistor 7 decreases, and the node 1
The potential of 1 rises. When the input signal terminal from the low power supply voltage operation circuit is completely low, the NchMOS transistors 5 and 13 are turned off, and the NchMOS transistors 6 and 6 are turned off.
14 is on, PchMOS transistor 7 is on, Pc
The hMOS transistor 8 is turned off, and the potential of the high power supply voltage operation circuit output terminal 10 is stabilized at 0V.

[0019]

According to the present invention, by providing an NchMOS transistor, a P-channel MOS transistor having a previous state (on) is maintained.
The effect of quickly turning off the chMOS transistor shortens the operation transition time (time during which a through current flows), and speeds up the level shifter circuit, which is essential when the different power supply operation circuit is integrated into one chip with a MOS integrated circuit. In addition, it is possible to provide a high-speed, high-performance electronic circuit / system that can reduce power consumption.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a level shifter circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a conventional level shifter circuit;

[Explanation of symbols]

1, low power supply voltage operation inverter 3 high power supply voltage operation inverter 4 high power supply voltage source 5, 6 N-channel MOS transistor 7, 8 P-channel MOS transistor 9 input signal terminal (input signal terminal of low power supply voltage operation circuit) 10 high Output terminal to power supply voltage operation circuit 11, 12 Node 13, 14 N-channel MOS transistor

Claims (1)

(57) [Claims] 1. Two Ps connected to a source with a high power supply voltage
An output signal of the low power supply voltage operation circuit is connected to the gate of the first N-channel MOS transistor, and the drain of the first N-channel MOS transistor is connected to the gate of the first P-channel MOS transistor. The second N-channel MOS transistor is connected to the drain of the second P-channel MOS transistor, and the signal of the opposite phase of the output signal of the low power supply voltage operation circuit is connected to the gate of the second N-channel MOS transistor
Connect the drain of the OS transistor to the first P-channel MO
In addition to the configuration in which the gate of the S transistor is connected to the drain of the second P-channel MOS transistor, the drains of the third and fourth N-channel MOS transistors are connected to a high power supply voltage source. Is connected to the gate of the first N-channel MOS transistor, the source of the third N-channel MOS transistor is connected to the drain of the first P-channel MOS transistor and the gate of the second P-channel MOS transistor, The gate of the fourth N-channel MOS transistor is connected to the gate of the second N-channel MOS transistor, and the source of the fourth N-channel MOS transistor is connected to the gate of the first P-channel MOS transistor and the second P-channel MOS transistor. Drain and high power Connected to the input of the pressure operation inverter,
A level shifter circuit that uses the output of the high power supply voltage operation inverter as the output to the high power supply voltage operation circuit.