JP2654275B2 - Bidirectional buffer - Google Patents
Bidirectional bufferInfo
- Publication number
- JP2654275B2 JP2654275B2 JP3193352A JP19335291A JP2654275B2 JP 2654275 B2 JP2654275 B2 JP 2654275B2 JP 3193352 A JP3193352 A JP 3193352A JP 19335291 A JP19335291 A JP 19335291A JP 2654275 B2 JP2654275 B2 JP 2654275B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- terminal
- input
- output
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は双方向バッファに関し、
特にＣＭＯＳ回路におけるトランジスタ−トランジスタ
・ロジック（ＴＴＬ）出力双方向バッファに関する。BACKGROUND OF THE INVENTION The present invention relates to a bidirectional buffer.
In particular, it relates to a transistor-transistor logic (TTL) output bidirectional buffer in a CMOS circuit.
【０００２】[0002]
【従来の技術】従来、この種の双方向バッファは、図３
に示す様に、バッファが出力状態になる時に入力端子２
３に加わる内部（例えば半導体チップ内）からの信号を
双方向端子２５へと出力させる出力回路部２２と、バッ
ファが入力状態になった時に、双方向端子２５に加わる
外部からの信号を内部へと伝える入力回路部２１とから
構成され、双方向バッファが出力状態にある時には入力
回路部の入力部２６もそれと同電位となる構成を有して
いる。2. Description of the Related Art Conventionally, a bidirectional buffer of this kind has been disclosed in FIG.
As shown in the figure, the input terminal 2
An output circuit unit 22 for outputting a signal from the inside (for example, inside the semiconductor chip) applied to the bidirectional terminal 3 to the bidirectional terminal 25, and an external signal applied to the bidirectional terminal 25 when the buffer enters an input state. And the input section 26 of the input circuit section has the same potential as that when the bidirectional buffer is in the output state.
【０００３】[0003]
【発明が解決しようとする課題】この従来のＴＴＬ出力
双方向バッファにおいては、双方向バッファが出力状態
で高（Ｈｉｇｈ）レベル（約３Ｖ）が出力されている時
には、入力回路部２１の入力部２６も同電位となってし
まう為、入力回路部２１の内部に定常的なリーク電流が
流れてしまい、消費電力の増大につながるという欠点が
ある。In the conventional TTL output bidirectional buffer, when the bidirectional buffer is in the output state and a high level (about 3 V) is output, the input section of the input circuit section 21 is output. 26 also has the same potential, so that a steady leakage current flows inside the input circuit section 21, which leads to an increase in power consumption.
【０００４】本発明の目的は、前記欠点を解決し、リー
ク電流による消費電力が増大しないようにした双方向バ
ッファを提供することにある。[0004] It is an object of the present invention to provide a bidirectional buffer which solves the above-mentioned drawbacks and does not increase power consumption due to leakage current.
【０００５】[0005]
【課題を解決するための手段】本発明の双方向バッファ
の構成は、入力回路部と出力回路部とを備えた双方向バ
ッファにおいて、イネーブル端子と前記出力回路部の入
力端子との信号がＡＮＤ回路またはＮＡＮＤ回路の機能
を有する回路の入力端子に接続され、前記ＡＮＤ回路ま
たはＮＡＮＤ回路の機能を有する回路の出力端子がトラ
ンジスタのゲート端子に接続され、前記トランジスタの
ソース端子，ドレイン端子のうち一方が電源に他方が前
記入力回路部に接続されることを特徴とする。According to the present invention, there is provided a bidirectional buffer comprising a bidirectional buffer having an input circuit and an output circuit, wherein a signal between an enable terminal and an input terminal of the output circuit is ANDed. An output terminal of the AND circuit or the circuit having the function of the NAND circuit is connected to a gate terminal of the transistor; and one of a source terminal and a drain terminal of the transistor is connected to the input terminal of the circuit or the circuit having the function of the NAND circuit. Are connected to a power supply and the other is connected to the input circuit section.
【０００６】[0006]
【実施例】図１は本発明は第１の実施例の双方向バッフ
ァを示す回路図である。図１において、本実施例の双方
向バッファは、イネーブル端子４と出力回路部２の入力
端子３とがＡＮＤ回路５の入力端子に接続され、その出
力端子がＰチャネル（ｃｈ）トランジスタ６のゲート端
子に接続され、さらにそのＰｃｈトランジスタ６のソー
ス端子が電源（５Ｖ）に，ドレイン端子が入力回路部１
のＰｃｈトランジスタ７のソース端子と接続される。FIG. 1 is a circuit diagram showing a bidirectional buffer according to a first embodiment of the present invention. In the bidirectional buffer of this embodiment, an enable terminal 4 and an input terminal 3 of an output circuit unit 2 are connected to an input terminal of an AND circuit 5, and the output terminal of the bidirectional buffer is a gate of a P-channel (ch) transistor 6. The Pch transistor 6 has a source terminal connected to a power supply (5 V) and a drain terminal connected to the input circuit unit 1.
Is connected to the source terminal of the Pch transistor 7.
【０００７】双方向バッファが出力状態でＨｉｇｈレベ
ル（約３Ｖ）を出力する場合には、イネーブル端子４と
入力端子３は共にＨｉｇｈベレ（５Ｖ）の電位になる
為、ＡＮＤ回路５の出力はＨｉｇｈレベル（５Ｖ）とな
り、Ｐｃｈトランジスタ６は完全にオフ（ＯＦＦ）の状
態となる。また入力回路部１の入力部９の電位もＨｉｇ
ｈレベル（約３Ｖ）となる為、入力回路部Ｎｃｈトラン
ジスタ８は完全にオン（ＯＮ）状態、入力回路部１のＰ
ｃｈトランジスタ７に流れるソース−ドレイン電流ＩSD
はＰｃｈトランジスタ６が完全にＯＦＦ状態にある為、
ほぼ零となる。When the bidirectional buffer outputs a High level (about 3 V) in the output state, the output of the AND circuit 5 is High because both the enable terminal 4 and the input terminal 3 have the potential of High level (5 V). Level (5 V), and the Pch transistor 6 is completely turned off. The potential of the input unit 9 of the input circuit unit 1 is also high.
The input circuit section Nch transistor 8 is completely turned on (ON) because the input circuit section is at the h level (about 3 V).
source-drain current I SD flowing through channel transistor 7
Is because the Pch transistor 6 is completely off.
It becomes almost zero.
【０００８】従って入力回路部１に流れる定常電流は大
幅に少なくなり、従来の回路に比べて消費電力は減少す
る。Accordingly, the steady current flowing through the input circuit section 1 is greatly reduced, and the power consumption is reduced as compared with the conventional circuit.
【０００９】図２は本発明の第２の実施例の双方向バッ
ファを示す回路図である。FIG. 2 is a circuit diagram showing a bidirectional buffer according to a second embodiment of the present invention.
【００１０】図２において、本実施例では、図１のＡＮ
Ｄ回路５がＮＡＮＤ回路１４と置きかわり、その出力端
子が、ソース端子を電源（５Ｖ）に，ドレイン端子を入
力回路部１０の入力部１６にそれぞれ接続されたＰｃｈ
トランジスタ１５のゲート端子に、さらにはＰｃｈトラ
ンジスタとＮｃｈトランジスタとから構成されるトラン
スミッションゲート１７のうちＮｃｈトランジスタのゲ
ート端子，及びインバータ回路１８の入力端子に接続さ
れ、インバータ回路１８の出力端子がトランスミッショ
ンゲート１７のＰｃｈトランジスタのゲート端子に接続
される。その他は、図１と同様である。In FIG. 2, in the present embodiment, the AN of FIG.
The D circuit 5 replaces the NAND circuit 14, and its output terminal is a Pch whose source terminal is connected to the power supply (5 V) and whose drain terminal is connected to the input unit 16 of the input circuit unit 10.
The gate terminal of the transistor 15 is connected to the gate terminal of the Nch transistor of the transmission gate 17 composed of a Pch transistor and an Nch transistor, and the input terminal of the inverter circuit 18. The output terminal of the inverter circuit 18 is connected to the transmission gate. 17 are connected to the gate terminals of the Pch transistors. Others are the same as FIG.
【００１１】双方向バッファが出力状態でＨｉｇｈレベ
ル（約３Ｖ）を出力している時を同様に考えてみると、
イネーブル端子１３と入力端子１２はＨｉｇｈレベル
（５Ｖ）となり、ＮＡＮＤ回路１４の出力はＬｏｗレベ
ル（０Ｖ）となる。ゆえにトランスミッションゲート１
７はＯＦＦ状態，Ｐｃｈトランジスタ１５はＯＮ状態と
なり、入力回路部１０の入力部１６の電位はほぼ電源電
圧（５Ｖ）と等しくなる。Similarly, when the bidirectional buffer is outputting a High level (about 3 V) in the output state,
The enable terminal 13 and the input terminal 12 are at a high level (5 V), and the output of the NAND circuit 14 is at a low level (0 V). Therefore transmission gate 1
7 is in an OFF state, the Pch transistor 15 is in an ON state, and the potential of the input section 16 of the input circuit section 10 is substantially equal to the power supply voltage (5 V).
【００１２】ここで、入力回路部１０の入力部１６に５
Ｖと３Ｖという２種の電位が加わった場合を考えてみる
と、入力回路部１０のＮｃｈトランジスタ２０はどちら
の電位が加わったとしても完全にＯＮ状態となっている
為、入力回路部１０に流れる定常電流はＰｃｈトランジ
スタ１９に流れるソース・ドレイン電流ＩSDにほぼ等し
くなる。すなわち、次式のようになる。Here, 5 is input to the input section 16 of the input circuit section 10.
Considering the case where two kinds of potentials, V and 3V, are applied, the Nch transistor 20 of the input circuit section 10 is completely ON regardless of which potential is applied. The flowing steady current is substantially equal to the source / drain current I SD flowing through the Pch transistor 19. That is, the following equation is obtained.
【００１３】 [0013]
【００１４】前記（１）式より、入力回路部の入力部１
６に５Ｖを加えた方が、入力回路部１０に流れる定常電
流は大幅に減少し、従来の回路に比べて消費電力が減少
する。From the above equation (1), the input unit 1 of the input circuit unit
When 5 V is applied to 6, the steady-state current flowing through the input circuit section 10 is greatly reduced, and the power consumption is reduced as compared with the conventional circuit.
【００１５】[0015]
【発明の効果】以上説明したように、本発明は、イネー
ブル端子と出力回路部の入力端子との信号により、入力
回路部を制御し、定常電流を低減することにより消費電
力が少なくできるという効果を有する。As described above, according to the present invention, the power consumption can be reduced by controlling the input circuit section by the signal of the enable terminal and the input terminal of the output circuit section and reducing the steady-state current. Having.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の第１の実施例の双方向バッファの回路
図である。FIG. 1 is a circuit diagram of a bidirectional buffer according to a first embodiment of the present invention.
【図２】本発明の第２の実施例の回路図である。FIG. 2 is a circuit diagram of a second embodiment of the present invention.
【図３】従来の双方向バッファの回路図である。FIG. 3 is a circuit diagram of a conventional bidirectional buffer.
１，１０，２１ 入力回路部 ２，１１，２２ 出力回路部 １４ ＮＡＮＤ回路 ８，２０ 入力回路部Ｎｃｈトランジスタ ７，１９ 入力回路部Ｐｃｈトランジスタ ３，１２，２３ 出力回路部入力端子 ４，１３，２４ イネーブル端子 ６，１５ Ｐｃｈトランジスタ １７ トランスミッションゲート ５ ＡＮＤ回路 １８ インバータ回路 ２５ 双方向端子 ９，１６，２６ 入力回路部の入力部 1, 10, 21 input circuit section 2, 11, 22 output circuit section 14 NAND circuit 8, 20 input circuit section Nch transistor 7, 19 input circuit section Pch transistor 3, 12, 23 output circuit section input terminal 4, 13, 24 Enable terminal 6,15 Pch transistor 17 Transmission gate 5 AND circuit 18 Inverter circuit 25 Bidirectional terminal 9,16,26 Input section of input circuit section
Claims (2)
向バッファにおいて、イネーブル端子と前記出力回路部
の入力端子との信号がＡＮＤ回路またはＮＡＮＤ回路の
機能を有する回路の入力端子に接続され、前記ＡＮＤ回
路またはＮＡＮＤ回路の機能を有する回路の出力端子が
トランジスタのゲート端子に接続され、前記トランジス
タのソース端子，ドレイン端子のうち一方が電源に他方
が前記入力回路部に接続されることを特徴とする双方向
バッファ。In a bidirectional buffer including an input circuit section and an output circuit section, a signal between an enable terminal and an input terminal of the output circuit section is connected to an input terminal of a circuit having a function of an AND circuit or a NAND circuit. An output terminal of a circuit having the function of the AND circuit or the NAND circuit is connected to a gate terminal of a transistor, one of a source terminal and a drain terminal of the transistor is connected to a power supply, and the other is connected to the input circuit portion. A bidirectional buffer.
スタ・ロジックの出力構成となっている請求項１記載の
双方向バッファ。2. The bidirectional buffer according to claim 1, wherein the input circuit section has a transistor-transistor logic output configuration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3193352A JP2654275B2 (en) | 1991-08-02 | 1991-08-02 | Bidirectional buffer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3193352A JP2654275B2 (en) | 1991-08-02 | 1991-08-02 | Bidirectional buffer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0537343A JPH0537343A (en) | 1993-02-12 |
| JP2654275B2 true JP2654275B2 (en) | 1997-09-17 |
Family
ID=16306479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3193352A Expired - Lifetime JP2654275B2 (en) | 1991-08-02 | 1991-08-02 | Bidirectional buffer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2654275B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5898232A (en) * | 1995-11-08 | 1999-04-27 | Advanced Micro Devices, Inc. | Input/output section of an integrated circuit having separate power down capability |
| US5860125A (en) * | 1995-11-08 | 1999-01-12 | Advanced Micro Devices, Inc. | Integrated circuit including a real time clock, configuration RAM, and memory controller in a core section which receives an asynchronous partial reset and an asynchronous master reset |
| US5561384A (en) * | 1995-11-08 | 1996-10-01 | Advanced Micro Devices, Inc. | Input/output driver circuit for isolating with minimal power consumption a peripheral component from a core section |
-
1991
- 1991-08-02 JP JP3193352A patent/JP2654275B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0537343A (en) | 1993-02-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19970422 |