JPH0537343A - Bidirectional buffer - Google Patents

Abstract

PURPOSE:To decrease the power consumption by controlling an input circuit by signals of an enable terminal, and an input terminal of an output circuit part, and reducing a steady state current. CONSTITUTION:In the case a bidirectional buffer outputs an H level (about 3V) in all output states an enable terminal 4 and an input terminal 3 both become the potential of am H level (5V). Therefore, an output of an AND circuit 5 becomes an H level, and a Pch transistor 6 becomes completely a turn-off state. Also, the potential of an input part 9 of an input circuit part 1 becomes an H level (about 3V), therefore, an Nch transistor 8 becomes completely a turn-on state, and a source-drain current flowing to a Pch transistor 7 becomes about zero since the Pch transistor 6 is completely in a turn-off state. Accordingly, a steady state current flowing to the input circuit 1 decreases, and the power consumption decreases.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to bidirectional buffers,
In particular, it relates to a transistor-transistor logic (TTL) output bidirectional buffer in a CMOS circuit.

[0002]

2. Description of the Related Art Conventionally, this type of bidirectional buffer has been shown in FIG.
As shown in, when the buffer is in the output state, input terminal 2
The output circuit unit 22 that outputs a signal from the inside (for example, in the semiconductor chip) to the bidirectional terminal 25 to the bidirectional terminal 25 and the signal from the outside applied to the bidirectional terminal 25 to the inside when the buffer is in the input state. And an input circuit section 21 for transmitting the signal, the input section 26 of the input circuit section has the same potential as that when the bidirectional buffer is in the output state.

[0003]

In this conventional TTL output bidirectional buffer, when the bidirectional buffer is in the output state and a high level (about 3 V) is output, the input section of the input circuit section 21 is output. Since 26 also has the same potential, there is a disadvantage that a steady leak current flows inside the input circuit section 21, which leads to an increase in power consumption.

An object of the present invention is to solve the above-mentioned drawbacks and to provide a bidirectional buffer in which the power consumption due to the leak current is not increased.

[0005]

According to the structure of a bidirectional buffer of the present invention, in a bidirectional buffer having an input circuit section and an output circuit section, signals of an enable terminal and an input terminal of the output circuit section are ANDed. Connected to an input terminal of a circuit having a function of a circuit or a NAND circuit, an output terminal of the circuit having a function of the AND circuit or a NAND circuit is connected to a gate terminal of a transistor, and one of a source terminal and a drain terminal of the transistor Is connected to a power source, and the other is connected to the input circuit section.

[0006]

1 is a circuit diagram showing a bidirectional buffer according to a first embodiment of the present invention. 1, in the bidirectional buffer of this embodiment, an enable terminal 4 and an input terminal 3 of an output circuit unit 2 are connected to an input terminal of an AND circuit 5, and the output terminal thereof is a gate of a P-channel (ch) transistor 6. The source terminal of the Pch transistor 6 is connected to the power supply (5V), and the drain terminal is connected to the input circuit unit 1.
Is connected to the source terminal of the Pch transistor 7.

When the bidirectional buffer outputs a high level (about 3 V) in the output state, both the enable terminal 4 and the input terminal 3 have a potential of High level (5 V), so that the output of the AND circuit 5 is high. At the level (5 V), the Pch transistor 6 is completely turned off. The potential of the input section 9 of the input circuit section 1 is also High.
Since it becomes the h level (about 3V), the input circuit section Nch transistor 8 is completely on (ON) and the input circuit section 1 P
Source-drain current I _SD flowing in the ch transistor 7
Is because the Pch transistor 6 is completely off,
It becomes almost zero.

Therefore, the steady current flowing through the input circuit section 1 is significantly reduced, and the power consumption is reduced as compared with the conventional circuit.

FIG. 2 is a circuit diagram showing a bidirectional buffer according to the second embodiment of the present invention.

In FIG. 2, in this embodiment, the AN of FIG. 1 is used.
The D circuit 5 replaces the NAND circuit 14, and its output terminal is a Pch whose source terminal is connected to the power supply (5 V) and whose drain terminal is connected to the input section 16 of the input circuit section 10.
The output terminal of the inverter circuit 18 is connected to the gate terminal of the transistor 15, and further to the gate terminal of the Nch transistor of the transmission gate 17 composed of a Pch transistor and an Nch transistor, and the input terminal of the inverter circuit 18. It is connected to the gate terminal of the 17 Pch transistor. Others are the same as in FIG.

Considering the same way when the bidirectional buffer is outputting a high level (about 3 V) in the output state,
The enable terminal 13 and the input terminal 12 become High level (5V), and the output of the NAND circuit 14 becomes Low level (0V). Therefore transmission gate 1
7, the Pch transistor 15 is turned on, and the Pch transistor 15 is turned on, so that the potential of the input section 16 of the input circuit section 10 becomes substantially equal to the power supply voltage (5 V).

Here, the input section 16 of the input circuit section 10 has 5
Considering the case where two kinds of potentials, V and 3V, are applied, the Nch transistor 20 of the input circuit unit 10 is completely in the ON state regardless of which potential is applied. The steady current that flows is substantially equal to the source / drain current I _SD that flows in the Pch transistor 19. That is, the following equation is obtained.

[0013]

From the equation (1), the input section 1 of the input circuit section
When 5V is applied to 6, the steady-state current flowing through the input circuit unit 10 is significantly reduced, and the power consumption is reduced as compared with the conventional circuit.

[0015]

As described above, according to the present invention, the power consumption can be reduced by controlling the input circuit section by the signal from the enable terminal and the input terminal of the output circuit section and reducing the steady current. Have.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a bidirectional buffer according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional bidirectional buffer.

[Explanation of symbols]

1,10,21 Input circuit section 2,11,22 Output circuit section 14 NAND circuit 8,20 Input circuit block Nch transistor 7, 19 Input circuit block Pch transistor 3,12,23 Output circuit block input terminal 4, 13, 24 Enable terminals 6,15 Pch transistor 17 Transmission gate 5 AND circuit 18 Inverter circuit 25 bidirectional terminals 9, 16, 26 Input section of the input circuit section

Claims (2)

[Claims] 1. In a bidirectional buffer having an input circuit section and an output circuit section, signals of an enable terminal and an input terminal of the output circuit section are connected to an input terminal of a circuit having a function of an AND circuit or a NAND circuit. The output terminal of the circuit having the function of the AND circuit or the NAND circuit is connected to the gate terminal of the transistor, one of the source terminal and the drain terminal of the transistor is connected to the power supply, and the other is connected to the input circuit section. Bidirectional buffer characterized by. 2. The bidirectional buffer according to claim 1, wherein the input circuit section has a transistor-transistor logic output configuration.