JPH0637623A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To share the bus of a 3V driving device and a 5V driving device equipped with a 3-state output buffer. CONSTITUTION:A transfer gate 8 is provided between an output terminal 11 of a 3 state outputting circuit, and pre-MOS transistors 4A and 5A. Thus, the gate width W of a P type MOS transistor 4B connected with the output terminal 11 is reduced, so that a P type diffusion layer area can be reduced, and forward currents in proportion to the joint area of a parasitic diode can be reduced. Thus, the bus of the 3V driving device and the 5V driving device can be shared.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a CMOS semiconductor integrated circuit.

[0002]

2. Description of the Related Art 3 consisting of conventional CMOS transistors
The state output circuit is shown in FIG.

In FIG. 2, the present 3-state output circuit is
A 3-state output circuit control circuit 12A including a NAND circuit 1, a NOR circuit 2, and an inverter circuit 3, and a P-type MOS
A transistor 4A, an N-type MOS transistor 5A,
It has a signal input terminal 10, an enable input terminal 9, and an output terminal 11. A power supply 6 and a ground (GND) are connected to the series body of the transistors 4A and 5A.

In the conventional CMOS 3-state output circuit, the enable input terminal 9 has a high level signal and the signal input terminal 1 has a high level signal.
When a high level signal is input to 0, the output of the NAND circuit 1 becomes low level, the P-type MOS transistor 4A is turned on, and the output of the NOR circuit 2 becomes low level,
The N-type MOS transistor 5A is turned off and the output terminal 11 is set to a high level output state.

A high level signal is applied to the enable input terminal 9,
When a low level signal is input to the signal input terminal 10, NA
The output of the ND circuit 1 goes high, the P-type MOS transistor 4A turns off, the output of the NOR circuit 2 goes high, the N-type MOS transistor 5A turns on, and the output terminal 11 goes low. become.

When a low level signal is input to the enable input terminal 9, the output of the NAND circuit 1 becomes high level regardless of whether the signal input to the signal input terminal 10 is a high level signal or a low level signal, and the P-type MOS transistor 4A is turned on. In the off state, the output of the NOR circuit 2 becomes low level, the N-type MOS transistor 5A is turned off,
The output terminal 11 is in a high impedance state.

As described above, depending on the signals input to the enable input terminal 9 and the signal input terminal 10, there are three states of a high level output state, a low level output state and a high impedance state.

[0008]

With the miniaturization of semiconductor manufacturing technology, the gate length L of a MOS transistor is 1 μm.
If it is less than m, the power supply voltage of the logic LSI tends to decrease due to the improvement of reliability and the reduction of power consumption, and the conventional logic LSI having a high operation power supply voltage and the conventional logic LSI having a low operation power supply voltage. And will be mounted on one board.

Therefore, as shown in FIG. 3, the CMOS 3 of the logic LSIs 13A and 13B having different operating power supply voltages is used.
It may happen that the state output is connected to one bus line 14. In FIG. 3, the logic LSI 13A has 5V
The operation logic LSI, the logic LSI 13B is a 3V operation logic LSI, the circuit 15A is a three-state output circuit in the logic LSI 13A, and the circuit 15B is a CMO in the logic LSI 13B.
It is an S3 state output circuit.

C of the logic LSI 13A operating at 5V power supply voltage
When the MOS 3-state output circuit 15A is in the output state (high level 5V or low level 0V), the CMOS 3-state output circuit 15B of the logic LSI 13B operating with the 3V power supply voltage is in the high impedance state, and the bus line 14 is in the output level of the logic LSI 13A. It becomes a state.

At this time, the CMOS 3 of the logic LSI 13A
When the state output circuit is in the high level output state (5V output) and the bus line 15 is in the high level (5V) state, even if the 3-state output circuit 15B of the logic LSI 13A is in the high impedance state, the CMOS 3-state output circuit 15
B is a 3V power supply voltage operation, so the P-type M at the final stage
A forward voltage is applied to the parasitic diode composed of the P-type diffusion layer of the OS transistor and its N-well, and a forward current flows from the P-type diffusion layer to the N-well, resulting in a large power consumption of the entire circuit. There was a problem that

An object of the present invention is to solve the above-mentioned problems and to provide a semiconductor integrated circuit device in which power consumption does not increase.

[0013]

The structure of the semiconductor integrated circuit device of the present invention is characterized in that a transfer gate is provided between the output terminal and the final stage output circuit.

[0014]

1 is a circuit diagram showing a semiconductor integrated circuit device according to a first embodiment of the present invention.

Referring to FIG. 1, the semiconductor integrated circuit device of this embodiment has a 3-state output circuit control circuit 12A and a P-type M circuit.
OS transistor 4A and N-type MOS transistor 5A
Series body, transfer gate 8, and output terminal 11
And a signal input terminal 10 and an enable input terminal 9.

Here, the transfer gate 8 includes a P-type MOS transistor 4B and an N-type MOS transistor 5B.
Have and. The gate of the transistor 4B is connected to the enable input terminal 9, and the gate of the transistor 5B is connected to the output of the inverter circuit 3. Transistor 4A,
The 5 A series body is connected to the power supply 6 and the ground 7. The 3-state output circuit control circuit 12A includes the NAND circuit 1 and
It has a NOR circuit 2 and an inverter circuit 3.

This embodiment is characterized in that the transfer gate 8 is provided in front of the output terminal 11.

This 3-state output circuit is a P-type MO that constitutes the transfer gate 8 in the signal output state.
The S transistor 4B and the N-type MOS transistor 5B are turned on, and the signals from the drains of the P-type MOS transistor 4A and the N-type MOS transistor 5A are output to the output terminal.

In the high impedance state, the P-type MOS transistor 4 forming the transfer gate 8 is formed.
The B and N type MOS transistors 5B are turned off, and P
Type MOS transistor 4A, N type MOS transistor 5
Cut off the drain of A from the output terminal.

Here, as shown in FIG. 3, considering a case where a bus is configured with a logic LSI 13A having a high operating power supply voltage,
The high-level output of the logic LSI 13A having a high operating power supply voltage raises the voltage of the output terminal 11, and the parasitic diode formed by the P-type diffusion layer connected to the terminal of the P-type MOS transistor 4B forming the transfer gate 8 and its N well. Although a forward voltage is applied to the gate to cause a forward current to flow, a P-type MOS forming the transfer gate 8 is formed.
By reducing the gate width W of the transistor 4B, P
Since the area of the type diffusion layer is reduced and the junction area of the diode is reduced, the forward current proportional to the junction area can be reduced. When the gate width W of the P-type MOS transistor 4A is 100 μm and the gate width W of the P-type MOS transistor 4B forming the transvager gate 8 is 10 μm, the output terminal 11 is farther from the output terminal 11 than in the case of the conventional 3-state output circuit. The viewed P-type diffusion layer area is 1/10, and the forward current proportional to the junction area of the parasitic diode is also 1/10.

N-type MO constituting a transfer gate
The S-transistor 5B and the P-type MOS transistor 4A in the preceding stage have a large gate width W so as not to impair the drive capability of the output signal in the output state.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

In FIG. 4, this embodiment is a three-state output circuit having a control circuit section different from that of the first embodiment.
That is, the control circuit 12B of this embodiment is different from that of FIG.
When a high level signal is input to the enable input terminal 9 and a high level signal is input to the signal input terminal 10, the P-type MOS transistors 4C, 4D and 4E are turned off, the N-type MOS transistors 5D and 5E are turned on, and the N-type MOS transistor 5C is turned off. As a result, the lines 16A and 16B become low level, the P-type MOS transistor 4A is turned on, and the N-type M transistor is turned on.
The OS transistor 5A is turned off, the transfer gate 8 is turned on, and the output terminal 11 is in a high level output state.

A high level signal is input to the enable input terminal 9,
When a low level signal is input to the signal input terminal 10, the P-type MOS transistors 4C and 4E are turned on, 4D is turned off and N
Type MOS transistors 5C and 5D and N type MOS transistor 5E are turned off, as a result, lines 16A and 16B are set to a high level, P type MOS transistor 4A is turned off, N type MOS transistor 5A is turned on, and transfer gate 8 Is turned on, and the output terminal 11 is in a low level output state.

A low level signal is applied to the enable input terminal 9,
When a high level signal is input to the signal input terminal 10, the P-type MOS transistors 4C and 4E are turned off, the P-type MOS transistor 4D is turned on, and the N-type MOS transistors 5C and 5 are turned on.
D is on, N-type MOS transistor 5E is off, as a result line 16A is at high level, line 16B is at low level, and P-type MOS transistor 4A is off.
The N-type MOS transistor 5A is turned on, the transfer gate 8 is turned off, and the output terminal 11 is in a high impedance state.

A low level signal is input to the enable input terminal 9,
When a low level signal is input to the signal input terminal 10, the P-type MOS transistors 4C and 4D are turned on, the P-type MOS transistor 4E is turned off, the N-type MOS transistor 5C is turned on, and the N-type MOS transistors 5D and 5E are turned off. 16A goes high and line 16B goes low, turning off the P-type MOS transistor 4A,
The N-type MOS transistor 5A is turned on, the transfer gate 8 is turned off, and the output terminal 11 is in a high impedance state.

Also in the circuit of this embodiment, the transfer gate is turned off in the high impedance state, and the same effect as that of the first embodiment can be obtained.

[0028]

As described above, the CM of the present invention is particularly effective.
The OS3 state output circuit can reduce the gate width W of the transfer gate P-type MOS transistor to reduce the P-type diffusion layer area and the forward current proportional to the junction area of the parasitic diode. There is an effect that the bus can be shared between the 5V drive device and the 3V drive device.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional 3-state output circuit.

FIG. 3 is a block diagram showing an example in which three-state circuits of logic LSIs having different power supply voltage operations are connected to one bus line.

FIG. 4 is a circuit diagram of a second embodiment of the present invention.

[Description of Reference Signs] 1 NAND circuit 2 NOR circuit 3 Inverter circuit 4A, 4B, 4C, 4D, 4E P-type MOS transistor 5A, 5B, 5C, 5D, 5E N-type MOS transistor 6 Power supply 7 Ground 8 Transfer gate 9 Enable input Terminal 10 Signal input terminal 11 Output terminal 12A, 12B 3 state output circuit control circuit section 13A Logic LSI with 5V operating power supply voltage 13B Logic LSI with 3V operating power supply voltage 14 Bus line 15A, 15B 3 state output circuit of logic LSI 16A , 16B signal line

Claims (2)

[Claims] 1. A semiconductor integrated circuit device comprising a 3-state output buffer provided with a transfer gate between an output terminal and a final stage output circuit. 2. The semiconductor integrated circuit device according to claim 1, wherein the gates of the transfer gates are respectively connected to the enable input terminal and its input inverting output.