JP3031090B2 - Output port circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit for outputting a plurality of power supply potentials from one port, and more particularly, to selecting two or more different power supply potentials except a ground (GND) potential and an intermediate potential (Z). And an output port circuit for outputting from one output port.

[0002]

2. Description of the Related Art Conventionally, when there are two internal power supply voltages having different potentials in a semiconductor integrated circuit, an output port circuit which selects one of the two internal power supply voltages and outputs the selected one from one output port Is being considered. For example, FIG.
Is an example, and the output port is a P-type FET 51 and N
A buffer 50 composed of an FET 52 is connected, and is configured to output a power supply voltage to the output port P based on the data 40. A first power supply voltage VDD1 and a second power supply voltage VDD2 are connected to the buffer 50 via P-type FETs 13 and 23, respectively. The output of the potential determination circuit 30 is directly input to the gate of the P-type FET 13;
When the output of the potential determination circuit 30 is input to the gate of the FET 23 via the inverter 60, the P-type FETs 13 and 23 are selectively turned on by the output of the potential determination circuit 30. . In this circuit, a P-type FET is used in accordance with the output level of the potential determination circuit 30.
Since the switches 13 and 23 are selectively turned on, the power supply voltage VDD1 or VDD2 on the turned-on side is selected and output from the output port P.

[0003]

In such an output port circuit, for example, when an attempt is made to output the first power supply voltage VDD1, the P-type FET 13 is turned on and the buffer 5 is turned on.
The power supply voltage VDD1 should be output from the output port P in order to make the power supply voltage of VDD0 VDD1. At this time, the potential difference between the first and second power supply voltages VDD1 and VDD2 is applied to the P-type FET 23 in the OFF state. (VDD1> VDD
2) is applied as a reverse voltage and a reverse current to the substrate of the P-type FET 23, a current flows into the P-type FET 23, and the P-type FET 23 is destroyed or a reverse current is output from the output port. And the power supply voltage may fluctuate. SUMMARY OF THE INVENTION It is an object of the present invention to provide an output port circuit that prevents the destruction of the FET and prevents the output voltage from fluctuating.

[0004]

According to the present invention, there are provided two voltage sources having different potentials, a buffer for outputting one of the two voltage sources from an output port based on data;
Switch means interposed between each of the two voltage sources and the buffer, and an output port circuit including a potential determination circuit that outputs a signal for selectively opening and closing the switch means, wherein each of the switch means, A configuration in which first and second transistors of the same conductivity type are connected in cascade, wherein one of the two voltage sources, one electrode of the first transistor, and a substrate are connected;
Wherein the other electrode of the first transistor and the first electrode of the second transistor is connected, the other electrode and the sub straight the said buffer second transistor is to configurations connected.

[0005]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of one embodiment of the present invention, and the same parts as those of the circuit shown in FIG. That is,
A buffer 50 composed of a P-type FET 51 and an N-type FET 52 is connected to the output port P, and is configured to output a power supply voltage to the output port P based on the data 40. In this buffer 50, a first power supply voltage VDD1 and a second power supply voltage VDD2 are respectively supplied to switch means 10, 2
0 is connected. The first switch means 10, the difference
The substrate and the source were set to a common potential (hereinafter, sub-
(It is also referred to as having a straight on the source side.) P-type FET1
1, and the substrate and the drain were set to a common potential.
(Hereinafter, it is also referred to as having the substrate on the drain side.
The P-type FETs 12 are connected in cascade, and the gates of the respective FETs are connected to each other so that the output of the potential determination circuit 30 is input. The second switch means 20 is similarly configured by P-type FETs 21 and 22, but is configured such that the output of the potential determination circuit 30 is input to each gate via the inverter 60.

According to this configuration, for example, the power supply voltage VD
When D1 and VDD2 are set to VDD1 = 10V and VDD2 = 5V, an attempt is first made to output VDD1 = 10V from the output port P. At this time, a low-level signal is output from the potential determination circuit 30, and the P-type F
The first switch means 10 including ET11 and ET12 is turned on
Then, the power supply voltage VDD1 passes through the switch means 10 and is output from the output port P through the buffer 50. At this time, a high level obtained by inverting the low level output from the output power supply potential determination circuit 30 by the inverter 60 is input to the P-type FETs 21 and 22.
The second switch means 20 consisting of 1 and 22 is turned off.

For this reason, the second switch means 20 has V
A potential difference between DD1 and VDD2 will be applied,
The second switch means 20 includes a drain and a substrate.
And the source of the P-type FET 22 having a common potential
Of the P-type FET 21 having a common potential with the substrate and the substrate
Since the drains are cascaded, these P-type FETs
Of the current between the substrates 22 and P-type FET 21
Flow is suppressed, and especially reverse voltage and reverse current
Reverse voltage due to the difference potential of the P-type FET21 respect VDD1 and VDD2 is prevented from being applied to the substrate, to prevent reverse current in the P-type FET21 that. As a result, VDD1 = 10 V from the output port P
Is output stably.

Conversely, when the power supply voltages VDD1 and VDD2 are set to VDD1 = 5V and VDD2 = 10V and VDD1 = 5V is to be output from the output port, the output of the potential determination circuit 30 is reversed. To be configured. As a result, a low level is output from the potential determination circuit 30, the first switch means 10 including the P-type FETs 11 and 12 is turned on, and the power supply voltage VDD1 passes through the first switch means 10, and the power supply voltage of the buffer 50 is And output from the output port P.

At this time, since the low level output from the potential determination circuit 30 is input to the P-type FETs 21 and 22 as a high level from the inverter 60, the switch means 20 is turned off. In the switching means 20, the drain of the P-type FET 21 having the source and the substrate at a common potential, and the drain and the substrate
The source of the P-type FET 22 with the common potential
The P-type FET 21 and the P-type FET
The current flow between both substrates is suppressed.
In particular, the drain and the substrate are common
It is possible to prevent the leakage current to the P-type FET 22 which is set as the potential, and to stably output the power supply potential of VDD1 = 5V from the output port.

[0010]

As described above, according to the present invention, the switch means is a cascade connection of a transistor having a substrate on the source side and a transistor having a substrate on the drain side. Even when a voltage is applied to the means, it is possible to prevent the transistor from being in a reverse bias state with respect to the substrate,
This has the effect of preventing the transistor from being destroyed and preventing the output voltage from fluctuating due to the leakage current, so that a stable voltage can be output.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of an output port circuit of the present invention.

FIG. 2 is a circuit diagram of an example of an output port circuit currently under study.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 1st switch means 11 P-type FET which has a substrate on the source side 12 P-type FET which has a substrate on the drain side 20 2nd switch means 21 P-type FET which has a substrate on the source side 22 Sub-type on the drain side Straight P-type FET 30 Potential determination circuit 40 Data 50 Buffer 60 Inverter

Claims (1)

(57) [Claims] An output port for outputting one of the two voltage sources based on data; and a buffer interposed between the two voltage sources. And a potential determination circuit that outputs a signal for selectively opening and closing each of the switch units, wherein each of the switch units includes first and second transistors of the same conductivity type. A cascade-connected configuration, wherein one of the two voltage sources is connected to one electrode and the substrate of the first transistor, and the other electrode of the first transistor is connected to the one electrode of the second transistor. and electrodes are connected, the output port of times with the other electrode of the said buffer second transistor and <br/> sub straights, characterized in that the connection configurations .