JPS62159911A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To quicken the transition of a data output and to reduce noise at output data change by providing a bias impressing means controlled by an internal signal to a data output terminal of an output buffer and operating the bias impressing means only during a prescribed period just before the output. CONSTITUTION:A bias impressing means bringing the level of a data output terminal 3 to an intermediate voltage in response to a preceding output data by using N-channel MOSFETs 18-20 and P-channel MOSFETs 21-23, is constituted. The operation of the bias impressing means is controlled by a control signal 24. The bias impressing means is provided to the data output terminal in this way and the output terminal is brought into the intermediate potential by charging or discharging the output terminal before the data is outputted. Thus, the noise due to a counter electromotive force at the change of the output data is small and the response speed is quickened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a data output cover sofa thereof.

[Conventional technology]

Figure 3 is a circuit diagram of a well-known conventional data output bumper. inverter, 5, 6. 9. 10.
13 is P channel MO3FET, 7, 8, 11, 12
．． 14 is an n-channel MO3FET. The transistors 5, 6° 7.8 constitute a NAND circuit which inputs the internal data 1 and the OR signal 2, and the transistors 9, 10, 11, and 12 form the internal data 1.
A NOR circuit is configured, which receives as inputs the inverted signal of OE which is the output of the inverter 4. The output transistor 13 has a source connected to the power supply potential, a drain connected to the data output terminal 3, and a gate 15 connected to the output of the NAND circuit, and the output transistor 14 has its source connected to the reference potential, and its drain connected to the output terminal 3. A gate 16 is connected to the NOR circuit output. Here, the output transistors 13 and 14 are designed to have a large gate width because they must drive a large capacitive load of about 100 FF that is added to the data output terminal from outside the semiconductor integrated circuit.

Next, the operation will be explained.

When OR signal 2 is “L”, N
The output of the AND circuit becomes II Hml regardless of the internal data, and the output of the NOR circuit inputting the inverted signal of OE becomes "L" regardless of the internal data.

Therefore, the gate 15.1 of the output transistor 13.14
6 are respectively at "H" and 'L', and the output transistors 13 and 14 are both non-conductive and do not output internal data.

On the other hand, when OE signal 2 is “H”, the NAND circuit and NOR
Both circuits output inverted data of internal data l.

Therefore, if internal data 1 is "H", then game) 15.1
6 becomes 6L'' and is out.

Only the transistor 13 becomes conductive, and the data output terminal 3
Outputs “H” to If the internal data 1 is “L”, the gate 15.16 becomes 1H” and the output transistor 14
only becomes conductive and outputs “L” to the data output terminal 3.

The timing chart of the operation of such an output sofa circuit is shown in FIG. 4. Before and after 0 time t1, the OR signal 2 is "
This shows the case where the data transitions from "H" to "L" in the state of "H", and the case where the data changes from "L" to "H" after the OR signal is once set to "L" is shown before and after time t2. In both cases, as shown in FIG. Since the state changes from a non-conductive state to a conductive state, the amount of change in the drain current at tl and t2 is large.

Assuming that the inductance of the power supply wiring and reference potential wiring within the integrated circuit chip, the package, and the wire connecting the integrated circuit chip and the package is L2°Ll, the 1' rain current i2. tl
are the power supply current and base dt, respectively.

Therefore, a back electromotive force is generated at the reference potential at time t1 and at the power supply at time t2, resulting in noise.

・Also, at time t1, gate 15.1 is activated, albeit for a short period of time.
6 becomes an intermediate potential, output transistors 13 and 14 are both conductive, and a through current flows from the power supply potential to the reference potential. This is a wasteful current that does not contribute to charging and discharging the data output terminal. However, at time t2, the through current is avoided by the OR signal.

[Problem that the invention seeks to solve]

Since the conventional output bumper is configured as described above, there is a problem in that noise is generated in the reference potential and the power supply when the output data changes. Therefore, if the gate width of the output transistor is designed to be small, the above noise can be reduced.
There is a benefit and disadvantage in that reducing the gate width slows down the data output. Furthermore, since the data output terminal holds the value of the previous data until just before outputting new data, there is also the drawback that it takes time for the data output to transition.

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, it is an object of the present invention to provide a semiconductor integrated circuit that can reduce noise caused by back electromotive force and can perform data output transitions at high speed.

[Means for solving problems]

In the semiconductor integrated circuit according to the present invention, a bias application means controlled by an internal signal is provided at the data output terminal of the output cover/sofa, and the bias application means is operated only during a certain period immediately before data output. be.

[Effect]

In this invention, since the data output terminal is set to an intermediate voltage in advance according to the previous output data by the bias application means, the time required for output data transition is shortened, and when the output data changes [Example] An embodiment of the present invention will be described with reference to the drawings.

In Fig. 1, 18, 19, and 20 are n-channel MO3Fs connected in series between the power supply and the data output terminal 3.
ET (hereinafter referred to as n-) transistor), and n-)
The gates and drains of transistors 19 and 20 are each short-circuited. 21.22゜23 is a p-channel MO3 connected in series between the reference potential and the data output terminal 3.
FET (hereinafter referred to as p-transistor), and p-
The drain and gate of each transistor 21 and 22 are short-circuited. The transistors 18, 19, 20, 21 and 22, 23 constitute a bias applying means that brings the data output terminal 3 to an intermediate voltage according to the previous output data. A control signal 24 controls the operation of the bias applying means, and is connected to the gate of the n-transistor 18 and the inverter 17, and the output 25 of the inverter 17 is connected to the gate of the p-transistor 23. Therefore, when the control signal 24 is H', the bias applying means operates.

There are various methods for generating the control signal 24 depending on the type of semiconductor integrated circuit. For example, in static RAM, ATD (8 ddr
In a dynamic RAM, the τAS input signal can be generated by adding a delay time.

Here, the operation of the bias applying means will be explained. The threshold voltages of n-transistors 18, 19, and 20 are Vthn1, Vthn2, and V, respectively.
thn3. pl'' transistors 21, 22.23 threshold voltages are Vthp1 and Vthp2, respectively.
, Vthp 3, the data output is (Vcc
(Power supply potential 1-Vthn i-Vthn 2-Vth
n 3 ), the data output is (Vcc-
Vthn 1-Vthn 2-Vthn 3). Also, the data output is (lVthpzl+1vt
hp21+1Vtbp3 l), the data output is (lVthp 11+1Vthp 2 l+1vt
discharged to hp3 l). However, here, it is assumed that the control signal 24 is at Vcc and the output 25 of the inverter 17 is at OV (reference potential).

Next, the effects will be explained. FIG. 2 shows a timing chart of the operation of the output buffer circuit according to this embodiment.

First, sH++ is output as previous data.

When the OE signal 2 becomes 'L', the output transistor 13 becomes non-conductive, and then the control signal 24 becomes H' and the bias application means operates.At this time, the data output 3 is 'H', so the data output is (lVthp 11+1V
tl+p 21+1vthp 3 l).

Next, when new internal data 1 appears, OE signal 2 becomes “
H', the control signal 24 becomes L''.

Due to the gate 16 becoming H'' according to internal data 1,
The output transistor 14 becomes conductive, and Vcc and (
lVthp 1 l+1vthp 2 +1vth
Data output 3, which was at a level between p 3 1), is “L”
”. This time is time t1. MO
Since the drain current of the SFET has a positive relationship with the drain voltage, the drain voltage of the output transistor 14 changes over time t.
Since Vc and c have decreased by a certain voltage at the time of 1, the drain current 11 decreases. The more the counter electromotive force is applied, the more the applied back electromotive force is alleviated. In addition, since the potential at which transition begins is lowered, the time required for data transition is reduced accordingly (Δ1 in the figure).

Although FIG. 2 also shows the case where the data subsequently changes from "L" to 'H', the operation is the same as when the data changes from 'H' to 'L'.

In this case, data output 3 changes from the reference potential to Vcc-(Vthn 1
+ Vthn 2 + Vthn 3 ). Therefore, the voltage between the source and drain of the output transistor 13 is reduced, and the back electromotive force applied to the drain current 12 is alleviated.

In the above example, the level of data output 3 is defined using three n-channel MO8FETs and three I11-channel MO3FETs, but this level can be freely set by controlling the number of transistors connected in series and vth. Therefore, if the logical threshold value of the output is Vp, if it is set, even when the output data does not change, that is, when there is a transition from "H" to "H" or from 'L' to "L", there will be no change. There is no need to output normal data after outputting data.

The present invention is particularly effective in semiconductor integrated circuits having a large number of output terminals, such as multi-bit semiconductor memories.

Here, in the above embodiment, the data output 3 is provided with two types of bias applying means, an n-) transistor and a p-) transistor. However, in the case of an MO3 integrated circuit whose input/output levels are TTL compatible, the output logic threshold is closer to the reference voltage than the midpoint between the reference voltage and the electric voltage, so the data output changes from "H" to "L". It is necessary to increase the discharge current of the data output terminal when the data output changes from "L" to "H", and the noise in this case is larger than when the data output changes from "L" to "H". Therefore, as a bias application means,
It is also effective to configure the structure using only p-) transistors connected in series.

Further, in the above embodiment, a MOSFET is used for each transistor, but a similar circuit can be constructed using a MESFET or a bipolar transistor.

(Effects of the Invention) As described above, according to the present invention, the data output terminal is provided with a bias applying means, and the terminal is charged or discharged to an intermediate potential before data is output. , low noise and high response speed can be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an output buffer of a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a timing chart diagram for explaining the operation of the output buffer according to an embodiment of the present invention, and FIG. The figure is a circuit diagram showing a conventional output cover sofa for a semiconductor integrated circuit, and FIG. 4 is a timing chart diagram for explaining the operation of the conventional output cover sofa. 1...Internal data, 3...Data output terminal, 13°14...Output transistor, 1B, 19.20...
h-channel MO3FET (bias switch means and load means), 21.22.23...p-channel MO
3FET (bias switch means and load means),
24...Control signal. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (4)

[Claims] (1) Switch means for data output provided between the power supply terminal, the reference terminal and the data output terminal, and conduction or non-conduction of the above two switch means for data output are controlled by internal data. In a semiconductor integrated circuit that outputs data according to internal data, the bias switch means and the load means are connected in series, and between the power supply terminal and the data output terminal and between the reference potential terminal and the data output terminal. The present invention is characterized by comprising bias applying means connected to at least one side and operating only during a certain period immediately before data is output to charge or discharge the data output terminal to a predetermined level according to the previous output data. semiconductor integrated circuits. (2) The semiconductor integrated circuit according to claim 1, wherein the bias switch means and the load means are electric field transistors or bipolar transistors monolithically formed on the surface of the semiconductor substrate. (3) Claims characterized in that the load means is a field effect transistor whose drain and gate are short-circuited, or a field-effect transistor whose drain and gate are short-circuited connected in series. The semiconductor integrated circuit according to item 2. (4) Claim 2, characterized in that the load means is a bipolar transistor whose collector and base are short-circuited, or bipolar transistors whose collector and base are short-circuited are connected in series. The semiconductor integrated circuit described.