JP2908348B2 - Output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit,
In particular, it relates to an output circuit that handles digital signals.

[0002]

2. Description of the Related Art Semiconductor integrated circuits (hereinafter referred to as ICs)
Usually performs internal processing by inputting a signal or data from the outside, and outputs a signal of the processing result to an external through an output circuit.

The supply terminal and the reference terminal of the IC are supplied with a supply voltage and a reference voltage from an external supply terminal and an external reference terminal of the IC package, respectively. These two voltages are supplied to the IC via inductances existing in wiring on the IC package, bonding in the IC package, and the like. A load capacitance as an external load is connected between the output terminal of the IC and the reference terminal.

The capacitance as an external load is about 10 to 100 pF when mounted on a substrate board. In order to drive this at high speed, an output circuit having a large driving capability must be used. No.

However, when an output circuit having such a large driving capability is used, the occurrence of noise due to overshoot and undershoot when the IC is actually used becomes a problem. That is, due to the fast transition of the output circuit in the IC,
This is because back electromotive force is generated at the supply terminal and the reference terminal.

For example, consider the case where the output signal changes from Hi to Lo. The electric charge stored in the external load capacitance (hereinafter referred to as C1) in advance is discharged to the reference terminal when the transistor is turned on. As a result, the output signal changes from Hi to Lo. At this time, the current ISS flowing to the reference terminal also changes.

[0007] The rate of change of the current ISS over time dIS
Based on S / dt and the inductance component L1 between the external reference terminal and the reference terminal, L1 × (dISS /
dt) is generated. That is, in the IC, the reference voltage rises immediately after the transistor is turned on, and then becomes negative as the ON current decreases. When the ON current stops flowing, the reference voltage returns to the original reference voltage and stabilizes. .

As the rise time Tr and fall time Tf of the signal waveform are reduced and the speed is increased, the back electromotive force increases, and overshoot and undershoot noises are more likely to occur.

As described above, in order to operate the output circuit at a high speed, the rise time Tr and the fall time Tf must be as small as possible. Has achieved this.

However, when the driving force of the output circuit is increased,
Noise due to overshoot and undershoot is generated and causes a malfunction. Therefore, in order to reduce the noise generated by the output circuit, it is necessary to reduce the capability of the transistor for driving the output circuit and to slow the rise time and the fall time (Tr, Tf) of the output signal.

However, if the rise time and the fall time (Tr, Tf) are reduced, there is a problem that the overall speed is reduced and a high-speed operation cannot be realized. A conventional high-speed output circuit in which such noise is reduced is disclosed in, for example, JP-A-3-195120.

FIG. 4 is a circuit diagram of an output circuit showing an example of the prior art.

Referring to FIG. 4, the output circuit includes an input terminal H01, an input terminal H02, a power supply voltage supply terminal VDD, and a P-channel insulated gate field effect transistor (hereinafter referred to as a PMOS transistor) P1.
N-channel insulated gate field effect transistor (hereinafter referred to as NMOS transistor) N1 and PMOS
The transistor P4, the NMOS transistor N4, and P
MOS transistor P2 and PMOS transistor P3
, An NMOS transistor N2, an NMOS transistor N3, an inverter INV1, and an inverter INV2.
And an output terminal N01.

The input terminal H01 is connected to the gates of the PMOS transistors P1 and P3 and the input of the inverter INV1. The output of INV1 is connected to the gate of PMOS transistor P2. The input terminal H02 is connected to the NMOS transistors N1 and N1.
The gate of the MOS transistor N2 and the inverter IN
It is connected to the input of V2. The output of INV2 is NM
It is connected to the gate of the OS transistor N3.

A connection point A between the PMOS transistors P2 and P3 is connected to a PMOS transistor P4.
NMOS transistors N2 and NM
The connection point B of the OS transistor N3 is connected to the gate of the NMOS transistor N4.

The output terminal N01 is connected to a connection point between the PMOS transistor P1 and the NMOS transistor N1 and the PMOS transistor P1 and the NMOS transistor N1.
The starting point of the transistor P4, the NMOS transistor N4 and the NMOS transistor N2, the PMOS transistor P3
Connected to the connection point.

Next, the operation of the conventional output circuit will be described. The conventional example shown in FIG. 4 is a 3-State type. Input terminal H01 is Hi level, input terminal H02 is L
By setting it to the o level, the output terminal N01 can be brought into a high impedance state. First, this high impedance state will be described.

When the signal at the input terminal H01 is Hi, PM
OS transistor P1 and PMOS transistor P3 are O
Since Hi is input to the FF and the inverter INV1, the output becomes Lo. Thereby, the PMOS transistor P2
Turns on, so that the PMOS transistor P4 turns off. Therefore, the output terminal N01 does not go high because there is no transistor that propagates the high level at the output terminal N01.

Next, when the signal at the input terminal H02 is Lo, the NMOS transistor N1 and the NMOS transistor N2 are turned off, and Lo is input to the inverter INV2, so that the output becomes Hi. As a result, the NMOS transistor N3 is turned on, so that the NMOS transistor N4 becomes O
FF. Therefore, the output terminal N01 does not go low because there is no transistor that propagates the Lo level at the output terminal N01. Therefore, the output terminal N01 does not become Hi or Lo, and becomes in a high impedance state.

Next, a case where the input signal changes from Lo to Hi will be described. Input terminal H01, input terminal H0
When 2 is Lo, the PMOS transistor P1, the NMOS transistor N3, and the PMOS transistor P3 are turned on,
Since all other transistors are turned off, the output N01
Becomes Hi. At this time, since the output terminal N01 is Hi, the PMOS transistor P4 propagates Hi through the PMOS transistor P3, so that the PMOS transistor P4 is turned off.

Next, when the input terminals H01 and H02 are changed from Lo to Hi, the PMOS transistors P1 and N
MOS transistor N3, PMOS transistor P3
The PMOS transistor P4 turns off, the NMOS transistor N1, the PMOS transistor P2, the NMOS transistor N2, and the NMOS transistor N4 turn on,
The output terminal N01 changes from Hi to Lo.

The initial voltage at the contact B (gate voltage of the NMOS transistor N4) becomes a voltage dropped by the threshold value (hereinafter referred to as Vt) of the output terminal N01 via the NMOS transistor N2, so that the initial driving of the NMOS transistor N4 is performed. Power drops. As a result, the initial response is poor.

When the output terminal N01 exceeds the threshold level and approaches Lo, the NMOS transistor N2
Is lower than Vgs, the NMOS transistor N4 is completely turned off. Therefore, when the signal converges to Lo, the NMOS transistor N4 turns off, and the current is drawn only by the NMOS transistor N1.

Next, a case where the input signal changes from Hi to Lo will be described.

When the input terminals H01 and H02 are Hi, each of the NMOS transistor N1, the PMOS transistor P2 and the NMOS transistor N2 is turned on.
Output terminal N because all other transistors are turned off
01 becomes Lo. At this time, since the output terminal N01 is Lo, the NMOS transistor N4 propagates Lo through the NMOS transistor N2, so that the NMOS transistor N4 is turned off.

Next, the input terminals H01 and H02 are set to H level.
When i → Lo is changed, the NMOS transistors N1 and PM
The OSP2, the NMOS transistor N2, and the NMOS transistor N4 are turned off, the PMOS transistor P1, the PMOS transistor P3, the NMOS transistor N3, and the PMOS transistor P4 are turned on, and the output terminal N01 changes from Lo to Hi. Contact A
Initial voltage (gate voltage of PMOS transistor P4)
Is an output terminal N01 through a PMOS transistor P3.
, The initial drive capability of the PMOS transistor P4 decreases. As a result, the initial response is poor.

Next, when the output terminal N01 exceeds the threshold level and approaches Hi, the Vds of the PMOS transistor P3 becomes lower than | Vgs |, so that the PMOS transistor P4 is completely turned off. Therefore, the signal is H
PMOS transistor P4 is turned off at the time of convergence to i
As a result, the current is driven only by the PMOS transistor P1.

[0028]

The output circuit of the prior art is one of circuit types in which overshoot and undershoot are prevented. However, in the case of high-speed operation, the effect of reducing overshoot and undershoot is reduced. First
This is the problem.

FIGS. 4 and 5 (a) and 5 (b)
This will be described with reference to FIG.

In the conventional output circuit, when the signal at the output terminal N01 changes from Hi to Lo, the output terminal N01
At the point when the threshold voltage exceeds the threshold level and approaches the Lo level, the NMOS transistor N2 is turned ON because the gate is at the Hi level. However, since the signal at the output terminal N01 actually drops to Lo level,
The drain-source voltage Vd of the NMOS transistor N2
s becomes lower than the gate-source voltage Vgs, and NMO
The S transistor N2 is turned off. Since the potential at the contact B drops together with the output terminal N01 and the NMOS transistor N4 is completely turned off before the output signal becomes Lo, the signal at the output terminal N01 is converged to Lo only by the NMOS transistor N1. This NMOS transistor N
By reducing the performance of the first method, slow landing is performed to prevent undershoot as shown in FIG.

To increase the speed of the conventional circuit, FIG.
It is necessary to increase the capacity of the NMOS transistor N1 and the NMOS transistor N4 shown in FIG. As described above, the output terminal N01 of the NMOS transistor N4 is Lo.
Since the power is completely turned off before the time becomes, even if the capacity is increased, it does not contribute to speeding up.

Next, when the capacity of the NMOS transistor N1 is increased, its input is directly connected to the input terminal H01, so that an undershoot occurs in proportion to the capacity as shown in FIG. The intended Low noise characteristic cannot be obtained. That is, since the slow landing is performed at the expense of the operation speed, it is not suitable for high-speed operation. The same applies to the mechanism of occurrence of overshoot.

The second problem is that the initial response of the output signal is poor.

Hereinafter, description will be made with reference to FIGS. 4 and 5 (a). In order for the output signal to change from Hi to Lo, the NMOS transistors N1 and N4 shown in FIG. 4 must be turned on. However, the NMOS transistor N2 for driving the NMOS transistor N4 is N
Since it is a MOS transistor, the voltage at the contact B is NMO
The voltage falls by the threshold value Vt of the S transistor N2, and the time for the NMOS transistor N4 to change from OFF to ON is delayed. As a result, the initial response deteriorates as shown in FIG. The same applies when the output signal changes from Lo to Hi.

The third problem is that the area of the conventional output circuit becomes larger than that of the ordinary output circuit by the addition of a control circuit for reducing noise.

The area of the transistor is (gate length L) ×
(Gate width W). When the gate length L is fixed, the area ratio can be determined by the value of the gate width W.

For example, in a 0.5 μm process semiconductor device, when the gate length L is uniformly set to 0.5 μm for high-speed driving, the gate width W of each of the PMOS transistor and the NMOS transistor needs to be about 600 μm. Here, for easy comparison with the conventional example, W of the PMOS transistor and the NMOS transistor of the normal output circuit is divided into 、, and each is connected in parallel to make a total of 4
When each transistor is composed of two transistors, the W of one PMOS transistor and one NMOS transistor is 300 μm each.
m, and the sum of W is 300 × 4 = 1200 (μ
m). By the way, when an output circuit having the same capacity as that described above is to be constituted by the conventional circuit shown in FIG. 4, as described in the second problem, the gate voltages of the PMOS transistor P4 and the NMOS transistor N4 are equal to the threshold voltage Vt.
Since the divided voltages are reduced, the driving capability of the PMOS transistor P4 and the NMOS transistor N4 is reduced. Generally, the magnitude of the driving capability of a transistor can be represented by a driving current (hereinafter, referred to as Ids), and is obtained by the following equation.

Ids = W / L × Cox × μ × (Vgs−Vt) Vds Cox is gate capacitance (hereinafter referred to as Cox), μ is mobility (hereinafter referred to as μ), and Vgs is gate-source voltage (hereinafter Vgs). ), And Vds is a drain-source voltage (hereinafter, referred to as Vds).

Here, when the output signal changes from Hi to Lo, the NMOS transistors N4 and NMO shown in FIG.
The driving capability of the S transistor N1 is compared. In order to simplify the calculation, the gate capacitance Cox, mobility μ, and gate length L determined by the manufacturing process of the semiconductor integrated circuit are replaced by Cox × μ / L = α as constants, and the gate width W is simply calculated.
It is calculated only by the size and the voltage. For example, a power supply voltage of 3.3 V, Vt = 0.7 V, and W = 30 in the conventional circuit shown in FIG.
When the condition of 0 μm is given, the NMOS transistor N2 that drives the NMOS transistor N4 is an NMOS transistor.
Becomes lower than the threshold voltage Vt of the conventional circuit.
The gate-source voltage Vgs of the S transistor N4 is Vg
s = 3.3V-0.7V = 2.6V.

The following value is obtained by calculating the drive current Ids of the conventional NMOS transistor N4.

Ids = 300 × (2.6-0.7) ×
3.3 × α = 1881α (A) Similarly, when the same condition as above is applied to the NMOS transistor N1, the gate voltage does not drop by the threshold value Vt, so that the gate-source voltage Vgs of the NMOS transistor N1 becomes Vgs = 3. 0.3V.

The drive current Ids of the NMOS transistor N1 is calculated as follows.

Ids = 300 × 3.3-0.7) × 3.
3 × α = 2574α (A) From the above calculation, the NMOS transistor N4 has the NMO
Only about 73% of the driving current can be obtained for the S transistor N1.

Conversely, the NMOS transistor N4 has the NMO
In order to obtain the same drive current as the S transistor N1, W =
410 μm is required.

Further, a normal IC has a pre-buffer circuit for driving an output circuit. Generally, the gate width W of the pre-buffer circuit needs to be 15% of that of the output circuit. Therefore, the PMOS transistors P2 and NM
OS transistor N2, PMOS transistor P3, N
In order for MOS transistor N3 to obtain a driving force equivalent to that of the pre-buffer circuit, a gate width of 61.5 μm is required for each. Similarly, the PMOS transistors P2 and P2
Inverter INV driving NMOS transistor N3
1. The gate width of the inverter INV2 is 9.2 μm.

As a result, the conventional gate width W shown in FIG.
Is the sum of P1 + N1 + (P2 + N2 + P3 + N3 + IN
V1 + INV2) + P4 + N4 = 300 × 2 + (61.
5 × 4 + 9.2 × 4) + 410 × 2 = 1703 (μm)
Becomes

Thus, the total of the gate width W of the ordinary output circuit obtained above is 1200 μm, whereas the total of the conventional example is 1 μm.
703 μm, requiring an area of 1.42 times.

The conventional example shown in FIG.
When the 3-State function is not used, the same signal is input to the input terminal H01 and the input terminal H02.
Becomes sharable. Here, if the inverter INV2 is omitted, the total of the gate width W becomes 1685 μm, but the area is still required to be 1.40 times as compared with the normal output circuit.

[0049]

An output circuit according to the present invention comprises an input terminal, an output terminal, a supply terminal for supplying a power supply voltage, a reference terminal for supplying a reference voltage, a drive circuit, and a control circuit. And a drive circuit, wherein the supply terminal and the first PM
An OS transistor is connected to the source, the reference terminal is connected to the source of the second NMOS transistor, and the drain of the first PMOS transistor is connected to the second N transistor.
The drain of the MOS transistor is connected to the output terminal, and the input terminal is connected to the gate of the first PMOS transistor and the gate of the second NMOS transistor.

The control circuit includes a fifth PMO to the supply terminal.
The source of the S transistor is connected to the source of the third PMOS transistor, the drain of the fifth PMOS transistor is connected to the gate of the third PMOS transistor, and the drain of the fifth PMOS transistor is connected to the sixth The drain of the sixth NMOS transistor is connected to the output terminal, the drain of the third PMOS transistor is connected to the output terminal, and the eighth terminal is connected to the reference terminal. The source of the NMOS transistor is connected to the source of the fourth NMOS transistor, the drain of the eighth NMOS transistor is connected to the gate of the fourth NMOS transistor, and the drain of the eighth NMOS transistor is connected to the drain of the eighth NMOS transistor. Connecting the gate of the fourth NMOS transistor, The drain of the eighth NMOS transistor is connected to the drain of the seventh PMOS transistor, the source of the seventh PMOS transistor is connected to the output terminal, and the drain of the fourth NMOS transistor is connected to the output terminal. Connecting the input terminal to the input of a first inverter, wherein the output of the first inverter is connected to the gate of the fifth PMOS transistor, the gate of the sixth NMOS transistor, and the seventh PMOS transistor. Gate and the eighth NM
It is connected to the gate of the OS transistor.

[0051]

Next, an output circuit according to a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an output circuit according to a first embodiment of the present invention.

Referring to FIG. 1, the output circuit includes an input terminal H01, an output terminal N01, a supply terminal for supplying a power supply voltage, and a reference terminal for supplying a reference voltage, and the supply terminal and the PMOS transistor P1. Are connected, the reference terminal is connected to the source of the NMOS transistor N2,
The drain of the PMOS transistor P1, the drain of the NMOS transistor N1, and the output terminal N01 are connected,
The input terminal H01, the gate of the PMOS transistor P1, and the gate of the NMOS transistor N2 are connected to form a drive circuit.

Further, this output circuit has a PM
The source of the OS transistor P2 is connected to the source of the PMOS transistor P4, the drain of the PMOS transistor P2 is connected to the gate of the PMOS transistor P4, the drain of the PMOS transistor P2 is connected to the drain of the NMOS transistor N2, and the NMOS transistor is connected. The source of N2 is connected to the output terminal N01, and PM
The drain of the OS transistor P4 is connected to the output terminal N01, and the reference terminal is connected to the source of the NMOS transistor N3 and the source of the NMOS transistor N4.
The drain of the OS transistor N3 is connected to the gate of the NMOS transistor N4, and the NMOS transistor N3
Is connected to the drain of the PMOS transistor P3, the source of the PMOS transistor P3 is connected to the output terminal N01, the drain of the NMOS transistor N4 is connected to the output terminal N01, and the input terminal H01 and the input of the inverter INV1 are connected. The output of the inverter INV1 is connected to the gate of the PMOS transistor P2 and the NMO
The control circuit is connected to the gate of the S transistor N2, the gate of the PMOS transistor P3, and the gate of the NMOS transistor N3.

Next, the operation will be described. First,
A case where the input signal changes from Lo to Hi will be described.

When the input terminal H01 is Lo, the PMOS transistor P1, the NMOS transistor N2, and the NMOS transistor N3 are turned on, and all other transistors are turned on.
The output terminal N01 becomes Hi because of FF. Then P
Since the output terminal N01 is Hi, the MOS transistor P4 has N
Since Hi propagates through MOS transistor N2, O
It becomes FF state.

Next, when the input terminal H01 is changed from Lo to Hi, the PMOS transistor P1, the NMOS transistor N2, the NMOS transistor N3 and the PMOS transistor P4 are turned off, and the NMOS transistors N1 and PMO are turned off.
S transistor P2, PMOS transistor P3, NM
The OS transistor N4 turns on, and the output terminal N01 changes from Hi to Lo. At this time, the voltage at the contact B rises from Lo to the same voltage as the output terminal N01. PMO
Since the S transistor P3 is a PMOS transistor, it rises to a higher level than the conventional example. PMOS transistor P
Since 3 is a PMOS transistor, it drives the NMOS transistor N4 without dropping by one step of the threshold value Vt.
Good initial response.

Next, when the output terminal N01 approaches the Lo level, the voltage of the contact B decreases as the voltage of the output terminal N01 decreases. However, since there is a level drop due to the PMOS transistor P3, the NMOS transistor N4 is not completely turned off. As a result, NMO
The S transistor N4 absorbs noise and prevents undershoot. Further, when the signal change of the output terminal N01 is completely completed and the output terminal N01 becomes the GND level, only the NMOS transistor N1 is turned on to draw the load drive current, so that the output terminal N01 holds Lo. PM
Since the OS transistor P1 and the PMOS transistor P4 are completely turned off, no leak flows.

Next, a case where the input signal changes from Hi to Lo will be described.

When the input terminal H01 is Hi, each of the NMOS transistor N1, the PMOS transistor P2 and the PMOS transistor P3 is turned on, and all the other transistors are turned off, so that the output terminal N01 becomes Lo.
At this time, since the output terminal N01 is Lo, the NMOS transistor N4 is turned off because Lo propagates through the PMOS transistor P3.

Next, when the input terminal H01 is changed from Hi to Lo, the NMOS transistor N1, the PMOS transistor P2, the PMOS transistor P3 and the NMOS transistor N4 are turned off, and the PMOS transistor P is turned off.
1, the NMOS transistor N2, the NMOS transistor N3, and the PMOS transistor P4 are turned on, and the output terminal N01 changes from Lo to Hi. At this time, the voltage at the contact A falls from Hi to the same voltage as the output terminal N01. Since the NMOS transistor N2 is an NMOS transistor, it falls to a lower level than the conventional example. N
Since the MOS transistor N2 is an NMOS transistor, it drives the PMOS transistor P4 without dropping by one step of the threshold value Vt, so that the initial response is good.

Next, when the output terminal N01 approaches the Hi level, the voltage of the contact A increases as the voltage of the output terminal N01 increases. However, since the level of the NMOS transistor N2 rises, the PMOS transistor P4 is not completely turned off. As a result, PMO
The S transistor P4 absorbs noise and prevents overshoot. Further, when the signal change of the output terminal N01 is completely completed and the output terminal N01 becomes the VDD level, only the PMOS transistor P1 is turned on to output the load driving current, so that the output terminal N01 holds Hi. NM
Since the OS transistor N1 and the NMOS transistor N4 are completely turned off, no leak flows.

Next, an output circuit according to a second embodiment of the present invention will be described with reference to the drawings.

FIG. 2 shows the first embodiment as a 3-state.
This is an output circuit transformed into a type.

Referring to FIG. 2, the output circuit includes an input terminal H01, an input terminal H02, an output terminal N01,
A supply terminal VDD for supplying a power supply voltage, a reference terminal for supplying a reference voltage, and a PMOS transistor P1 having a source connected to the supply terminal and an NMOS transistor N1 having a source connected to the reference terminal. And
The drain of the PMOS transistor P1, the drain of the NMOS transistor N1, and the output terminal N01 are connected, the input terminal H01 is connected to the gate of the PMOS transistor P1, and the input terminal H02 is connected to the gate of the NMOS transistor N1 to drive the driving circuit. Make up.

Further, this output circuit is connected to the input terminal H
01, an inverter INV1 for inputting the signal of the input terminal H02, a PMOS transistor P4 and a PMOS transistor P2 having a source connected to the supply terminal, and a source connected to the reference terminal. NMOS transistors N4 and NM
An OS transistor N3; an NMOS transistor N2 connected in series with the PMOS transistor P2;
It comprises a transistor N3 and a PMOS transistor P3 connected in series.
The OS transistor P3 is connected in series, and the connection point between the PMOS transistor P2 and the NMOS transistor N2 is P
Connected to the gate of the MOS transistor P4, the PMOS
The connection point between the transistor P3 and the NMOS transistor N3 is connected to the gate of the NMOS transistor N4, the output signal of the inverter INV1 is connected to the gates of the PMOS transistor P2 and the NMOS transistor N2, and the output signal of the inverter INV2 is connected to the PMOS transistor P3. Connected to the gate of the NMOS transistor N3, the connection point between the NMOS transistor N2 and the PMOS transistor P3, the connection point between the PMOS transistor P4 and the NMOS transistor N4, and the output terminal are connected to form a control circuit.

Next, the operation will be described.

Since the second embodiment is a modification of the first embodiment to a 3-state type, the basic operation is the same. Input terminal H01 is Hi
By setting the level and the input terminal H02 to the Lo level, the output terminal N01 can be set to the high impedance state.
First, this high impedance state will be described.

When the signal at the input terminal H01 is Hi, PM
Since the OS transistor P1 is OFF and Hi is input to the inverter INV1, the output becomes Lo. As a result, the NMOS transistor N2 is turned off and the PMOS transistor P2 is turned on.
FF. Therefore, the output terminal N01 does not go high because there is no transistor that propagates the high level at the output terminal N01.

Next, when the signal at the input terminal H02 is Lo, the NMOS transistor N1 is turned off and the inverter I
Since Lo is input to NV2, the output becomes Hi. As a result, the PMOS transistor P3 is turned off and the NMOS transistor P3 is turned off.
Since the transistor N3 turns on, the NMOS transistor N4 turns off. Therefore, the output terminal N01 does not go low because there is no transistor that propagates the Lo level at the output terminal N01. Therefore, the output terminal N01 does not become Hi or Lo, and becomes in a high impedance state.

Next, the case where the signal at the input terminal H01 changes from Lo to Hi will be described. When the input terminal H01 and the input terminal H02 are Lo, the PMOS transistor P1, the NMOS transistor N2, and the NMOS transistor N3 are turned on, and all the other transistors are turned off, so that the output terminal N01 becomes Hi. At this time, since the output terminal N01 is Hi, the PMOS transistor P4 is turned off because Hi propagates through the NMOS transistor N2.

Next, when the input terminals H01 and H02 are changed from Lo to Hi, the PMOS transistors P1 and NM are changed.
OS transistor N2, NMOS transistor N3, P
The MOS transistor P4 is turned off, the NMOS transistor N1, the PMOS transistor P2, the PMOS transistor P3, and the NMOS transistor N4 are turned on, and the output terminal N01 changes from Hi to Lo. At this time, the voltage at the contact B rises from Lo to the same voltage as the output terminal N01. Since the PMOS transistor P3 is a PMOS transistor, it rises to a higher level than the conventional example. PMOS
Since the transistor P3 is a PMOS transistor, the NMOS transistor N4 does not drop one step by the threshold value Vt.
, The initial response is good.

Next, when the output terminal N01 approaches the Lo level, the voltage of the contact B decreases as the voltage of the output terminal N01 decreases. However, since there is a level drop due to the PMOS transistor P3, the NMOS transistor N4 is not completely turned off. As a result, NMO
The S transistor N4 absorbs noise and prevents undershoot. Further, when the signal change of the output terminal N01 is completely completed and the output terminal N01 becomes the GND level, only the NMOS transistor N1 is turned on to draw the load drive current, so that the output terminal N01 holds Lo. PM
Since the OS transistor P1 and the PMOS transistor P4 are completely turned off, no leak flows.

Next, a case where the input signal changes from Hi to Lo will be described.

When the input terminals H01 and H02 are Hi, the NMOS transistor N1 and the PMOS transistor P
2. Since the PMOS transistor P3 is turned on and all other transistors are turned off, the output terminal N01 becomes Lo. At this time, the NMOS transistor N4 is connected to the output terminal N
01 is Lo through the PMOS transistor P3.
Is propagated, so that it is turned off.

Next, when the input terminals H01 and H02 are changed from Hi to Lo, the NMOS transistors N1 and P2 are changed.
MOS transistor P2, PMOS transistor P3
The NMOS transistor N4 turns off, the PMOS transistor P1, the NMOS transistor N2, the NMOS transistor N3, and the PMOS transistor P4 turn on,
The output terminal N01 changes from Lo to Hi. At this time, the voltage of A decreases from Hi to the same voltage as the output terminal N01. Since the NMOS transistor N2 is an NMOS transistor, it falls to a lower level than the conventional example. Since the NMOS transistor N2 is an NMOS transistor, the NMOS transistor N2 drives the PMOS transistor P4 without dropping by one step of the threshold value Vt, so that the initial response is good.

Next, when the output terminal N01 approaches the Hi level, the voltage of the contact A increases as the voltage of the output terminal N01 increases. However, since the level is increased by the NMOS transistor N2, the PMOS transistor P4 is not completely turned off. As a result, PM
The OS transistor P4 absorbs noise and prevents overshoot.

When the signal change at the output terminal N01 is completely completed and the output terminal N01 becomes the VDD level, only the PMOS transistor P1 is turned on to output a load drive current, so that the output terminal N01 holds Hi. . NM
Since the OS transistor N1 and the NMOS transistor N4 are completely turned off, no leak flows.

[0079]

A first effect of the present invention is that overshoot and undershoot can be absorbed without slow landing, thereby easily realizing high speed. The reason will be described below with reference to FIGS.

First, the reason why the undershoot can be absorbed will be described. The signal at the output terminal N01 shown in FIG.
In the process of changing from i to Lo, when the output terminal N01 exceeds the threshold level and approaches the Lo level, the PMOS transistor P3 is turned ON because the gate is at the Lo level. Then, the output terminal N01
Signal drops to the Lo level, but since the transistor P3 is a PMOS transistor, the Vds voltage is | Vgs
│ voltage and the PMOS transistor P3 becomes O
The N state continues. Therefore, the potential of the signal at the contact point B shown in FIG. 3 holds the threshold level (Vth) of the NMOS transistor N4 even when the output terminal N01 drops. Then, following the fluctuation of the GND potential shown in FIG.
The gate potential of the MOS transistor N4 (the potential of the signal B) also fluctuates.

As a result, when GND tries to change to a negative potential, the Vgs voltage of the NMOS transistor N4 increases, the Ids current flowing to GND increases, and the original GND increases.
Return to potential. Conversely, when GND attempts to change to the positive potential, the Vgs voltage of the NMOS transistor N4 decreases, and the Ids current flowing to GND decreases, returning to the original GND potential.

With the above operation, the PMOS is used to increase the speed.
Even if the performance of the transistor P1 and the NMOS transistor N1 is increased and an undershoot occurs, the undershoot can be absorbed by the NMOS transistor N4, so that the signal noise of the output terminal N01 can be reduced. From the simulation result of the first embodiment (FIG. 3) and the simulation result of the prior art (FIG. 6), the conventional undershoot of about 640 mv can be reduced to about 91 mv.

Next, the reason why overshoot can be absorbed will be described. The signal at the output terminal N01 shown in FIG.
In the process of changing from o to Hi, when the output terminal N01 exceeds the threshold level and approaches the Hi level, the NMOS transistor N2 is turned ON because the gate is at the Hi level. Then, the output terminal N01
Rises to the Hi level, but since the transistor N2 is an NMOS transistor, the Vds voltage becomes higher than the Vgs voltage, and the NMOS transistor N2 remains ON. Therefore, the potential of the signal at the contact A shown in FIG. 3 holds the threshold level (Vth) of the PMOS transistor P4 even when the output terminal N01 rises. Then, following the fluctuation of the VDD potential shown in FIG. 3, the gate potential (the potential of the signal A) of the PMOS transistor P4 also changes.

As a result, if it is attempted to change the power supply potential VDD to the plus side from the original potential, the PMOS transistor P
| Vgs | voltage of PM4 increases from power supply potential VDD to PM
The Ids current flowing through the OS transistor P4 increases and returns to the original VDD potential. Conversely, when the power supply potential VDD tries to change to the minus side from the original potential, the | Vgs | voltage of the PMOS transistor P4 decreases, and the Ids current flowing from the power supply potential VDD to the PMOS transistor P4 decreases to return to the original power supply potential VDD. return.

With the above operation, the PMOS is used to increase the speed.
Even if the performance of the transistor P1 and the NMOS transistor N1 is increased and an overshoot occurs, the overshoot can be absorbed by the PMOS transistor P4, so that the signal noise of the output terminal N01 can be reduced. From the simulation result of the first embodiment (FIG. 3) and the simulation result of the conventional technique (FIG. 6), the conventional overshoot of about 90 mv can be reduced to about 85 mv.

The second effect is that the initial response of the output signal is good. The reason will be described first for the case where the output signal changes from Hi to Lo.

The signal at the output terminal N01 shown in FIG.
In the process of changing to Lo, unlike the conventional example, the PMO
Since the S transistor P3 is constituted by a PMOS transistor, the voltage at the contact B can drive the NMOS transistor N4 without dropping by the threshold value Vt of the PMOS transistor 3. As a result, the PMOS transistor P3 gives a sufficient driving force to the NMOS transistor N4, so that the time when the NMOS transistor N4 changes from OFF to ON is shortened, and the initial response is improved.

Next, a case where the output signal changes from Lo to Hi will be described. In the initial process in which the signal at the output terminal N01 shown in FIG. 1 changes from Lo to Hi, unlike the conventional example, the NMOS transistor N2 is composed of an NMOS transistor. The PMOS transistor P4 can be driven without increasing by Vt. So NMO
Since the S transistor N2 gives a sufficient driving force to the PMOS transistor P4, the PMOS transistor P4
The time required to change from FF to ON is shortened, and the initial response is improved.

A third effect is that the area of the output circuit can be reduced as compared with the conventional example. The reason is that the transistor size of the control circuit shown in FIG. 1, that is, the gate width W of the PMOS transistor P4 and the NMOS transistor N4 can be reduced. The power supply voltage 3.3 in the circuit shown in FIG.
Given the conditions of V, Vt = 0.7 V and W = 300 μm, the PMOS transistor P3 driving the NMOS transistor N4 is a PMOS transistor, and the voltage at the contact B does not drop by the threshold value Vt.
It becomes 3.3V.

That is, the PMOS transistor P of the present invention
4. The NMOS transistor N4 can be configured with W = 300 μm, which is the same as the ordinary output circuit described in the third problem of the “problem to be solved by the invention”.

Next, the PMO required to reduce noise
S transistor P2, NMOS transistor N2, PM
When W of the OS transistor P3, NMOS transistor N3, and inverter INV1 is calculated, W of the PMOS transistor P2, NMOS transistor N2, PMOS transistor P3, and NMOS transistor N3 is PMOS
15% of transistor P4 and NMOS transistor N4
Therefore, 45 μm is required for each. Similarly, the gate width W of the inverter INV1 that drives the PMOS transistor P2 and the NMOS transistor N3 is:
6.75 μm. As a result, the sum of the gate widths W of the present invention shown in FIG. 1 is P1 + N1 + (P2 + N2 + P3 + N
3 + INV1) + P4 + N4 = 300 × 2 + (45 × 4
+ 6.75 × 2) + 300 × 2 = 1393.5 (μm)
Becomes

Accordingly, the sum of the gate width W of the present invention is 1703 μm, whereas the sum of the gate width W of the conventional output circuit obtained in the third problem of the above-mentioned “Problems to be Solved by the Invention” is 1393.5 μm.

As a result, the area of the conventional example is 1.40 times as large as that of a normal output circuit. However, the present invention can suppress the increase by 1.16 times, and can reduce the increase by 24%.
As described above, the first embodiment has been described, but the same effect can be obtained in the second embodiment.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an output circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an output circuit according to a second embodiment of the present invention.

FIG. 3 is a simulation waveform chart according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional output circuit.

5A and 5B are output waveform diagrams, and FIG. 5A is a waveform diagram of a conventional output circuit, and FIG. 5B is a waveform diagram of a conventional example when the speed is increased.

FIG. 6 is a waveform diagram of a simulation result of a conventional example.

[Explanation of symbols]

 H01, H02 Input terminal N01 Output terminal P1, P2, P3, P4 PMOS transistor N1, N2, P3, P4 NMOS transistor INV1, INV2 Inverter VDD supply terminal A, B, C, D contacts

Claims (4)

(57) [Claims] An input terminal, an output terminal, a supply terminal for supplying a power supply voltage, and a reference terminal for supplying a reference voltage, wherein the supply terminal is connected to one end of a first insulated gate field effect transistor. Connecting the reference terminal to one end of a second insulated gate field effect transistor, and connecting the other end of the first insulated gate field effect transistor, the other end of the second insulated gate field effect transistor, and the output terminal. A drive circuit configured to connect and connect the input terminal, the gate of the first insulated gate field effect transistor, and the gate of the second insulated gate field effect transistor; One end of a gate field effect transistor is connected to one end of a third insulated gate field effect transistor, and the other end of the fifth insulated gate field effect transistor is connected to the third insulated gate field effect transistor. And the other end of the fifth insulated gate field effect transistor is connected to one end of the sixth insulated gate field effect transistor, and the other of the sixth insulated gate field effect transistor is connected. End and the output terminal, and the third
The other end of the insulated gate field effect transistor is connected to the output terminal, and the reference terminal is connected to one end of an eighth insulated gate field effect transistor and one end of a fourth insulated gate field effect transistor. The other end of the insulated gate field effect transistor is connected to the gate of the fourth insulated gate field effect transistor, and the other end of the eighth insulated gate field effect transistor is connected to one end of the seventh insulated gate field effect transistor. Connecting the other end of the seventh insulated gate field effect transistor and the output terminal,
The other end of the fourth insulated gate field effect transistor is connected to the output terminal, the input terminal is connected to the input terminal of a first inverter, and the output terminal of the first inverter is connected to the fifth terminal. A control connected to the gate of the insulated gate field effect transistor, the gate of the sixth insulated gate field effect transistor, the gate of the seventh insulated gate field effect transistor, and the gate of the eighth insulated gate field effect transistor An output circuit having a circuit. 2. The first, third, fifth, and seventh insulated gate field-effect transistors are P-channel insulated gate field-effect transistors, and the second, fourth, sixth, and eighth insulated gate field-effect transistors are formed. 2. The output circuit according to claim 1, wherein the field effect transistor is an N-channel insulated gate field effect transistor. 3. A first input terminal, a second input terminal,
An output terminal, a supply terminal for supplying a power supply voltage, and a reference terminal for supplying a reference voltage. The supply terminal is connected to one end of a ninth insulated gate field effect transistor. Connecting one end of a gate field effect transistor, connecting the other end of the ninth insulated gate field effect transistor, the other end of the tenth insulated gate field effect transistor, and the output terminal, and connecting the first input terminal And a drive circuit configured by connecting the gate of the ninth insulated gate field effect transistor and the second input terminal and the gate of the tenth insulated gate field effect transistor; One end of the thirteenth insulated gate field effect transistor is connected to one end of the eleventh insulated gate field effect transistor, and the thirteenth insulated gate field effect transistor is connected. Connect the other end of the static and the gate of said eleventh insulated gate field effect transistor, the first 13
Connecting the other end of the insulated gate field effect transistor to one end of a fourteenth insulated gate field effect transistor; connecting the other end of the fourteenth insulated gate field effect transistor to the output terminal; The other end of the gate field effect transistor is connected to the output terminal; the reference terminal is connected to one end of a sixteenth insulated gate field effect transistor and one end of a twelfth insulated gate field effect transistor; Connecting the other end of the field effect transistor to the gate of the twelfth insulated gate field effect transistor; connecting the other end of the sixteenth insulated gate field effect transistor to one end of the fifteenth insulated gate field effect transistor; Connecting the other end of the fifteenth insulated gate field effect transistor to the output terminal;
The other end of the insulated gate field effect transistor is connected to the output terminal, the first input terminal is connected to the input terminal of a ninth inverter, and the output terminal of the ninth inverter is connected to the thirteenth inverter. Connecting the gate of the insulated gate field effect transistor and the gate of the fourteenth insulated gate field effect transistor, connecting the second input terminal to the input terminal of the tenth inverter, and connecting the output terminal of the tenth inverter to An output circuit comprising a control circuit connected to the gate of the fifteenth insulated gate field effect transistor and the gate of the sixteenth insulated gate field effect transistor. 4. The ninth, eleventh, thirteenth, and fifteenth insulated gate field-effect transistors are P-channel insulated gate field-effect transistors,
4. The output circuit according to claim 3, wherein the second, fourteenth, and sixteenth insulated gate field effect transistors are N-channel insulated gate field effect transistors.