JPH01112815A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To attain stable circuit operation over a wide range of a power voltage by supplying a lower voltage than a conventional power supply fed to an integrated internal circuit as the power voltage of the output stage. CONSTITUTION:A data output circuit 2 consists of AND gates 8, 9 whose one end is connected to a couple of input/output data lines 6, 7 of the memory and whose other end receives a control signal phiout generated in the memory inside and a precharge/discharge type output buffer in which two N-channel MOS TRs 10, 11 whose gate receives an output of the AND gates 8, 9 respectively are connected in series between a voltage drop output node 6 of a voltage drop circuit 3 and a ground line 5. The voltage drop circuit 3 decreases a VDD power voltage supplied at the outside of the chip and supplies it as the power voltage VDW of the data output buffer. Moreover, the P-channel MOS TR T4 and the MOS TR T5 are connected between the power line 4 and the ground line 5.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to semiconductor integrated circuits such as semiconductor memories.
In particular, it relates to data output circuits.

(Prior Art) FIG. 5 shows a power supply system and an output load system for a data output circuit on a conventional semiconductor memory chip F50. That is, the data output circuit 51 includes AND gates 54 and 55, each of which has one end connected to a pair of input/output data lines 52 and 53 of the memory, and the other end of which is supplied with a control signal φout generated inside the memory. Andgut 54, 55
A precharge/discharge type transistor in which two N-channel/I/MOS transistors 56 and 57, each output of which is given to a corresponding dart, are connected in series between a power supply line 58 and a ground line 59 on the chip. It consists of an output buffer and an output buffer. 6
0 is the VDD power pin of the chip 50, 61 is the parasitic resistance component of the power line 5gK on the chip, 62 is the ground pin of the chip 50, and 63 is the ground line 5 on the chip.
A parasitic resistance component 64 is an output pin of the chip 50 and is connected to the output node of the output buffer 1.

On the other hand, 65 is chip 5 outside the chip.

66 is a stabilizing capacitor of the power supply, 61 is a power line, 68 is a grounding end, 69 is a grounding line, 70 and 11 are resistance components and inductance components parasitic to the power line errtc, 72. and 73 are resistance components and inductance components parasitic to the grounding wire 69, 14 is an output line, 15 is an output load container, 76 and 77
are resistance components and inductance components parasitic to the output line 74.

When data is output from the memory chip 50, fluctuations occur between the power supply potential and the ground potential as the output load capacitor 75 is charged and discharged at high speed. In particular, the overshoot of the ground potential that occurs when outputting 1 data 10'' is larger than the undershoot of the ground potential that occurs when outputting data @1'', which causes malfunction of the internal circuit of the chip 50. becomes. The above-mentioned overshading of the ground potential is caused by the time increment dr/d t of the discharge current applied to the ground wire 59.69 due to the rapid discharge of the output load capacity 15.
The majority is occupied by @L dI/dt, which is an inductance component parasitically present in the discharge current path. When the power supply voltage used increases, the gm (mutual conductance) of the transistor of the data output circuit 51 increases.
The upper value is 9, and the noise sensitivity of the memory chip 50 also increases, so
Due to the above-mentioned open knee), malfunctions of the internal circuit become more likely to occur.

Here, the operation when the data output circuit 51Vc in FIG. 5 outputs data ``O'' is shown in FIGS. 6(a) and (b).
This will be explained in detail with reference to . When outputting data @0″,
When one data line 52 becomes a low potential and the other data line 53 becomes a high potential, and the control signal φout becomes a high potential, one of the AND GO J-54 and 55, 55, is selected. Output node N2 of and dart 55
The potential of the transistor 51 is the threshold voltage aEV? The voltage rises above H, making the transistor 51 conductive, causing the output load capacitance 75 to be discharged, and setting the data output D out of the output pin 64 to a low potential, thereby reducing the data ``0''.
When the output load capacitance Rvs is discharged, a large discharge current Id is generated through the transistor 57, and the resistance components 76, 63, 72 and Due to the inductance component 71.73, the potential of the ground pin 62 of the chip 50 has a large kina overshade as shown in the diagram w Appears in electric potential.

Therefore, especially in the case of a memory chip having a plurality of output pins, when outputting data 10'' from each corresponding data output circuit to each output pin, the overshading is significant. This may cause the internal circuits of the memory to malfunction.

Conventionally, when there is only one ground-side driving transistor per output pin as in the data output circuit described above, K reduces the channel width of the driving transistor 57 in order to suppress the circuit malfunction as described above. Or, the 6th
As shown by the dotted line in the figure (aJ), by slowing down the rising speed of the potential of the node N2 (slowing down the change in the rising waveform), and by significantly suppressing the current driving capability of the driving transistor 51, , Fig. 6 (as shown by the dotted line in bJ, to suppress the overshade,
But when I do this, output pin 64
As the potential of K gradually decreases as shown by the dotted line in Figure 6(a), the access time of the ``O'' output of the memory is significantly delayed, and the high-speed performance of the memory must be sacrificed significantly. It will stop happening. This is inconvenient when high speed data access is important.

(Problems to be Solved by the Invention) The present invention has been made in order to solve the above-mentioned problem that data output speed must be sacrificed significantly in order to suppress power fluctuations during data output. , it is possible to suppress the overshoot of the ground potential associated with "o'" data output and prevent malfunction of the internal circuit without significantly sacrificing the data output speed, and the system is stable over a wide range of power supply voltages. An object of the present invention is to provide a semiconductor integrated circuit that can perform various circuit operations.

[Structure of the invention]

(Means for Solving the Problems) The semiconductor integrated circuit of the present invention supplies a lower step-down voltage as the power supply voltage of the output stage of the data output circuit than the normal power supply voltage that is supplied to the internal circuits of the integrated circuit. It is characterized by being K.

(Function) Since the data output @1″ is a step-down voltage,
'The temporal increment of the current discharged from the output load during data output is reduced, and the overshoot of the ground potential is reduced. Therefore, power fluctuations during data output can be suppressed without significantly sacrificing data output speed, and stable operation can be achieved over a wide range of power supply voltages without causing internal circuit malfunctions relative to the power supply margin. It becomes possible to have the

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the data output circuit 2 on the semiconductor memory chip f1.
Also shown are a step-down circuit 3, a power supply line 4 and a ground line 5 on the chip, and a power supply system and an output load system outside the chip. That is, the data output circuit 2 includes an AND gate 8.9, one end of which is connected to a pair of input/output data lines 6.1 of the memory, and the other end of which is supplied with a surface control signal φout generated inside the memory; Each output of this AND f-) 8.9 corresponds to two N-channel MOs given K
A precharge/discharge type output buffer 1 includes eight transistors 10 and 11 connected in series between a step-down output node N6 of a step-down circuit 3 and a ground line 5. The step-down circuit 3 steps down the VDD power supply voltage supplied from outside the chip to provide the power supply voltage Vl of the data output buffer 1.
) Supplied as iF (21: Oh, the above AND gate 8
, 9 and other memory internal circuits are connected to the external power supply E.
EVDD is supplied) and a) is configured as shown in FIG. 2, for example. That is, the power line 4 and the ground line 5
Three P-channel MO8) transistors T7.1 and T7.1 each have their substrates and sources connected to each other, and have their gates and drains connected to each other. 'r,? ,'I',? are connected in series. Further, a P-channel MO8) transistor Ts'H having a substrate and a source connected to each other and a P-channel MO8) transistor Ts'H having a substrate and a source connected to each other and a gate and a drain connected to each other is connected to the power supply line 4. and the ground wire 5. The series connection point (node N7) of the transistors T2 and T3 is connected to the gate of the transistor T4. In this case, the potential of the node N7 is VDD −21VTPl
(VTP is the gate threshold voltage of a P-channel transistor) so that transistors TI, T, 2. The voltage ratio of TJ is set, and the transistor T4. Transistors T4. The gm ratio of T5 is set. Here, the characteristics of the step-down circuit 3 (power supply voltage V
An example of DD versus output step-down voltage (VDW) is shown in FIG. The step-down voltage VDW is VDD −21VTPIO up to around the minimum value VMMIN of the usage range of the power supply voltage VDD.
When VDD is higher than or equal to VDDMIN, the range is VDD
DMIN -21VTP I It becomes a constant voltage close to K. The constant voltage is s VDI]j High level output voltage of output buffer 1 at IN voltage VOH% Output current (outflow current) IOH
and is set to a value that can guarantee the inflow current IOH.

Note that in FIG. 1, each part other than the above-mentioned explanation part is the same as that with reference to FIG. 5, and is given the same reference numeral as in FIG. 5, and the explanation thereof will be omitted.

Next, the operation of the data output circuit 2 when outputting data will be explained with reference to FIG.

If the vDD voltage is greater than VDDMIN, VDD
Constant voltage step-down voltage VDW close to MIN -21VTPIK
is given as the power supply voltage of the output buffer 1. "l
``When reading data, one input/output data line 6 is at a high level and the other input/output data line 1 is at a low level], and when the control signal φ0TJT is on, the gate of the transistor 10 is at a high level. Then, the transistor 10 is turned on and the output load capacitor 15 is charged. In this case,
Since the charging potential is a step-down voltage EVDW and is lower than the power supply voltage EEVDD, the change in the charging current is gradual compared to the case where the VDD power supply voltage is applied to the output buffer 1, and the potentials of the power supply line 4 and the ground line 5 The undershoot of is small,
On the other hand, when reading @0'' data, one input/output data line 6 is at a low level and the other input/output data line 7 is at a high level, and when the control signal φOUT is on, the gate of the transistor 11 (node NZ) is at a high level),
Transistor 11 is turned on and output load capacitance 25 is discharged. In this case, the discharge starting potential is the step-down voltage vn
Since w is lower than the power supply voltage vDD, the temporal increment d I/d of the discharge current Id flowing through the transistor 11 is
t decreases. Therefore, the product of the inductance component existing in the discharge current path and the above ax/dt is small, and the magnitude and width of fluctuations (undaterination) in the electrophoretic wire 4 and the ground wire 5 are also small.

In addition, fluctuations in the power supply line 4 and ground line 5 as described above are caused by VD.
Even if the D power supply voltage increases further, the output/(T77
) The power supply is a step-down voltage VDW (= VDDMIN −2
1VTP+), the power supply of the output buffer 1 does not increase as vDD increases.

That is, according to the memory chip having the step-down circuit as described above, since the step-down voltage VDW is supplied as a power source for the output buffer 1, the gate drive of the output buffer 1 transistor 10 or 11 with a steep waveform is performed. Even when a voltage is applied, the power supply fluctuations are small, so there is no need to sacrifice data output speed significantly.Furthermore, power fluctuations are small over a wide power supply voltage range, causing a reduction in data output speed or malfunction of the chip's internal circuits. This makes it possible to perform stable operation without any problems. In addition, the step-down voltage E
VDW is the high level output voltage of the output buffer 7 at the VDD side NtEH, and the output currents IOH and IO
Since the voltage is set to ensure L, the specifications of these output characteristics can be satisfied.

〔Effect of the invention〕

As described above, according to the semiconductor integrated circuit of the present invention, the oversheet of the ground potential accompanying the "O" data output is suppressed and the malfunction of the internal circuit is prevented without significantly sacrificing the data output speed. This enables stable circuit operation over a wide range of power supply voltages. Therefore, when the present invention is applied to a semiconductor memory having multiple data output circuits that simultaneously output data from multiple pits, it is possible to avoid sacrificing the high speed of data access.
, stable circuit operation can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a memory chip, an external power supply system, and an output load system according to an embodiment of the semiconductor integrated circuit of the present invention, and FIG. 2 is a circuit diagram showing a specific example of the step-down circuit in FIG. 1. 3 shows the characteristics of the step-down circuit shown in FIG.
a) and (b) are voltage waveform diagrams showing the operation of the data output circuit in the memory chip in Figure 1 and power supply fluctuations of the ground line, and Figure 5 is a diagram showing the conventional memory chip, external power supply system, and output load system. The circuit diagrams shown in FIGS. 6(a) and 6(b) are voltage waveform diagrams showing the operation of the data output circuit in the memory chip of FIG. 5 and power fluctuations of the power supply line and the ground line. 1...Memory chip, 2...Data output circuit, 3.
...Step-down circuit, 8.9...AND gate, 10.11
...Output stage transistor Patent attorney for applicant Takehiko Suzue - Electric power supply voltage V (1) Fig. 3 1 hour 1 hour Fig. 4 - Time Fig. 6

Claims (2)

[Claims] (1) A semiconductor integrated circuit comprising a built-in data output circuit and supplying a step-down voltage lower than the normal power supply voltage supplied to the internal circuits of the integrated circuit as the power supply voltage of the output stage of the data output circuit. (2) The semiconductor integrated circuit according to claim 1, further comprising a step-down circuit that outputs a constant step-down voltage that is higher than a certain set value of the normal power supply voltage and lower than the power supply voltage. .