KR950012028B1 - Semiconductor memory device with low noise output structure - Google Patents

Abstract

The coupling capacitor of output terminal of a memory is connected to additional power line to decrease noise generated in output terminal. The output terminal of a memory comprises a pull-up and pull-down transistor connected to a VCC and a ground to output data, and a capacitor connected to a ground and a third source which level is same as the VCC.

Description

Semiconductor memory device with low noise output structure

1 is an embodiment of an output stage structure according to the prior art.

2 is a voltage waveform diagram of FIG.

3 is another embodiment of an output stage structure according to the prior art.

4 is a lay-out view of FIG.

5 is a voltage waveform diagram of FIG.

6 is an embodiment of an output stage structure according to the present invention.

7 is a lay-out view of FIG.

8 is a voltage waveform diagram of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having an output stage that realizes low noise.

In general, it is well known in the art that a data output buffer that forms an output terminal of a semiconductor memory device generates a circuit for inputting data read from the memory chip, voltage amplifying it, and outputting it out of a chip. Higher speed of operation due to higher integration of semiconductor memory devices is accompanied by large noise. The main reason for this is that the output stage of the data output buffer (commonly referred to as the "output driver") has a large channel size. When a transition operation is performed in a state, a large peak current is generated, which in turn affects each power line in the chip, causing a large noise, thereby causing a malfunction of the semiconductor memory device. . The reason why the impulsive peak current is generated at the output terminal of the data output buffer is that the channel size of the transistors constituting the output terminal is considerably larger than that of other circuits, and at the power supply voltage level "high". This is because a full swing operation is performed at the ground voltage level "low" or from "low" to the "high" level. Therefore, research is being conducted to realize low noise and speed-up, which are essential requirements of the data output buffer output stage.

In this regard, an embodiment of the output stage structure of the conventional data output buffer is shown in FIG. The structural features of FIG. 1 are as follows. That is, a pull-up transistor 1 and a pull-down (output) for outputting predetermined data by performing a channel-connected series between the power supply voltage VCC and the ground voltage VSS and performing complementary opening and closing operations with each other. The pull-down transistor 2 forms an output stage structure. In addition, the resistor 3 and the capacitor 4 connected to the output terminal in FIG. 1 represent line loading and capacitance present at the pin PIN of the chip. Referring to the output operation of FIG. 1, for example, when the data input signal D is input at a logic "high" level, the pull-down transistor 1 is "turned on" and the pull-down transistor 2 ) Is turned off and the output terminal DOUT is output at the "high" level. On the other hand, when the data input signal D is input at the logic "low" level, the pull-down transistor 1 is "turned off", the pull-down transistor 2 is "turned on", and the output terminal DOUT is brought to the "low" level. Is output. In the above configuration, the pull-up and pull-down transistors 1 and 2 constituting the output driver each have a unique power supply VCC (which means a normal supply voltage) and VSS (which means a normal ground voltage). Will have At this time, since the two-supply power supply VCC and VSS are generally used in the output driver, the capacitance of the line on which the power supply is carried is very small. Therefore, when the "low" level D is input, the VSS noise is largely generated when the charge voltage is discharged from the output terminal DOUT to the VSS. When the "high" level D is input, the VSS noise is generated from the output terminal DOUT. When the power supply voltage is charged toward the side, VCC noise is greatly generated. The voltage waveform diagram showing the noise generated at this time is shown in FIG. The waveform diagram of FIG. 2 shows the least noise among the output waveforms of a byte-wide memory having eight data output buffers, for example, seven out of eight output data are high. In the impedance state, it goes up to the "high" level, falls to the "low" level, and only one shows that it falls to the "low" level in the high impedance state. As shown, VCC noise lowers the speed at which the A1 portion drops from the "low" to the "high" sub-chuck output stage (DOUT). However, since this is smaller than the speed drop from "high" to "low" due to VSS noise A4, it is important to substantially reduce the value of A4, which is critical for chip malfunction and reliability. It is well known that it acts as an inhibitor. In addition, if the level V _OL caused by the ring phenomenon of A5 is about 0.4V or more, the data is recognized as the "high" level data even though the data is the "low" level data. do. Therefore, it is necessary to reduce the level of A5, and to solve this problem, it is essential to reduce the level of A4, as can be seen from the waveform shown.

In order to solve this problem, another embodiment of the output stage structure of the conventional data output buffer is shown in FIG. 3 is a coupling capacitor including a MOS transistor (in FIG. 3, an NMOS transistor) connected at both ends of the electrode to a VCC power supply and a VSS power supply as shown in FIG. capacitor) MC. The configuration as shown in FIG. 3 is implemented as the layout of the layout shown in FIG. That is, both ends of the MOS capacitor are connected between the power supply line (■) on which the VCC is loaded and the power supply line (▨) on the VSS. The reason for having the coupling capacitor MC is to ultimately reduce VSS noise, such as A4 in FIG. 2, which flows into the VSS when the output of the data transitions from the "high" to the "low" level. It is distributed to the coupling capacitor MC before completely exiting to the source pad PAD, thereby reducing VSS noise to a level. That is, as shown in FIG. 5 showing the driving voltage waveform of FIG. 3, when the output stage includes the coupling capacitor MC, the voltage levels of A14 and A15 are considerably larger than those of the waveform shown in FIG. The lower the bar, thereby improving the VSS noise characteristics. However, as described above, 7 out of 8 output data of 8 byte wide memory having 8 data output buffers rise from the high impedance state to the "high" level, fall to the "low" level, and only one is in the high impedance state. When it drops to the "low" level, as shown in FIG. 5, a noise such as A11 is generated, from which the VSS is unnecessarily oscillated by the coupling capacitor MC such as A12. At this time, the output stage DOUT transitioning from the high impedance state to the "low" level generates unwanted curvature along the waveform of the above unstable VSS. This phenomenon becomes more serious as more than one data in the output data of the byte wide memory falls to the "low" level in the high impedance state, which also causes noise different from that in the circuit of FIG. This will cause a decrease in speed.

Accordingly, it is an object of the present invention to provide a semiconductor memory device having an output structure for realizing low noise during a data output operation.

Another object of the present invention is to provide a semiconductor memory device having an output structure with improved speed characteristics during a data output operation.

Still another object of the present invention is to provide an output structure in which the output curve of the data of the second level is not affected by the noise caused by the data output of the first level when simultaneously outputting the data of the first level and the second level. It is to provide a semiconductor memory device having.

In order to achieve the object of the present invention is an output terminal having a pull-up and pull-down transistor that is connected in series between the first power supply and the second power supply, and outputs a predetermined data through complementary opening and closing operation, And a MOS transistor having a capacitor connected between both ends of the electrode between the second power source and the third power source. The third power source is characterized in that the first power source or the second source and the source is the same power source. In addition, the capacitor size of the MOS transistor is more effective than the other components for the dispersion of noise generated from the first power source or the second power source can be more effective.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. A circuit showing an embodiment of the structure of the output stage according to the present invention is shown in FIG. In Fig. 6, the same symbols as those in Figs. 1 and 3 of the conventional drawings indicate the same configuration. As shown in FIG. 6, the configuration characteristic of FIG. 6 is that the coupling capacitor MC is connected to VCC2, which is a different power supply line than the first power supply VCC1 to which the pull-down transistor 91 is connected.

In the configuration as shown in FIG. 6, the third power supply VCC2 to which one end of the electrode of the coupling capacitor MC is connected may be realized through the layout as shown in FIG. 7. As shown in FIG. 7, the power supply line is branched out from the VCC source to the first power supply VCC1 (■) and the third power supply VCC2 (▤) so that the first power supply VCC1 is the output driver 1.2 of FIG. The third power source VCC2 is used as the gate voltage of the coupling capacitor MC of FIG. 7 shows an example in which the second power supply VCC source is distinguished for output (i.e., for DOUT) and for logic of an internal circuit, but is divided in one lead frame, for example. Is used by branching VCC for coupling capacitor from VCC to the output terminal DOUT. In another embodiment, when there is room in the pad PAD, one pad may be separately set for the VCC for the coupling capacitor so that the coupled noise does not affect other power lines. In this way, if the noise is generated during the output operation of the data, it is distributed to the second power supply VSS (▨) and the MC. The noise dispersed in the MC is coupled and transferred to VCC2, and the transferred noise falls into a pad to which the first power source VCC source is connected along the VCC2 line. Therefore, the second power supply VSS noise can be considerably smaller according to the capacity of the MC, and the effect is greater when the position of the MC is close to D.

The voltage waveforms in operation different from those of FIG. 6 and FIG. 7 are shown in FIG. Referring to the output characteristic of the circuit of FIG. 6 according to the present invention, when the data input signal D is input at the logic "high" level, the pull-down transistor 1 is "turned on" and the pull-down transistor 2 is "turned off". When the "high" level is output to the output terminal DOUT and the data input signal D is input to the logic "low" level, the pull-down transistor 1 is "turned off" and the pull-down transistor 2 is "turned on" to the output terminal DOUT. The " low " level is output to perform the same logic operation as conventional circuits. Meanwhile, as shown in FIG. 8, seven out of eight output data of the byte wide memory rise to the "high" level in the high impedance state and fall to the "low" level, and only one is the "low" level in the high impedance state. In this case, since the noise caused by the first power supply VCC1 has no path to be coupled with the second power supply VSS, part A22 of FIG. 8 exhibits the same characteristics as part A2 of FIG. In addition, since the noise generated at the VSS and the output terminal DOUT is distributed to the coupling capacitor MC, the A24 and A25 parts of FIG. 3 have the same characteristics as the A14 and A15 parts of FIG. Accordingly, the present invention improves speed by reducing noise of the second power supply VSS without being affected by the first power supply VCC1.

6 and 7 according to the present invention, and the optimum embodiment realized based on the idea of the present invention to be laid out, the configuration of the output driver shown in FIG. It is evident to those skilled in the art that SG is applicable to all of these forms. For example, the pull-up transistors constituting the output driver of the data output buffer have tended to adopt a large number of PMOS transistors. Therefore, the present invention can be sufficiently obtained even when applied to such a form.

As described above, the present invention includes another power supply line to which one end of the electrode of the coupling capacitor is connected to the output end structure of the semiconductor element, thereby realizing low noise during data output operation and providing an output structure with improved speed characteristics. do. In particular, when outputting data of the first level and the second level at the same time, the output curve of the data of the second level is not affected by the noise caused by the data output of the first level, thereby preventing chip malfunction and There is an effect of improving the reliability.

Claims (6)

An output terminal circuit of a semiconductor memory device, comprising: a pull-up and pull-down transistor for outputting predetermined data through a channel connected in series between a predetermined first power supply and a second power supply and complementary opening and closing operations; An output terminal circuit comprising a MOS transistor having a capacitor connected between two power supplies between three power supplies. The output stage circuit according to claim 1, wherein the first power supply and the second power supply are power supplying a power supply voltage and a ground voltage, respectively. 3. The output stage circuit according to claim 2, wherein the third power source is a power source having the same level as the first power source, and is formed of a power line formed from a branch of a power line on which the first power source is loaded. An output terminal circuit of a semiconductor memory device having an output driver having a channel connected between a predetermined first power supply and a second power supply, the output terminal circuit comprising: a noise dispersing MOS capacitor connected to one end of an electrode of the second power supply; And a third power supply connected to the other end of the electrode. 5. The output stage circuit according to claim 4, wherein the first power supply and the second power supply are power supplying a power supply voltage and a ground voltage, respectively. 6. The output stage circuit according to claim 4 or 5, wherein the third power source is a power source having the same level as the first power source, and is formed of a power line branched from a source of the first power source.