KR100407991B1 - Level Shifter - Google Patents

Level Shifter Download PDF

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Publication number
KR100407991B1
KR100407991B1 KR10-2001-0017114A KR20010017114A KR100407991B1 KR 100407991 B1 KR100407991 B1 KR 100407991B1 KR 20010017114 A KR20010017114 A KR 20010017114A KR 100407991 B1 KR100407991 B1 KR 100407991B1
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KR
South Korea
Prior art keywords
pmos transistor
input
transistor
word line
signal
Prior art date
Application number
KR10-2001-0017114A
Other languages
Korean (ko)
Other versions
KR20020076903A (en
Inventor
김학수
홍현성
Original Assignee
주식회사 하이닉스반도체
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR10-2001-0017114A priority Critical patent/KR100407991B1/en
Publication of KR20020076903A publication Critical patent/KR20020076903A/en
Application granted granted Critical
Publication of KR100407991B1 publication Critical patent/KR100407991B1/en

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by G11C11/00
    • G11C5/14Power supply arrangements, e.g. Power down/chip (de)selection, layout of wiring/power grids, multiple supply levels
    • G11C5/147Voltage reference generators, voltage and current regulators ; Internally lowered supply level ; Compensation for voltage drops
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/356104Bistable circuits using complementary field-effect transistors
    • H03K3/356113Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit

Abstract

The present invention relates to a level shifter which has a fast transition time of an input signal to increase a shift output speed. The present invention relates to a first inverter buffer (IN1) which inverts and outputs an input precharge signal and an output signal thereof. A first NMOS transistor MN1 and a second NMOS transistor MN2 including a second inverter buffer IN2 for determining a switching point of an output for an input signal, each output signal being input to a gate; 2, the second PMOS transistor MP2 and the first PMOS transistor (2) which serve as active loads of the first and second NMOS transistors MN1 and MN2, respectively. A third PMOS transistor MP3 having a drain connected to a drain of the first POMS transistor MP1 in common, a Vpp voltage applied to a source, and a precharge signal input to a gate; And a third NMOS transistor MN3 connected in series with the MOS transistor MP3 and having a precharge signal input to the gate.

Description

Level Shifter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the driving of semiconductor memory devices, and more particularly, to a level shifter capable of bringing the transition time of an input signal early to increase the shift output speed.

In the design of semiconductor integrated circuits, there are cases where a voltage level converter is required for the interface between circuits requiring different voltage levels. For example, many integrated circuits, such as DRAM, operate over a defined voltage range, but require more voltage amplitude to interface with external circuits or provide signals to other circuits included with the DRAM.

Two major challenges of all voltage level converters are the reduction of time required for the conversion of the input signal and the power requirements to complete the conversion.

Hereinafter, a level shifter circuit of the related art will be described with reference to the accompanying drawings.

1 is a circuit diagram of a level shifter in the prior art, and FIG. 2 is a circuit diagram of a word line driver in the prior art.

The prior art level shifter circuit inverts and outputs a first inverter buffer IN1 that inverts an input precharge (PCG) signal and an output signal of the first inverter buffer IN1 again to output an input signal. The first NMOS transistor MN1 to which the second inverter buffer IN2 and the output signal of the second inverter buffer IN2 and the output signal of the first inverter buffer IN1 are respectively input to the gate. And includes a second NMOS transistor MN2, a second PMOS transistor MP2 and a first PMOS transistor MP1 serving as active loads of the first NMOS transistor MN1 and the second NMOS transistor MN2. Here, the gate of the first PMOS transistor MP1 is connected in common to the drain of the second PMOS transistor MP2 and the drain of the second NMOS transistor MN2, and the gate of the second PMOS transistor MP2 is formed in the first manner. 1 PMOS transistor MP1 It is commonly connected to the phosphorus and the drain of the first NMOS transistor MN1.

Here, the Vpp voltage is applied to the source of the first and second PMOS transistors MP1 and MP2, and the Vss voltage is applied to the source of the first and second NMOS transistors MN1 and MN2.

The level shift operation of the level shifter of the prior art configured as described above is as follows.

The operation of the level shifter can be efficiently understood by looking at the state of the sweeping output by the second inverter buffer IN2 input to the gate of the first NMOS transistor MN1, that is, the state of the output voltage MWLB. Can be.

That is, voltage transfer characteristics are as follows.

When the input precharge voltage PCG is at the low level, the output voltage MWLB is also at the low level.

In this state, increasing the voltage level of the input signal increases the Vgs of the first NMOS transistor MN1, which increases the current passing through the first NMOS transistor MN1.

As described above, even though the passage current of the first NMOS transistor MN1 increases, the output voltage does not increase significantly as compared with the former.

The reason why the output voltage Vout does not increase significantly is as follows.

If the output of the inverter buffer IN1 is not greater than the low level (the level of the signal currently being input), the output of the inverter buffer IN1 does not change significantly, and this output is connected to the gate of the second NMOS transistor MN2. 2 There is no big change in the current flowing through the NMOS transistor NM2, and the output signal level does not change significantly.

In this state, when the input continues to increase and becomes greater than the low level and less than the high level, the inverter buffer IN1 operates in the transition region, thereby reducing the current flowing in the second NMOS transistor MN2.

When the current flowing in the second NMOS transistor MN2 decreases, the Vgs voltage of the second NMOS transistor MN2 is lowered to increase the output voltage Vout.

This reduces the Vgs of the first PMOS transistor MP1 to further reduce the current flowing through the first PMOS transistor MP1, thereby lowering the drain-source voltage of the first NMOS transistor MN1.

In this case, the current flowing through the second PMOS transistor MP2 is further increased to increase the level of the voltage that is quickly output.

Therefore, the first PMOS transistor MP1 and the second PMOS transistor MP2 vary the level of the output voltage according to the change in the logic state of the input voltage of the level shifter circuit.

Fig. 2 shows a word line driver having such a prior art level shifter configured at the front end.

The word line driver has a common output terminal connected in series to each other and outputs a sub word line driving signal SUB_WL, and a PMOS transistor MP3 and an NMOS transistor, in which a main word line driving signal MWLB output from a level shifter is input to a gate, respectively. MN3 and an NMOS transistor MN4 connected to an output terminal and having a word line clamping signal WLC input to the gate for discharging the charge remaining in the word line after the word line is deserialized.

Here, the Fx signal is applied to the source of the PMOS transistor MP3. The Fx signal is a signal for delivering a Vpp level to a word line, and has a Vpp level when enabled, but changes to a Vss level when disabled, thereby discharging the charge of the word line.

However, such a prior art level shifter has the following problems.

In the level shift operation, the difference between the transition time of the input signal and the transition time of the output signal is large, and the operation speed is lowered.

This makes it difficult to apply to the high speed data input / output memory.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem of the level shifter of the prior art, and an object thereof is to provide a level shifter capable of increasing the shift output speed by bringing the transition time of an input signal quickly.

1 is a circuit diagram of a prior art level shifter

2 is a circuit diagram of a conventional word line driver.

3 is a circuit diagram of a level shifter according to the present invention.

4 is a circuit diagram of a word line driver according to a first embodiment of the present invention.

5 is a circuit diagram of a word line driver according to a second exemplary embodiment of the present invention.

6 is a graph comparing the operation waveforms of the level shifter and the prior art level shifter according to the present invention.

The level shifter according to the present invention for achieving the above object is a first inverter buffer (IN1) for inverting and outputting the input precharge signal and the first to determine the switching point of the output for the input signal by inverting the output signal again A first NMOS transistor MN1 and a second NMOS transistor MN2 including two inverter buffers IN2 and respective output signals are respectively input to a gate; drains of the first and second NMOS transistors MN1 and MN2 A second PMOS transistor (MP2), a first PMOS transistor (MP1) serving as an active load of the first and second NMOS transistors (MN1) and (MN2), respectively; A third PMOS transistor MP3 connected to a drain in common, a Vpp voltage applied to a source, and a precharge signal input to a gate; a third PMOS transistor MP3 connected in series to the third PMOS transistor MP3 and precharged to a gate It characterized in that it comprises a second NMOS transistor 3 (MN3) that the call type is entered.

Hereinafter, a level shifter and a word line driving circuit according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram of a level shifter according to the present invention.

4 is a circuit diagram of the word line driver according to the first embodiment of the present invention, and FIG. 5 is a circuit diagram of the word line driver according to the second embodiment of the present invention.

3, the first inverter buffer IN1 for inverting and outputting the input precharge (PCG) signal and the output signal of the first inverter buffer IN1 are inverted again to provide an input signal. The first NMOS transistor (IN2) for determining the switching point of the output for the first inverter, the output signal of the second inverter buffer (IN2) and the output signal of the first inverter buffer (IN1) is input to the gate ( MN1, the second NMOS transistor MN2, the second PMOS transistor MP2 and the first PMOS transistor MP1 serving as active loads of the first NMOS transistor MN1 and the second NMOS transistor MN2; And a first PMOS transistor when a drain is commonly connected to a drain of the first POMS transistor MP1, a Vpp voltage is applied to a source, a precharge signal is input to a gate, and an input precharge signal transitions from high to low. Faster than (MP1) A third PMOS transistor MP3 that is turned on to turn off the second PMOS transistor MP2 and a precharge signal that is connected in series with a third PMOS transistor MP3 and inputs a precharge signal to a gate are input at low. It is composed of a third NMOS transistor MN3, which is turned on faster than the first NMOS transistor MN1 when turned high, so that the second PMOS transistor MP2 is turned on quickly. Here, the first PMOS transistor MP1 The gate is connected to the drain of the second PMOS transistor MP2 and the drain of the second NMOS transistor MN2 in common, and the gate of the second PMOS transistor MP2 is connected to the drain of the first PMOS transistor MP1 and the first NMOS. Commonly connected to the drain of the transistor MN1.

Here, the source of the third NMOS transistor MN3 is connected to the ground terminal.

The Vpp voltage is applied to the source of the first and second PMOS transistors MP1 and MP2, and the Vss voltage is applied to the source of the first and second NMOS transistors MN1 and MN2.

The drain of the second PMOS transistor MP2 and the drain of the second NMOS transistor MN2 are commonly connected to an output terminal of the main word line driving signal MWLB_NEW.

As described above, the level shifter of the main word line driving signal MWLB_NEW of the main word line driving signal MWLB_NEW is shifted when the precharge signal input by the third PMOS transistor MP3 and the third NMOS transistor MN3 transitions. The transition to High is made at high speed.

4 and 5 show the configuration of a word line driver employing such a level shifter according to the present invention.

First, the word line driver of FIG. 4 has a common output terminal connected in series to each other and outputs a sub word line driving signal SUB_WL_NEW, and a PMOS transistor having a main word line driving signal MWLB_NEW output from a level shifter as a gate thereof. To the NMOS transistor MN5, which is connected to the output terminal of the MP4) and the NMOS transistor MN4, and a word line clamping signal WLC is input to the gate for discharging the charge remaining on the word line after being connected to the output terminal. It is composed.

Here, the Fx signal is applied to the source of the PMOS transistor MP4. The Fx signal is a signal for delivering a Vpp level to a word line, and has a Vpp level when enabled, but changes to a Vss level when disabled, thereby discharging the charge of the word line.

Since the PMOS transistor MP4 to which the Fx signal is applied has a poor high level transfer characteristic in the discharge operation of the word line, the NMOS transistor MN5 is completely discharged to the Vss level.

The word line driver of FIG. 5 has the same circuit configuration as that of the word line driver of FIG. 4, but is connected to the Vbb terminal instead of the source of the NMOS transistor MN5 at the Vss terminal at the “A” portion. It is to.

The operation characteristics of the level shifter and the word line driver employing the same according to the present invention will be described below.

6 is a graph comparing the operation waveforms of the level shifter according to the present invention and the level shifter of the prior art.

In FIG. 6, when the waveform of the conventional sub word line driving signal SUB_WL is compared with the waveform of the sub word line driving signal SUB_WL_NEW according to the present invention, the operation speed of the word line driver using the level shifter of the present invention is high. Able to know.

A portion "B" in FIG. 6 is a waveform at a word line enable time point, and a portion "C" shows a waveform at a word line diable time point.

Here, the last edge portion of the word line deserial is very important and a precharge signal should be applied after the word line is completely discharged.

The reason is that when the precharge signal comes in while the word line is not completely discharged, the sub threshold current of the cell transistors increases, resulting in a decrease in cell retention time. .

Thus, to make a device with acceptable operation, it is necessary to wait until the word line is fully discharged or to increase the discharge speed.

The present invention improves the slowing of the word line waveform using Vbb to speed up the discharge speed.

Such a level shifter according to the present invention has the following effects.

Transistors that turn on faster than the first PMOS transistor MP1 that acts as an active load when the input precharge signal transitions from high to low than first NMOS transistors MN1 when the precharge signal transitions from low to high The transistor MN3, which is turned on quickly, is configured to reduce the difference between the transition point of the input signal and the transition point of the output signal during the level shift operation, thereby increasing the operation speed.

This has the effect of facilitating the implementation of a high speed data input / output memory or the like.

Claims (5)

  1. A first inverter buffer IN1 for inverting and outputting the input precharge signal and a second inverter buffer IN2 for inverting the output signal thereof again to determine a switching point of the output for the input signal, wherein each output signal is A first NMOS transistor MN1 and a second NMOS transistor MN2 respectively input to the gates;
    The drain outputs of the first and second NMOS transistors MN1 and MN2 are respectively input to gates, so that the second PMOS transistor MP2 and the first serve as active loads of the first and second NMOS transistors MN1 and MN2. PMOS transistor MP1;
    A third PMOS transistor MP3 having a drain connected to a drain of the first POMS transistor MP1 in common, a Vpp voltage applied to a source, and a precharge signal input to a gate;
    And a third NMOS transistor (MN3) connected in series with the third PMOS transistor (MP3) and having a precharge signal input to a gate thereof.
  2. The third PMOS transistor of claim 1, wherein the third PMOS transistor is turned on faster than the first PMOS transistor MP1 when the precharge signal transitions from high to low to cause the second PMOS transistor MP2 to be turned off. When the precharge signal transitions from low to high, the level shifter is turned on faster than the first NMOS transistor (MN1) so that the second PMOS transistor (MP2) is turned on quickly.
  3. The method of claim 1, wherein the Vpp voltage is applied to the sources of the first and second PMOS transistors MP1 and MP2, and the Vss voltage is applied to the sources of the first and second NMOS transistors MN1 and MN2. Level shifter.
  4. The main word line driving signal MWLB_NEW has a common output terminal connected in series to each other and outputting a sub word line driving signal SUB_WL_NEW, respectively. PMOS transistor MP4 and NMOS transistor MN4 input to
    A driver comprising an NMOS transistor MN5 having a word line clamping signal WLC inputted to a gate to be connected to an output terminal for discharging the charge remaining on the word line after the word line is disabled Level shifter.
  5. The NMOS transistors MN4 and MN5 respectively have a source terminal connected to a Vss terminal, or a source terminal of the NMOS transistor MN4 is connected to a Vss terminal and a source terminal of the NMOS transistor MN5 is connected to a Vbb terminal. A level shifter, characterized in that connected to.
KR10-2001-0017114A 2001-03-31 2001-03-31 Level Shifter KR100407991B1 (en)

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Application Number Priority Date Filing Date Title
KR10-2001-0017114A KR100407991B1 (en) 2001-03-31 2001-03-31 Level Shifter

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Application Number Priority Date Filing Date Title
KR10-2001-0017114A KR100407991B1 (en) 2001-03-31 2001-03-31 Level Shifter

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KR100407991B1 true KR100407991B1 (en) 2003-12-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101153114B1 (en) 2009-04-13 2012-06-04 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Level shifters, integrated circuits, systems, and method for operating the level shifters

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100810864B1 (en) * 2006-08-02 2008-03-06 리디스 테크놀로지 인코포레이티드 Precharge Type Level Shift Circuit and Driving Method the same
KR101493867B1 (en) 2008-02-11 2015-02-17 삼성전자주식회사 Level shifting circuit
US8115514B2 (en) * 2009-06-02 2012-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Pre-charged high-speed level shifters

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101153114B1 (en) 2009-04-13 2012-06-04 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Level shifters, integrated circuits, systems, and method for operating the level shifters
US8629704B2 (en) 2009-04-13 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Level shifters, integrated circuits, systems, and methods for operating the level shifters
US9071242B2 (en) 2009-04-13 2015-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Level shifters, methods for making the level shifters and methods of using integrated circuits

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