JPH05276003A - Output circuit device - Google Patents

Abstract

PURPOSE:To suppress production of undershoot/overshoot caused by the effect of an inductive component parasitic to a VDD, GND and a load capacitance when an output level is changed at a high speed in a CMOS invert buffer. CONSTITUTION:A control section 2 connecting to an output of an invert buffer 1 controls drive capability in response to an output level of the invert buffer 1. With an input set to a GND level, a load capacitor 3 is charged up to a VDD level. When the input is set to a VDD level in this case, an NMOS5 is turned on to discharge the charge in the capacitor 3. When an output level reaches a threshold voltage of a NOR9 and a NAND 10, an NMOS7 is turned on to discharge the charge in the capacitor 3. That is, the discharge is not implemented at a stroke, but the charge is discharged at first by the NMOS5 only, and after the charge is discharged at the threshold voltage, the charge is discharged through the two NMOS TRs with the addition of the NMOS7. Thus, production of a transient current is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit device for a semiconductor integrated circuit, and more particularly to an output circuit device for suppressing the occurrence of undershoot and overshoot of output voltage.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing an output circuit device using a conventional CMOS invert buffer.

In FIG. 4, in consideration of the inductive load components (inductance components) of the output wiring, the power supply wiring and the ground, the output wiring inductance 16, the power supply wiring inductance 14 and the ground wiring inductance 15 are respectively considered.
It is shown as. The commonly connected drains of the P-MOS transistor 17 and the N-MOS transistor 18 to which a common input signal is applied to the gates are connected to one end of the load capacitance 3 whose other end is grounded through the output wiring inductance 16. It is connected, and one end of the load capacitance 3 is connected to the output terminal. The source of the P-MOS transistor 17 is connected to the power supply via the power supply wiring inductance 14, and the source of the N-MOS transistor 18 is grounded via the ground wiring inductance 15.

When the input signal is low level, P-MOS
The transistor 17 is turned on, the N-MOS transistor 18 is turned off, the load capacitance 3 is charged by the power supply, and the output signal becomes VDD level which is the power supply voltage.

When the input signal is at high level, the P-MOS
The transistor 17 is turned off, the N-MOS transistor 18 is turned on, the load capacitance 3 is discharged through the N-MOS transistor 18, and the output signal becomes the GND level which is the voltage at the ground point.

[0006]

In the conventional output circuit device using the CMOS invert buffer, the channel width of the MOS transistor is increased in order to invert the level of the output signal at a high speed in response to the inversion of the level of the input signal. Therefore, it is necessary to reduce the ON resistance and shorten the time required for charging and discharging the load capacitance 3. However, an LC resonance circuit is formed by the power supply wiring inductance 14, the output wiring inductance 16 and the load capacitance 3 when the load capacitance 3 is charged, and by the ground wiring inductance 15, the output wiring inductance 16 and the load capacitance 3 when discharging. , When the load capacitance 3 is charged and discharged according to the input signal shown in FIG. 5A and a large transient current flows,
Resonance occurs, and the output signal produces an undershoot 17 and an overshoot 18, as shown in FIG.

Conventionally, due to the undershoot and overshoot, the logic level in which the output circuit is erroneous is
There is a problem that it outputs to the circuit of the next stage, especially,
For example, in a circuit using a large signal current, such as a communication control device, undershoot and overshoot are amplified and disturb the signal, which may cause a malfunction of the device. Further, when the undershoot and the overshoot occur, the voltages of the ground point and the power source also change, which causes a problem that other circuits connected to the same ground point and the power source malfunction.

[0008]

According to the present invention, an invert buffer for inverting an input signal, a load capacitance connected to the output end of the invert buffer, and a common drain connected to the output end of the invert buffer. The P-channel MOS transistor and the N-channel MOS transistor are provided, and one of the MOS transistors is turned on in accordance with the output voltage to control the charging / discharging current of the load capacitance so as not to change abruptly. An output circuit device having a control circuit for controlling shoot / overshoot is obtained.

[0009]

The present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an invert buffer output circuit device showing a first embodiment of the present invention. P-MOS transistor 4 whose source is connected to the power supply of voltage VDD
And a common drain of the N-MOS transistor 5 whose source is grounded serve as an input terminal and an output terminal of the inversion buffer 1, respectively, and an input signal is applied to the input terminal of the inversion buffer 1. The output end of 1 is connected to one end of a load capacitance 3 whose other end is grounded, and one end of the load capacitance 3 is connected to an output terminal.

Further, the input end of the inverter 8 in the control unit 2 is connected to the output end of the invert buffer 1, and the output end of the inverter 8 is a 2-input NOR to which an input signal is commonly applied to the second input end. Gate 9 and 2 inputs N
The AND gates 10 are connected to their respective first input terminals. The output terminal of the 2-input NOR gate 9 is a P-MOS whose source is connected to a power source via an inverter 11.
A 2-input NAND gate 10 is connected to the gate of the transistor 6.
The output terminal of the is connected to the gate of the N-MOS transistor 7 whose source is grounded through the inverter 12. And P-MOS transistor 6 and N-
The common drain of the MOS transistors 7 serves as the output end of the control unit 2, and this output end is connected to the output end of the invert buffer 1.

Next, the operation will be described. As shown in FIG. 2A, when the input signal changes from the GND level, which is the voltage at the ground point, to the VDD level, which is the power supply voltage, the P-MOS transistor 4 changes from the ON state to the OFF state, N- The MOS transistor 5 is turned on from the off state
The charge that has changed to the state and accumulated in the load capacitance 3 up to the VDD level flows to the ground point via the N-MOS transistor 5, and the voltage of the output signal is as shown in FIG.
From the VDD level, it begins to fall gradually. The voltage of the output signal is the NOR gate 9 of the control unit 2.
When the threshold voltage Vt becomes smaller than the threshold voltage Vt of the NAND gate 10, the P-MOS transistor 6 becomes OFF, the N-MOS transistor 7 becomes ON, and the load capacitance 3 becomes the N-MOS transistor 5 and the N-MOS transistor. It will be discharged by 7 and FIG.
As shown in (b), the voltage of the output signal sharply decreases toward the GND level.

In this case, when the load capacitance 3 is discharged by the N-MOS transistors 5 and 7, the charge of the load capacitance 3 is already discharged by the N-MOS transistor 5 to the threshold voltage Vt level, so that the output voltage is Eventually, the transient current when approaching the GND level decreases, and the undershoot phenomenon can be suppressed.

Similarly, when the input signal changes from the VDD level to the GND level as shown in FIG. 2A, the load capacitance 3 first passes through the P-MOS transistor 4,
When the power supply starts to be charged, the output voltage becomes the threshold voltage Vt.
After the voltage exceeds the level, it is charged by the P-MOS transistor 4 and the P-MOS transistor 6, and the output voltage rapidly reaches the VDD level as shown in FIG. 2 (b). Also in this case, when the load capacitance 3 is charged by the P-MOS transistors 4 and 6, since the load capacitance 3 has already been charged by the P-MOS transistor 4 to the threshold voltage Vt level, it finally approaches the VDD level. At this time, the transient current is reduced and the overshoot phenomenon can be suppressed.

FIG. 3 is a circuit diagram of an invert buffer output circuit device showing a second embodiment of the present invention. The source is connected to the power supply of the voltage VDD, the P-MOS transistor 4 to which the first input signal is applied to the gate, and the N-MOS to which the source is grounded and the second input signal is applied to the gate
The drain common to the transistor 5 becomes the output end of the 3-state inversion buffer 13, and this output end is
The other end is connected to one end of the load capacitance 3 which is grounded, and one end of the load capacitance 3 is connected to the output terminal.

Further, the input end of the inverter 8 in the control unit 2 is connected to the output end of the invert buffer 1, and the output end of the inverter 8 has a second input end to which the first input signal is applied. It is connected to the first input terminal of a 2-input NAND gate 10 to which the second input signal is applied to the first input terminal and the second input terminal of the NOR gate 9. The output terminal of the 2-input NOR gate 9 is connected to the inverter 11
The gate of the P-MOS transistor 6 whose source is connected to the power source via the output terminal of the 2-input NAND gate 10 is connected via the inverter 12 to the source N grounded.
-The gates of the MOS transistors 7 are respectively connected. And P-MOS transistor 6 and N-MOS
The common drain of the transistor 7 is the control unit 2
, Which is connected to the output end of the 3-state inversion buffer 13.

The 3-state invert buffer 13 in this embodiment has two input terminals and outputs VD as an output.
It is an invert buffer that can take a high impedance state in addition to the D level and the GND level.

When the first input signal and the second input signal are the same, as can be seen from the configuration, the output signal is inverted corresponding to the inversion of the input signal by the same operation as in the first embodiment. It is possible to suppress undershoot and overshoot when performing.

When the first input signal is at VDD level and the second input signal is at GND level, the 3-state inversion buffer 13 operates in the P-MOS transistor 4 and NM.
The OS transistor 5 is turned off together with the high impedance state. At this time, in the control unit 2, regardless of the voltage of the output signal, the P-MOS transistor 6 and the N-MOS transistor 7 are provided together.
Since the F state and the high impedance state are set, the voltage of the output signal does not change and the high impedance state of the output terminal is maintained.

That is, even when the present invention is applied to an output circuit device using a three-state inversion buffer, it has an effect of suppressing undershoot and overshoot of the output voltage when the output signal changes, and outputs in a high impedance state. When it becomes, it has no effect on the output.

[0021]

As described above, according to the present invention, in the output circuit device, the drive capacity for charging / discharging with respect to the load capacity is controlled according to the output level, so that the magnitude of the transient current when the load capacity is charged / discharged. As a result, it is possible to suppress the occurrence of undershoot and overshoot of the output voltage, prevent erroneous transfer of output logic, and increase the stability of the power supply and ground level of the entire integrated circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an output circuit device that is a first embodiment of the present invention.

FIG. 2 (a) is an input signal voltage in the first embodiment,
(B) is the corresponding output signal voltage.

FIG. 3 is a circuit diagram of an output circuit device that is a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional output circuit device.

5A is an input signal voltage for a conventional output circuit device, and FIG. 5B is a corresponding output signal voltage.

[Explanation of symbols]

 1 Invert Buffer 2 Control Section 3 Load Capacitance 4, 6, 17 P-MOS Transistor 5, 7, 18 N-MOS Transistor 8, 11, 12 Inverter 9 NOR Gate 10 NAND Gate 13 3 State Invert Buffer 14 Power Supply Wiring Inductance 15 Ground Wiring inductance 16 Output wiring inductance

Claims (2)

[Claims] 1. An inversion buffer that performs an inverting operation of an input signal, a load capacitance connected to an output end of the inversion buffer, and an output end of the inversion buffer, and a charge / discharge current of the load capacitance is output to an output voltage. And an output circuit device having a control circuit for controlling according to. 2. The control circuit includes a P-channel MOS transistor having a common drain and an N-channel MO transistor.
S-transistor, the common drain is connected to the output end of the inversion buffer, and the P-channel MOS transistor or the N-channel MOS transistor is connected in accordance with the output voltage.
2. The output circuit device according to claim 1, wherein the channel MOS transistor is made conductive to suppress the occurrence of overshoot and undershoot of the output voltage.