JPH0865138A - Signal line driving circuit - Google Patents

Abstract

PURPOSE: To attain high speed signal delivery and to attain a high processing speed for an integrated circuit by controlling a voltage to drive a wire in the signal driving circuit used for a semiconductor integrated circuit. CONSTITUTION: A transistor(TR) T01 of the driving circuit 2 is turned on when inputs 1, 2 are at a low level and a TR T02 is turned off to set a potential of a signal line 1 to be a high potential VCC of a power supply so as to turn on a low potential load TR T04, then the amplitude is suppressed by a high potential depending on an on-resistance ratio of the T01, T04. In this case, a VREF 2 of a comparator circuit 4 is set to a slightly lower voltage by this potential. When the level of the inputs 1, 2 is transited to a high level from this state the T01 is turned off and the T02 is turned on to reduce the potential of the signal line 1. The potential of the signal line 1 is reduced cup to the VREF 1 of the comparator circuit 3 to set an output of the circuit 3 to be lower and then the high potential side load TR T03 is turned on. Thus, the amplitude is suppressed by the potential depending on the on-resistance of the T02, T03 with the high potential VCC in this way.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal line driving circuit used in a semiconductor integrated circuit or the like, and more particularly to a signal line driving circuit capable of speeding up the semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, high speed and large capacity have been achieved. In recent years, semiconductor integrated circuits,
In particular, the chip area tends to increase as the capacity of the semiconductor memory device (memory) increases. Along with this, the wiring length tends to increase, and the wiring capacity also increases. Therefore, if the signal line driving circuit has the same driving capability, the signal propagation time becomes longer, which is a problem in achieving higher speed.

When a long-distance wiring is driven up to the voltage amplitude of the power supply voltage by an ordinary CMOS inverter or the like, the signal delay time is determined by the wiring capacity, the drive capability of the drive circuit, the amplitude and the like. Therefore, a method of suppressing the voltage amplitude is used in order to shorten the signal delay time. For example,
In the MOS memory, in order to suppress the voltage amplitude, a technique using a wire pull-down drive transistor for transmitting a signal and a wire pull-up load transistor for suppressing the voltage amplitude has been mainly used.

FIG. 6 is a diagram showing a conventional circuit example.
(1) is an NMOS wiring pull-down drive transistor T0
1 shows an example in which the NMOS wiring pull-up load transistor T02 is combined, and (2) shows an example in which the NMOS wiring pull-down drive transistor T03 and the PMOS wiring pull-up load transistor T04 are combined.

[0005]

In the example of (1) of FIG. 6, the NMOS wiring pulldown drive transistor T0 is used.
When 1 is in the off state, the signal line potential (wiring precharge voltage level) is a value obtained by subtracting the threshold voltage Vth of the NMOS wiring pull-up load transistor T02 from the power supply voltage VCC, and the NMOS wiring pull-down drive transistor T01 is in the on state. At the time of, the signal line potential becomes the ground potential VSS. At the time when the NMOS wiring pull-down drive transistor T01 starts transition from the off state to the on state, the NMOS wiring pull-up load transistor T0
Since 2 is in the off state, when the NMOS wiring pull-down driving transistor T01 is turned on, the charge accumulated in the parasitic capacitance of the signal line flows to the ground line through the NMOS wiring pull-down driving transistor T01, and thus the initial stage of the pull-down operation. Then, the voltage changes rapidly. Conversely, N
When the MOS wiring pull-down drive transistor T01 starts the transition from the on state to the off state, the NMOS
The wiring pull-up load transistor T02 is in the ON state in the initial stage and rapidly raises the potential of the signal line.
Since the gate-source voltage VGS decreases and changes to the off state, the off state is reached midway and the pull-up operation is delayed.

In the case of (2) of FIG. 6, since the wiring pull-up load transistor is a PMOS, the wiring can be pulled up at a high speed, but when the NMOS wiring pull-down drive transistor T03 transits from the off state to the on state,
Wiring pull-up load transistor T04 at the start of transition
Is on, and the on resistance is very low. Therefore, even if the NMOS wiring pull-down drive transistor T03 is turned on, electric charges are supplied from the power supply line VCC, so that the potential of the signal line changes slowly and the pull-down operation is delayed.

Although the conventional technique using the wiring pull-down driving transistor and the wiring pull-up load transistor has been described above, the same problem occurs when the wiring pull-up driving transistor and the wiring pull-down load transistor are used. As described above, in the conventional circuit, the load transistor that pulls up or pulls down the wiring acts to suppress the voltage in the initial stage of the signal voltage propagation, or the driving capability of the load transistor decreases from the middle. Therefore, there is a problem that the speed cannot be sufficiently increased. The present invention solves such a problem, and an object thereof is to speed up signal propagation.

[0008]

FIG. 1 is a block diagram showing the principle of a signal line drive circuit according to the present invention. In FIG. 1, reference numeral T
01 and T02 are transistors that form the drive circuit 2 that drives the signal line 1 in accordance with the input 1 and the input 2. T
O3 is a high potential side load transistor that raises the low potential side of the potential change range of the signal line 1 by a predetermined amount above the low potential VSS of the power supply. T04 is a low potential side load transistor that lowers the high potential side of the potential change range of the signal line 1 by a predetermined amount from the high potential VCC of the power supply. 3 is the potential of the signal line 1 and the first
Of the reference voltage VREF1. When the potential of the signal line 1 is equal to or lower than the first reference voltage VREF1, the high-potential-side load transistor TO3 is turned on, and the potential of the signal line 1 is
Is a first comparison circuit that turns off the high-potential-side load transistor TO3 when the reference voltage VREF1 is higher than the reference voltage VREF1.
Reference numeral 4 compares the potential of the signal line 1 with the second reference voltage VREF2. When the potential of the signal line 1 is equal to or higher than the second reference voltage VREF2, the low potential side load transistor TO4 is turned on and the potential of the signal line 1 is changed. Is a second comparison circuit that turns off the low-potential-side load transistor TO4 when is less than or equal to the second reference voltage VREF2.

In FIG. 1, the high potential side load transistor T0
3 is a P-channel transistor, and the low potential side load transistor T04 is an N-channel transistor. Further, in FIG. 1, the first comparison circuit 3
Is a differential amplifier in which the first reference voltage VREF1 is input to one input, the other input is connected to the signal line 1, and the output is connected to the gate of the high potential side load transistor T03. Comparing circuit 4 of the
Reference voltage VREF2 is input, the other input is connected to the signal line 1, and the output is the low potential side load transistor T
04 is a differential amplifier connected to the gate.

[0010]

FIG. 2 is a diagram showing the potential fluctuation of each part in the circuit of FIG. 1, in which the inputs 1 and 2 and the nodes a and b of FIG.
The potential fluctuation of c is shown. When the potential of the signal line 1, that is, the potential of the node a is higher than the first reference voltage VREF1, the node b becomes the “high (H)” level and the high potential side load transistor TO3 is turned off. Similarly, when the potential of the node a is smaller than the second reference voltage VREF2,
The node c becomes "low (L)" level, and the low potential side load transistor TO4 is turned off.

When the inputs 1 and 2 are at the "low" level, T01 of the drive circuit 2 is in the on state and T02 is in the off state, and the potential of the signal line 1 is close to the high potential VCC of the power supply. , T04 are turned on, the potential of the signal line 1 becomes higher than the low potential VSS of the power source by a predetermined amount determined by the ON resistance ratio of T01 and T04, and the amplitude is suppressed. V
REF2 is set to be slightly lower than this potential.

From this state, when the inputs 1 and 2 transit to the "high" level, T01 is turned off, T02 is turned on, and the potential of the signal line 1 starts decreasing. Since the voltage starts to drop and immediately becomes VREF2 or less, T04 is turned off and the signal line is only connected to the low potential side VSS of the power supply through T02. Therefore, the potential of the signal line 1 is up to VREF1. Falls sharply.

When the potential of the signal line 1 drops to VREF1, the output of the differential amplifier 3 changes to the "low" level, the high potential side load transistor T03 is turned on, and the potential of the signal line 1 is equal to that of the power supply. The potential becomes lower than the high potential VCC by a predetermined amount determined by the ON resistance ratio of T02 and T03, and the voltage amplitude is suppressed. VREF1 is set to be slightly higher than this potential.

On the contrary, when the inputs 1 and 2 transit to "low" level from this state, T01 is turned on, T02 is turned off, and the potential of the signal line 1 starts to rise. As soon as it starts rising, it becomes VREF1 or higher, so T03
Turns off and the signal line is only connected to the high potential side VCC of the power supply via T01, so the potential of the signal line 1 rapidly rises to VREF2.

When the potential of the signal line 1 rises to VREF2, the output of the differential amplifier 4 changes to "high" level, the low potential side load transistor T04 is turned on, and the potential of the signal line 1 is the level of the power source. From the low potential VSS, the potential becomes a predetermined amount determined by the ON resistance ratio of T01 and T04, and the voltage amplitude is suppressed.

[0016]

FIG. 3 is a diagram showing a circuit configuration of a first embodiment of the present invention. 3 is a circuit in which the differential amplifier 3 is a PMOS current mirror load type NMOS differential amplifier circuit and the differential amplifier 4 is an NMOS current mirror load type PMOS differential amplifier circuit in the circuit of FIG. . PM
In the OS current mirror load type NMOS differential amplifier circuit, when the potential of the node a is lower than VREF1,
The transistor to which VREF1 is input is turned on, and the potential of the node b becomes “low”. When the potential of the node a is higher than VREF1, the transistor to which VREF1 is input is turned off, and the potential of the node b becomes “high”. NMOS current mirror load type PMOS
In the differential amplifier circuit, the potential of the node a is VREF2.
When it is lower, the transistor to which VREF2 is input is turned off, and the potential of the node c becomes “low”.
If the potential of the node a is higher than VREF2, VRE
The transistor to which F2 is input is turned on, and the potential of the node c becomes “high”.

FIG. 4 is a diagram showing the circuit configuration of the second embodiment of the present invention. The circuit of FIG. 4 differs from the circuit of the first embodiment of FIG. 3 in that the differential amplifier 4 is also a PMOS current mirror load type NMOS differential amplifier circuit. The operation is the same as in the first embodiment. In this case, depending on the voltage conditions of VREF1 and VREF, the MOS of the two differential amplifier circuits may be changed.
Responsiveness may be improved by using different types of transistors.

FIG. 5 is a diagram showing a circuit configuration of the third embodiment of the present invention. The circuit of FIG. 5 is a circuit using a comparison circuit in place of the differential amplifiers 3 and 4 in the circuit of FIG. 1 and an inverting amplifier having a different threshold voltage. The threshold voltage of this inverting amplifier can be changed mainly by changing the ratio of the channel widths of the PMOS transistor and the NMOS transistor. Therefore, the channel width ratio of the transistors of the respective inverting amplifiers is selected according to VREF1 and VREF2.

[0019]

As described above, according to the present invention,
Since the wiring can be driven at a high speed while suppressing the voltage amplitude, a signal line drive circuit capable of high-speed signal propagation can be realized, and the speed of the semiconductor integrated circuit can be increased.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention.

FIG. 2 is a diagram illustrating the principle of the present invention.

FIG. 3 is a circuit diagram of a first embodiment of the present invention.

FIG. 4 is a circuit diagram of a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a third embodiment of the present invention.

FIG. 6 is a diagram showing a conventional signal line drive circuit.

[Explanation of symbols]

 1 ... Signal line 2 ... Drive circuit 3 ... First comparison circuit 4 ... Second comparison circuit T03 ... High potential side load transistor T04 ... Low potential side load transistor

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H03K 19/017

Claims (6)

[Claims] 1. A drive circuit (2) for driving so as to change the potential of a signal line (1) according to a signal, and a low potential side of a potential change range of the signal line is a low potential (VSS) of a power supply. A high-potential-side load transistor (T03) that raises the potential by a predetermined amount, and a low-potential-side load transistor (T04) that lowers the high-potential side of the potential change range of the signal line from the high potential (VCC) of the power supply by a predetermined amount. The potential of the signal line is compared with a first reference voltage (VREF1), and when the potential of the signal line is equal to or lower than the first reference voltage, the high potential side load transistor (T03) is turned on, and the signal A first comparison circuit (3) that turns off the high-potential-side load transistor when the potential of the line is equal to or higher than the first reference voltage, and a potential of the signal line and a second reference voltage (VREF2). Compare the signal line When the potential is equal to or higher than the second reference voltage, the low potential side load transistor (T04) is turned on, and when the potential of the signal line is equal to or lower than the second reference voltage, the low potential side load transistor is turned off. And a second comparison circuit (4) for performing the signal line driving circuit. 2. The signal line drive circuit according to claim 1, wherein the high potential side load transistor is a P channel transistor, and the low potential side load transistor is an N channel transistor. 3. The first comparison circuit receives the first reference voltage at one input, the other input is connected to the signal line, and the output is at the gate of the high potential side load transistor. A second differential circuit connected to the signal line, the second reference voltage being input to one of the inputs, the other input being connected to the signal line, and the output being the low potential side load. The signal line drive circuit according to claim 1, wherein the signal line drive circuit is a differential amplifier connected to a gate of a transistor. 4. The signal line drive circuit according to claim 3, wherein the differential amplifiers of the first and second comparison circuits are PMOS current mirror load type NMOS differential amplifier circuits. 5. One of the differential amplifiers of the first and second comparison circuits is a PMOS current mirror load type NMOS differential amplifier circuit, and the other is an NMOS current mirror load type PMOS differential amplifier circuit. The signal line drive circuit according to claim 3, wherein 6. The signal line drive circuit according to claim 3, wherein the differential amplifiers of the first and second comparison circuits are CMOS inverters having different threshold values.