JP2001053599A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a leakage current control circuit capable of controlling a leakage current amount corresponding to an operation frequency. SOLUTION: This circuit is provided with first and second switch elements for limiting a leak current composed by being inserted in parallel with a power source path between a power source and a logic circuit 101. The first switch element PMA is on/off controlled by control signals and the second switch element PMB is on/off controlled by input signals inputted to the logic circuit. Switching control is performed so as to turn off the first switch element PMA and limit the leak current at the time of a standby operation or at low-speed operation mode and to turn OFF the first switch element PMA at the high-speed operation mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a leak current control circuit suitable for use in a standard cell type semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a logic circuit such as a CMOS semiconductor integrated circuit, for example, a CMOS inverter (higher power supply VD) is used.
(P-channel MOS transistor and N-channel MOS transistor connected between D and the lower power supply VSS, the gates are connected in common, an input signal is input, the drains are connected in common and connected to the output terminal). In addition, since one of the P-channel MOS transistor and the N-channel MOS transistor connected between the higher power supply VDD and the lower power supply VSS is in the off state, a DC current flows between the higher power supply VDD and the lower power supply VSS. There is no path, and a spike-like current (“through current”) flowing between the higher power supply VDD and the lower power supply VSS when both the P-channel MOS transistor and the N-channel MOS transistor are transiently turned on during the switching operation.
), In principle, a quiescent current flows between the higher power supply VDD and the lower power supply VSS.
Does not flow.

However, due to the reverse bias leakage current of the parasitic diode existing between the source / drain diffusion region of the MOS transistor and the well and the substrate, even in a stationary state (off state), power consumption occurs due to the leakage current.
This is called static power consumption (staticdissipation). Further, in addition to the reverse bias leakage current of the parasitic diode between the diffusion region and the substrate, the subthreshold conduction in the subthreshold region is also increased.
), an off current flows between the source and the drain of the MOS transistor.

[0004] That is, for example, an ideal input-output characteristic of the enhancement type MOS transistor (voltage-current characteristic), As is well known, the gate-source voltage V _GS is smaller cutoff than the threshold voltage V _TH In a region (also referred to as a “sub-threshold region”), the current I _DS flowing between the drain and the source is zero.

[0005] That is, in the cutoff region, the I _{DS =} 0 ... (1) non-saturation _{region, I DS = β [(V} GS -V TH) V DS -V DS 2/2] (0 <V DS <V the _GS -V _TH) ... (2) the saturation region is given by _{I DS = β (V GS -V} TH) 2/2 (0 <V GS -V TH <V DS) ... (3). Where I _DS is the drain-source current, V
_DS is the drain-source voltage, β = με / t _OX (W /
L) is a gain coefficient, μ is the effective mobility of carriers in the channel, ε is the dielectric constant of the gate insulating film, t _OX is the thickness of the gate insulating film, W is the channel width, and L is the channel length. .

[0006] In the above sub-shreshoulder region, M
No signal is applied to the gate of the OS transistor (or the gate voltage is less than the threshold), and the MOS transistor is turned off. However, the current I _DS flowing between the drain and the source does not become 0, and is small. , A predetermined off-state current (also called “sub-threshold current”) flows, which contributes to an increase in static power consumption when the MOS transistor is off. MOS in this sub-threshold region
It is known that the drain-source current I _DS of the transistor increases exponentially depending on the gate-source voltage V _GS and the drain-source voltage V _DS (for example, circuit simulation SPICE level 3). ).

[0007]

Recently, in semiconductor integrated circuit devices, the channel length of MOS transistors has been shortened with the reduction in device dimensions due to the progress of microfabrication technology, and the power supply voltage has been reduced. In order to cope with an increase in the operating speed, the threshold voltage (V _TH ) of the MOS transistor is lowered, and as a result, an increase in drain / source current flowing when the MOS transistor is turned off is a serious problem. In the present specification, in addition to the reverse bias leakage current of the parasitic diode between the diffusion region and the substrate, the so-called sub-threshold current flowing between the drain and source of the MOS transistor in the sub-threshold region,
The current flowing in the power supply path when the OS transistor is off is called “leakage current”.

When a high-speed MOS transistor having a low threshold value and a large leakage current is used to form a logic circuit in order to increase the operating frequency, the leakage current can be reduced even when the circuit is not operating and in a static state. Since current flows, it is difficult to reduce power consumption.

Then, such a high-speed logic circuit is
For example, when used in a battery-operated portable terminal device or the like, a leakage current flowing through a logic circuit during a standby operation in which the supply of a clock is stopped and a stationary state is set to a non-negligible current value. As a result, battery consumption can be increased. It is inconvenient.

Further, an increase in leakage current flowing when the MOS transistor is turned off causes an increase in noise level due to line impedance (wiring resistance) of a power supply line, a ground line, and the like. There is also a problem that the amplitude margin is reduced.

On the other hand, when a logic circuit is composed of MOS transistors having a small leakage current, for example, the threshold voltage of the MOS transistor is large, so that the switching time increases, the operation speed of the logic circuit becomes slow, and desired performance is obtained. Cannot be achieved.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and has as its object to provide a leakage current control circuit and a semiconductor integrated circuit which can control the amount of leakage current of a logic circuit according to an operating frequency. Is to provide.
Other objects, features, advantages, etc. of the present invention will be immediately apparent to those skilled in the art from the following description.

[0013]

A leak current control circuit according to the present invention for achieving the above object is inserted into a power supply path of a logic circuit or the like, and its activation and deactivation are controlled by a control signal. A current control unit is provided to activate the current control unit during a standby operation or a relatively low-speed operation of the circuit to limit a leak current of the circuit.

In the present invention, the current control unit is inserted in parallel in a power supply path between a power supply and a logic circuit.
At least first and second switch elements for limiting a leakage current are provided. The first switch element is on / off controlled by a control signal, and the second switch element is input to the logic circuit. When the logic circuit is at rest or operates at a relatively low speed, the first switch element is turned off to limit the leak current, and when the logic circuit is operated at a relatively high speed, the on / off control is performed. The switching control is performed so that the first switch element is turned on.

In the present invention, the above-described leak current control circuit may be provided for each gate circuit or each cell. Further, a logic circuit group in which the leak current is limited and a logic circuit group in which the leak current is not limited by the above-described leak current control circuit may be provided separately for each block constituting the semiconductor integrated circuit.

A semiconductor integrated circuit according to the present invention includes a plurality of low-leakage current type switch transistors connected in parallel between a power supply line and a power supply terminal of a logic circuit, and the logic circuit is constituted by high-speed transistors. A control signal is input to a control terminal of at least one of the plurality of switch transistors,
An input signal input to the logic circuit is input to a control terminal of another transistor of the plurality of switch transistors, and at the time of a standby operation or a low-speed operation mode, the at least one switch transistor is turned off to limit a leak current. In the high-speed operation mode, the at least one switch transistor is set to an on state.

[0017]

Embodiments of the present invention will be described. The present invention activates a leakage current control unit for limiting a leakage current during a standby operation for stopping supply of a clock or when a switching operation of a circuit may be delayed, so as to suppress current consumption of the entire circuit. It was done.

According to a preferred embodiment of the present invention, a plurality of low-leakage current type switch transistors having a small value of a leak current at the time of OFF and connected in parallel between a power supply line and a power supply terminal of a logic circuit are provided. The logic circuit includes a high-speed transistor having a relatively large off-state leakage current, and a control signal is input to at least one of the plurality of switch transistors. An input signal input to the logic circuit is input to the remaining transistors of the switch transistor so as to conform to the logic of the logic circuit.At the time of low-speed switching operation, the at least one switch transistor is turned off by a control signal. The at least one switch transistor during relatively high speed operation to limit leakage current. The turning on.

In one embodiment of the present invention having such a configuration, the operation is performed in a standby state in which the circuit operation is stopped by stopping the drive clock or the like, or the drive clock is operated at a low frequency (operating frequency) at a low speed. In low-speed operation, such as when high-speed switching is not required, or when low-speed switching is not required, the leakage current when the logic circuit capable of high-speed operation is turned off is narrowed by a low-leakage current type switch transistor, and the high-side power supply and low-side This prevents a large amount of leakage current from flowing between the power supplies. In addition, during high-speed operation in which the operating frequency is increased or high-speed switching operation is required, a low-leakage current type switch transistor is turned on to increase the current path between the logic circuits of the power supply and to speed up the switching operation. Switch to

According to a preferred embodiment of the present invention, there are provided a plurality of low-leakage current type low leakage current values between a high-level power supply (VDD) wiring and a high-level power supply terminal of a logic circuit. MOS transistors are connected in parallel, a gate of at least one of the MOS transistors receives a first control signal to be turned on / off, and a gate of another MOS transistor is inputted to the logic circuit. Input signal is input so as to match the logic of the logic circuit.

Further, a plurality of low-leakage current type MOS transistors having a small value of a leak current at the time of OFF are connected in parallel between a lower power supply (VSS) wiring and a lower power supply terminal of the logic circuit. The second control signal is input to the gate of at least one MOS transistor to be turned on / off, and the input signal input to the logic circuit is applied to the gate of the other MOS transistor to the logic of the logic circuit. It is configured to be input so as to match. The first
And the second control signal are complementary to each other.

And a standard cell (standard cell)
(Also referred to as "basic cells") in a cell library in a computer-aided design apparatus, and at the time of layout, a plurality of cells are appropriately arranged in a row along a row, and interconnects between the cells are interconnected to design. When the present invention is applied to a cell of a standard cell type semiconductor integrated circuit to be performed, the leakage current can be variably switched and controlled according to the operating frequency in one type of cell.

[0023]

Next, in order to explain the above-mentioned embodiment of the present invention in more detail, an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of the first embodiment of the present invention. Referring to FIG. 1, a circuit according to a first embodiment of the present invention includes first and second circuits each having a source commonly connected to a higher power supply VDD and a drain commonly connected to a higher power supply terminal of a logic circuit 101. The second P-channel MOS transistor PMB includes two P-channel MOS transistors PMA and PMB. A control signal is input to a gate of the second P-channel MOS transistor PMB to be turned on / off. An input terminal is provided to a gate of the first P-channel MOS transistor PMA. An input signal from IN is input. In FIG. 1, first and second P-channel MOs
The S transistors PMA and PMB constitute a leakage current control unit.

Each of the first and second P-channel MOS transistors PMA and PMB is a low-speed transistor having a small leak current value when turned off. That is, the first and second P-channel MOS transistors PMA and PMB have a higher threshold voltage and a longer channel length (the gain coefficient of the transistor is smaller than that of a P-channel MOS transistor (not shown) forming the logic circuit 101). ), The drain-source current in the subthreshold region (cutoff region) is set to a small value. On the other hand, the logic circuit 101 is of a high-speed type (low threshold,
(Short channel length).

In FIG. 1, for simplicity, the logic circuit 1
Although 01 is shown a configuration to which an input signal is one input, if the input signal is plural, each of the input signals IN ₁ to IN _n
P-channel MOS transistors PMA _{1 to} PMA _n (not shown) may be provided corresponding to (not shown).

When this circuit is operated at a high speed, that is, in a high-speed operation mode, the control signal is set to a low level and the second
P-channel MOS transistor PMB is turned on. In this case, first P-channel MOS transistor PMA having an input signal to logic circuit 101 as a gate input
Is turned on in response to the fall of the input signal from High to Low, the second P-channel MOS transistor PM set to the on state
B, the current flowing from the higher power supply VSS to the logic circuit 101 is reduced by the second P-channel MOS transistor PMB.
Increases in comparison with the case of the OFF state, and thus the switching operation can be sped up.

On the other hand, in the standby operation or the low-speed operation mode, the control signal is set to the high level to turn off the second P-channel MOS transistor PMB. That is, at the time of low-speed operation, the logic circuit 10 is turned off by turning off the second P-channel MOS transistor PMB.
In 1, the leakage current flowing when the power supply path is off is narrowed down by the second P-channel MOS transistor PMB. Also, a first P-channel MOS which is turned on / off by using an input signal to the logic circuit 101 as a gate input.
Since the leakage current of the transistor PMA when it is off is small, the leakage current flowing to the logic circuit 101 is limited.

Next, a second embodiment of the present invention will be described. FIG. 2 is a diagram showing the configuration of the second embodiment of the present invention. Referring to FIG. 2, the first and second N-channel MOs each having a source commonly connected to the lower power supply VSS and a drain commonly connected to the lower power supply terminal of the logic circuit 101 are shown.
A control signal is input to the gate of the second N-channel MOS transistor NMB to be turned on / off, and the first N-channel MOS transistor is provided.
An input signal from an input terminal IN is input to a gate of the transistor NMA.

The first and second N-channel MOS transistors NMA and NMB constituting the leak current control section
A low-speed transistor with a small off-state leakage current (high threshold voltage and long channel length) is used. That is,
First and second N-channel MOS transistors NMA, N
The MB has a higher threshold voltage and a longer channel length (a smaller transistor gain coefficient) than an N-channel MOS transistor (not shown) constituting the logic circuit 101,
The drain-source current in the subthreshold region (cutoff region) is set to a small value. On the other hand, logic circuit 1
Numeral 01 is composed of a transistor having a large leak current in order to increase the speed.

In the high-speed operation mode, the control signal is set to Hig.
the second N-channel MOS transistor N
The MB is turned on. In this case, when the first N-channel MOS transistor NMA having the gate input of the input signal to the logic circuit 101 is turned on when the input signal rises from a low level to a high level, it is set to the on state. Second N-channel MOS
With the transistor NMB, the current flowing from the logic circuit 101 to the low potential power supply VSS side increases as compared with the case where the second N-channel MOS transistor NMB is off, so that the switching operation can be sped up.

On the other hand, during the standby operation or the low-speed operation mode, the control signal is set to the low level to set the second N
The channel MOS transistor NMB is turned off.
That is, at the time of low-speed operation, the logic circuit 1 is turned off by turning off the second N-channel MOS transistor NMB.
Leakage current flowing through the power supply path when 01 is off is reduced by the second N-channel MOS transistor NMB. When the first N-channel MOS transistor NMA, which is controlled to be turned on / off using an input signal to the logic circuit 101 as a gate input, is off, the leakage current flowing through the logic circuit 101 is limited because the leakage current is small.

In FIG. 2, the first N channel M
The logic circuit 101 is connected to the gate of the OS transistor NMA.
The input signal from the input terminal IN is input based on the logical operation of, but if there are a plurality of input signals, the first N
A plurality of channel MOS transistors NMA are provided, and an input signal is input to each gate.

Next, a third embodiment of the present invention will be described. FIG. 3 is a diagram showing the configuration of the third exemplary embodiment of the present invention. Referring to FIG. 3, first and second P-channel MOs each having a source commonly connected to the higher power supply VDD and a drain commonly connected to the higher power supply terminal of the logic circuit 101.
S-transistors PMA and PMB, and first and second N-channel MOS transistors NMA and NMB whose sources are commonly connected to the lower power supply VSS and whose drains are commonly connected to the lower power supply terminal of the logic circuit 101 are provided. , Second
A signal obtained by inverting a control signal by an inverter INV is input to the gate of the P-channel MOS transistor PMB to be turned on / off, and the input signal from the input terminal IN is input to the gate of the first P-channel MOS transistor PMA. And the second N-channel MOS transistor NMB
A control signal is input to a gate of the first N-channel MOS transistor NMA, and an input signal from an input terminal IN is input to a gate of the first N-channel MOS transistor NMA. First and second P-channel MOS transistors PMA, PM
B and the first and second N-channel MOS transistors NMA and NMB constitute a leakage current control unit.

Also in this embodiment, first and second P-channel MOS transistors PMA and PMB, first and second P-channel MOS transistors
N-channel MOS transistors NMA and NMB are low-speed transistors with small leakage current when turned off, and logic circuit 101 is composed of high-speed transistors with large leakage current in order to increase the speed.

In the high-speed operation mode, the control signal is set to Hig.
As the h level, the second P-channel MOS transistor PMB and the second N-channel MOS transistor NM
B in the ON state, while in the standby operation or the low-speed operation mode, the control signal is set to the Low level,
Second P-channel MOS transistor PMB, second N
The channel MOS transistor NMB is turned off.
Note that an input signal from the input terminal IN is input to the gates of the first P-channel MOS transistor PMA and the first N-channel MOS transistor NMA based on the logic operation of the logic circuit 101, and there are a plurality of input signals. Has a plurality of first N-channel MOS transistors NMA, and receives an input signal of each gate.

FIGS. 4 to 6 are diagrams showing specific circuits according to the third embodiment of the present invention, respectively. As typical basic cells, an inverter circuit, a NAND circuit, an N
Each of the OR circuits is shown.

Referring to FIG. 4, in this inverter circuit, the gates are commonly connected and connected to an input terminal IN,
A P-channel MOS transistor PM1 having a drain connected in common and connected to the output terminal OUT and an N-channel MOS transistor NM1 constitute a CMOS inverter. The source is commonly connected to the higher power supply VDD, and the P-channel MOS transistor P-channel MOS transistors PMA and PMB in which the drain is commonly connected to the source of the transistor PM1, and an N-channel MOS in which the source is commonly connected to the lower power supply VSS and the drain is commonly connected to the source of the N-channel MOS transistor NM1
P-channel MO including transistors NMA and NMB
A signal obtained by inverting a control signal by an inverter INV is input to the gate of the S transistor PMB to perform on / off control. An input signal from the input terminal IN is input to the gate of the P-channel MOS transistor PMA.
A control signal is input to the gate of the OS transistor NMB to perform on / off control, and an input signal from the input terminal IN is input to the gate of the N-channel MOS transistor NMA.

The P-channel MOS transistor PM1 and the N-channel MOS transistor NM1 forming the CMOS inverter are transistors having a low threshold value and a relatively large leak current.

On the other hand, the P-channel MOS transistors PMA and PMB and the N-channel MOS transistors NMA and NMB which constitute the leak current control circuit are all smaller than the transistor having a small off-state leak current (high threshold or long channel length). Become.

In the standby operation or the low-speed operation mode, the control signal is set to the low level, and the P-channel M
OS transistor PMB and N-channel MOS transistor NMA are turned off, and the CMOS inverter
The P-channel MOS transistor PMA is connected to the higher power supply VDD, and the N-channel MOS transistor NMA is connected to the lower power supply VSS. The P-channel MOS transistor PMA and the N-channel MOS transistor NMA
Are low-speed transistors with low leakage current, the switching operation of the circuit is slow.
The leakage current of the OS inverter is limited.

In the high-speed operation mode, the control signal is High.
is set to the h level, and the P-channel MOS transistor PMB
And the N-channel MOS transistor NMA are turned on, and the CMOS inverter supplies the high-level power supply VDD with
The channel MOS transistor PMA and the ON-state P-channel MOS transistor PMB are connected in parallel, and an N-channel MOS transistor NMA is connected to the lower power supply VSS.
And an on-state N-channel MOS transistor NMB are connected in parallel, and the switching operation is faster than when the control signal is at the Low level (in the low-speed operation mode).

In FIG. 4, the leakage current control section includes one of a set of P-channel MOS transistors PMA and PMB on the higher power supply side and N-channel MOS transistors NMA and NMB on the lower power supply side. It may be configured.

FIG. 7 shows (1) a high-speed P-channel MOS transistor PM1 having a large leakage current and an N-channel MOS transistor PM1.
A high-speed CMOS inverter composed of the same type of transistors as the OS transistor NM1 (see FIG. 4); (2) a low-speed type composed of transistors of the same type as the P-channel MOS transistor PMA and the N-channel MOS transistor NMA of the low leakage current type (see FIG. 4) CMOS inverter,
(3) FIG. 4 is a voltage waveform diagram showing a circuit simulation result of switching characteristics (input / output transient characteristics) when an input rises for each of the inverters according to the embodiment of the present invention shown in FIG. The time and the vertical axis respectively represent the voltage.

In FIG. 7, (a) is the voltage waveform of the input signal to the inverter, (b) is the output voltage waveform of the high-speed CMOS inverter, (C) is the output voltage waveform of the low-speed CMOS inverter, and (d) is FIG. 4 is a diagram showing output voltage waveforms when the control signal is at the Low level and the P-channel MOS transistor PMB and the N-channel MOS transistor NMB are turned off in the inverter according to the embodiment of the present invention shown in FIG. It is.

As shown in FIG. 7D, in one embodiment of the present invention, a high-speed CMOS inverter (FIG. 7B)
(See FIG. 7C), but the fall speed is lower than that of the low-speed CMOS inverter (see FIG. 7C). The same can be said for the rising characteristics. Also, the waveform of FIG.
As compared with (b), it is smoother, and a lower noise characteristic can be obtained.

FIG. 8 shows (1) a high-speed P having a large leak current.
Channel MOS transistor PM1, N channel MOS
A high-speed CMOS inverter composed of the same type of transistor as the transistor NM1 (see FIG. 4); (2) a low-speed type composed of a transistor of the same type as the P-channel MOS transistor PMA and the N-channel MOS transistor NMA of low leakage current type (see FIG. 4) FIG. 4 is a current waveform diagram showing a result of circuit simulation of current characteristics at the time of switching of the CMOS inverter and (3) the inverter of the embodiment of the present invention shown in FIG. 4, in which the horizontal axis represents time and the left vertical axis represents input signal. Voltage on the voltage waveform, the right vertical axis is (1),
The currents are shown for the current waveforms of (2) and (3), respectively. Note that the circuit simulation described above is based on S
Transient analysis was performed using PICE and a transistor model taking into account the subthreshold current.

In FIG. 8, (a) is a waveform of an input signal voltage to the inverter, (b) is a current waveform at the time of switching of the high-speed CMOS inverter, (c) is a current waveform at the time of switching of the low-speed CMOS inverter, ( FIG. 4 d)
In the embodiment of the present invention shown in FIG.
is set to the h level, and the P-channel MOS transistor PMB
FIG. 10 is a diagram showing current waveforms at the time of switching when the N-channel MOS transistor NMA is turned on.

As shown in FIG. 8D, in one embodiment of the present invention, during switching, a high-speed CMOS inverter (see FIG. 8B) and a low-speed CMOS inverter (see FIG. 8C) Since the current value falls faster than this, it is possible to reduce current consumption.

In FIG. 8, the peak current value at the time of the switching of the current waveform of FIG.
The reason why the current value of the OS inverter is higher is that the inverter according to the embodiment of the present invention has two low-leakage transistors arranged in parallel between the source of the P-channel MOS transistor forming the CMOS inverter and the higher power supply VDD. Current-type P-channel MOS transistors PMA and PMB and CMOS
Two low-leakage current type N-channel MOS transistors NMA and NMB arranged in parallel between the source of the N-channel MOS transistor forming the inverter and the lower power supply VSS.
This is because during the switching operation, the switching currents of these transistors are added.

Next, a two-input NAND cell will be described. Referring to FIG. 5, this 2-input NAND cell has an N-channel MO having a gate connected to input terminals IN1 and IN2 and a source and a drain connected to each other.
S transistors NM1, NM2 and input terminals IN2, I
N-channel MOS transistor NM1 has a gate connected to N1, a drain connected in common, and a drain connected to output terminal OUT together with a drain of N-channel MOS transistor NM1.
The OS transistors PM1 and PM2 constitute a NAND circuit, the sources of which are commonly connected to the higher power supply VDD, and the drains of which are commonly connected to the common sources of the P-channel MOS transistors PM1 and PM2. PMB and lower power supply V
N-channel MOS transistors NMA and NMB have a source commonly connected to SS and a drain commonly connected to the source of N-channel MOS transistor NM2, and the control signal is inverted by the inverter INV at the gate of P-channel MOS transistor PMB. The input signals IN2, IN2 are supplied to the gates of the P-channel MOS transistors PMA1, PMA2.
1 are input, and the N-channel MO
A control signal is input to the gate of S transistor NMB to be turned on / off, and an input signal from input terminal IN2 is input to the gate of N channel MOS transistor NMA.

In this NAND cell, based on its logic (logic defined by the truth table), a low-leakage current type P-channel MOS transistor PMA1, PMA1 is connected to the higher power supply VDD side in accordance with two input signals. Two PMAs 2 are provided, and the P-channel MOS transistor PMB is also a transistor having a low leakage current. Low side power supply VS
N-channel MOS transistor N inserted on S side
MA and NMB are also of low leakage current type. Note that N
The input signal IN1 may be input to the gate of the channel MOS transistor NMA.

When the control signal is at the low level, the input signal voltages supplied to the input terminals IN1 and IN2 are both Hi.
When the output terminal OUT is at the gh level, the N-channel MOS transistors NM1, NM2, NM
A is discharged by the current path to the lower power supply VSS through the output terminal A, the output terminal voltage becomes Low level, and the input terminal IN
When one or both of IN1 and IN2 are at the Low level, the output terminal OUT is charged from the higher power supply VDD through the P-channel MOS transistor that is turned on, and High.
h level.

When the control signal is at the high level, the input signal voltages supplied to the input terminals IN1 and IN2 are both high.
When at the high level, the output terminal OUT is connected to the N-channel MOS transistors NM1 and NM2 which are turned on,
N-channel MOS transistors NMA connected in parallel,
NMB is discharged through the current path to the lower power supply VSS, and one or both of the input terminals IN1 and IN2 are set to L level.
When the output terminal OUT is at the low level, the output terminal OUT is connected to the P-channel MO.
One of the S transistors PM1 and PM2 which is turned on, and the P channel MOS transistors PMA1 and PMA
The transistor MA2 is charged from the higher power supply VDD through the transistor that is turned on and the P-channel MOS transistor PMB that is turned on, and goes high.

Next, a two-input NOR cell will be described.
Referring to FIG. 6, this two-input NOR cell has an N-channel MOS transistor NM having gates connected to input terminals IN1 and IN2 and a drain connected in common.
1, NM2 and P-channel MOS transistors PM1 and PM2 whose gates are connected to the input terminals IN2 and IN1, respectively, and whose sources and drains are commonly connected. The drain of the P-channel MOS transistor PM2 and the N-channel MOS The commonly connected drains of the transistors NM1 and NM2 are commonly connected to the output terminal OUT, the drain is connected to the commonly connected sources of the N-channel MOS transistors NM1 and NM2, the source is connected to the lower power supply VSS, and the gate is Input terminals IN2, I
N-channel MOS transistor N connected to N1
MA1, NMA2 and N-channel MOS transistor N
An M-channel MOS transistor NMB having a drain connected to the source of M2, a source connected to the lower power supply VSS, and a control signal input to the gate.

According to the logic of the NOR circuit (logic defined by the truth table), a low-leakage current type N-channel MO is provided on the lower power supply side in correspondence with the input terminals IN1 and IN2.
It has two S transistors NMA1 and NMA2,
The N-channel MOS transistor NMB having the gate input of the control signal is also a transistor having a low leakage current. Further, both the P-channel MOS transistors PMA and PMB inserted on the higher power supply side are of a low leakage current type. Note that the input signal IN1 may be input to the gate of the P-channel MOS transistor PMA.

When both the input terminals IN1 and IN2 are at the low level, the output terminal OUT is charged to the high level by the current path from the higher power supply VDD to the output terminal OUT, and one or both of the input terminals IN1 and IN2 are at the high level. At the time of the level, the output terminal OUT is at the low level.

Each cell described with reference to FIGS. 4 to 6 is registered as a standard cell (also referred to as "primitive cell") in a library used for designing a standard cell type semiconductor integrated circuit. At the time of layout, a plurality of cells are arranged in a row in a row based on circuit connection information. That is, a basic logic circuit serving as a logic function of a primitive cell is arranged between a high-potential power supply (VDD) wiring pattern and a low-potential power supply (VSS) wiring pattern. The layout is performed by making contacts, inter-cell wiring connections for connecting the cells, and the like. Note that, in the present invention, the basic cell is applied to another logic circuit, that is, a sequential circuit such as an exclusive OR circuit, a latch circuit, and a flip-flop, based on the same principle as the configuration shown in FIGS. Clearly, it is possible.

In the present invention, a control signal for controlling on / off of a P-channel MOS transistor and an N-channel MOS transistor constituting a leakage current control unit is as follows.
The power may be supplied from an external terminal of the semiconductor integrated circuit.

Alternatively, a signal obtained by encoding a plurality of control signals is input from an external terminal, and a high-speed operation and a low-speed operation (low leakage current) are performed for each circuit block including a plurality of logic circuits constituting a semiconductor integrated circuit. Thus, a control signal to the leak current control unit may be set. Furthermore, for each circuit block, the signal wiring may be connected to the VDD or VSS line in advance at the time of designing inside the semiconductor chip.

Alternatively, in a CPU or the like in a semiconductor chip, a value of a control signal to a leak current control unit provided in each logic circuit of each circuit block may be dynamically set during a standby operation. Good.

For a circuit block including a logic circuit having a leakage current control circuit according to the present invention, a low leakage current mode is set for a circuit block that does not require high-speed operation, such as a logic circuit that holds and outputs a fixed value. Alternatively, activation and deactivation of the leak current control circuit may be selectively set for each circuit block, for example, by setting a high-speed operation mode for a circuit block that requires a high-speed switching operation. In a semiconductor integrated circuit, activation and deactivation of a plurality of leak current control circuits may be controlled collectively by a common control signal.

[0063]

As described above, according to the present invention,
The following effects are obtained.

The first effect of the present invention is that the switching between the activation and the deactivation of the leakage current control unit is controlled, so that the standby operation mode or the low-speed operation mode is selected according to the operating frequency or the switching operation speed. Sometimes low leakage current operation to reduce current consumption,
In the high-speed operation mode, high-speed switching operation is enabled.

A second effect of the present invention is that one semiconductor integrated circuit product can be controlled to be switched to a high-speed operation type or a low leakage current type according to a required operating frequency and current consumption. That is.

The third effect of the present invention is that a high-speed operation type and a low-leakage current type are provided for each circuit block in the semiconductor integrated circuit in accordance with the performance requirements such as the function, operating frequency, and current consumption of the circuit block. That is, they can be set individually, and the operating frequency and the current consumption can be adjusted. A fourth effect is that noise is less generated during low-speed operation because the waveform is gentler than when the high-speed CMOS inverter is operated at low speed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of an inverter as an example of a basic cell forming a third embodiment of the present invention.

FIG. 5 is a diagram illustrating a configuration of a NAND circuit as an example of a basic cell according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a NOR circuit as an example of a basic cell forming a third embodiment of the present invention.

FIG. 7 is a voltage waveform diagram showing switching characteristics (input / output characteristics) of an inverter according to a third embodiment of the present invention in comparison with a conventional circuit.

FIG. 8 is a current waveform diagram showing current characteristics at the time of switching of an inverter according to a third embodiment of the present invention, as compared with a conventional circuit.

[Explanation of symbols]

101 Logic circuit IN input terminal NM1, NM2, NMA, NMA1, NMA2, NMB
N-channel MOS transistor OUT output terminal PM1, PM2, PMA, PMA1, NPMA2, PM
BP channel MOS transistor

Claims (15)

[Claims] A current control unit which is inserted into a power supply path of a circuit and whose switching between activation and deactivation is controlled by a control signal; A leak current control circuit characterized in that when operating, the current control unit is activated to limit a leak current of the circuit. 2. The circuit according to claim 1, wherein said circuit comprises a logic circuit, and said current control unit is connected in parallel to a power supply path between a power supply and said logic circuit, and is configured to limit a leakage current. The first switch element is on / off controlled by a control signal, and the second switch element is on / off controlled by an input signal input to the logic circuit. When the logic circuit is in a standby operation or when the logic circuit is operated at a low speed, the first switch element is turned off to limit a leak current. When the logic circuit is operated at a relatively high speed, the first switch element is turned off. 2. The leak current control circuit according to claim 1, wherein a switching control is performed so as to be turned on. 3. A semiconductor device comprising at least first and second switch elements inserted in parallel in a power supply path between a power supply and a logic circuit for limiting a leakage current, wherein the first switch element comprises: The second switch element is on / off controlled by a control signal, and the second switch element is on / off controlled by an input signal input to the logic circuit, and turns off the first switch element during a standby operation or a low-speed operation mode. A leakage current control circuit configured to control switching so as to turn on the first switch element in a high-speed operation mode in a gate circuit or a cell unit. Semiconductor integrated circuit. 4. A semiconductor integrated circuit including a plurality of circuit blocks each comprising a logic circuit group, wherein each of the logic circuit groups includes the leakage current control circuit according to claim 3, wherein a leakage current is limited by the leakage current control circuit. A logic circuit group provided with each of the leak current control circuits, wherein a leak current is not limited by the leak current control circuit, provided separately for each circuit block to which the logic circuit group belongs; circuit. 5. A logic circuit group whose leak current is limited by said leak current control circuit according to claim 3, wherein said leak current is collectively controlled by a common control signal in a semiconductor integrated circuit including said logic circuit group. Control the control circuit,
A semiconductor integrated circuit characterized by the above. 6. A logic circuit comprising: a plurality of low-leakage current type switch transistors connected in parallel with each other between a power supply line and a power supply terminal of a logic circuit; A control signal is input to a control terminal of at least one of the switch transistors, and an input signal input to the logic circuit is input to control terminals of other transistors of the plurality of switch transistors. Alternatively, in a low-speed operation mode, the at least one switch transistor is turned off to limit a leak current, and in a high-speed operation mode, the at least one switch transistor is set to an on state. 7. A plurality of low-leakage current type MOS transistors are connected in parallel between a higher power supply wiring and a higher power supply terminal of a logic circuit, and at least one of the MOS transistors has a gate connected to a control signal. And an on / off control is performed, and an input signal input to the logic circuit is input to the gate of another MOS transistor in accordance with the logic of the logic circuit. . 8. A plurality of low-leakage current type MOS transistors are connected in parallel between the lower power supply line and the lower power supply terminal of the logic circuit, and at least one of the MOS transistors has a gate connected to a control signal. And an on / off control is performed, and an input signal input to the logic circuit is input to the gate of another MOS transistor in accordance with the logic of the logic circuit. . 9. A low-leakage current type first group of MOS transistors is connected in parallel between a higher power supply line and a higher power supply terminal of a logic circuit.
A first control signal is input to the gate of the transistor to be turned on / off, and an input signal input to the logic circuit is input to the gate of another MOS transistor in accordance with the logic of the logic circuit. A second group of low-leakage current type MOS transistors is connected in parallel between a power supply line on the lower side and a lower power supply terminal of the logic circuit, and at least one of the MOS transistors has a gate connected to the first control transistor. A second control signal complementary to the signal is input and on / off controlled, and an input signal input to the logic circuit is input to the gate of the other MOS transistor in accordance with the logic of the logic circuit;
A semiconductor integrated circuit device characterized by the above-mentioned. 10. A standard cell of a standard cell type semiconductor integrated circuit in which cells including a basic logic circuit are arranged and wired in a predetermined row, wherein a standard power supply wiring is connected to a high power supply terminal of the basic logic circuit. Multiple low leakage current type MOs connected in parallel between
S transistor, at least one of which MOS
A control signal is input to the gate of the transistor to turn it on.
A standard cell which is turned off and has an input signal input to the basic logic circuit in accordance with the logic of the basic logic circuit, applied to a gate of another MOS transistor. 11. A standard cell of a standard cell type semiconductor integrated circuit in which cells including a basic logic circuit are arranged and wired in a predetermined row, wherein a standard power supply line is connected to a low power supply terminal of the basic logic circuit. Multiple low leakage current type MOs connected in parallel between
S transistor, at least one of which MOS
A control signal is input to the gate of the transistor to turn it on.
A standard cell which is turned off and has an input signal input to the basic logic circuit in accordance with the logic of the basic logic circuit, applied to a gate of another MOS transistor. 12. A standard cell of a standard cell type semiconductor integrated circuit for arranging and wiring cells including a basic logic circuit in a predetermined row, wherein a standard cell is provided between a higher power supply wiring and a higher power supply terminal of the logic circuit. Low-current type first group of MOSs connected in parallel to
A first control signal is input to a gate of at least one of the MOS transistors to be turned on / off, and a gate of the other MOS transistor is connected to the basic logic circuit in accordance with the logic of the basic logic circuit. An input signal to be input to the circuit is input, and a second group of low-leakage current type Ms connected in parallel between a lower power supply line and a lower power supply terminal of the basic logic circuit.
OS transistor, and at least one of these
A second control signal complementary to the first control signal is input to the gate of the S transistor and on / off controlled, and the gates of the other MOS transistors have the basic logic in accordance with the logic of the basic logic circuit. A standard cell comprising an input signal input to a circuit. 13. An inverter cell included in a cell library of a standard cell type semiconductor integrated circuit, comprising: a first P-channel MOS transistor having a gate commonly connected to an input terminal and a drain commonly connected to an output terminal; A first N-channel MOS transistor, a source commonly connected to a higher power supply terminal, a drain commonly connected to a source of the first P-channel MOS transistor, and a gate for receiving an input signal and a control signal from the input terminal. Low-leakage current type second and third P-channel MOS transistors each receiving a complementary signal, a source commonly connected to the lower power supply terminal, and a drain common to the source of the first N-channel MOS transistor Connected to the input signal and the control signal. Inverter cell, characterized by comprising second current type, and a third N-channel MOS transistor. 14. A two-input NAND cell included in a cell library of a standard cell type semiconductor integrated circuit, wherein first and second input signals from first and second input terminals are input to a gate, respectively. A low-leakage current type in which the drain is commonly connected to the commonly connected sources of the first and second P-channel MOS transistors each having the drain commonly connected to the output terminal, and the source is commonly connected to the higher power supply terminal. A third to a fifth P-channel MOS transistor, wherein the gates of the third and fourth P-channel MOS transistors receive the first and second input signals, respectively, and the fifth P-channel MOS transistor A complementary signal of a control signal is input to a gate of the transistor, the first input signal is input to a gate, and a drain is connected to the output terminal. A first N-channel MOS transistor, a second N-channel MOS transistor having a gate to which the second input signal is input, and a drain connected to the source of the first N-channel MOS transistor; The third and fourth N-channel MOS transistors are commonly connected to the source, the sources are commonly connected between the lower power supplies, and the gates receive the second input signal and the control signal, respectively. And a channel MOS transistor.
D cell. 15. A two-input NOR cell included in a cell library of a standard cell type semiconductor integrated circuit, wherein a gate receives a first input signal from a first input terminal and a drain is connected to an output terminal. A second P-channel MOS transistor having a gate connected to a second input signal from a second input terminal and a drain connected to a source of the first P-channel MOS transistor A low-leakage current type third and fourth P-channel MOS transistor having a source commonly connected to the higher power supply terminal and a drain commonly connected to the source of the second P-channel MOS transistor; The gates of the third and fourth P-channel MOS transistors receive the second input signal and the complementary signal of the control signal. The first and second input signals are input to the output terminal, respectively, and the first and second input signals are respectively input to the gate.
And a third to fifth N-channel MOS transistors each having a drain commonly connected to a connection point of sources of the first and second N-channel MOS transistors, and a source commonly connected to a lower power supply terminal.
An OS transistor; gates of the third and fourth N-channel MOS transistors receive the first and second input signals, respectively;
A control signal is input to a gate of the fifth N-channel MOS transistor, and a two-input NOR gate is provided.
cell.