JPH11340806A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily conduct an IddQ test or the like for discriminating a standby current by decreasing the voltage applied to a gate oxide film of a MOSFET in a standby state. SOLUTION: An N-channel MOSFETN51, whose gate potential VP is selected to be a 1st potential with an absolute value higher than a power supply voltage VCC in a normal operation and is selected to be a 2nd potential, the same potential as the power supply voltage VCC or with a smaller absolute value than the power supply voltage VCC in a standby state, is provided between a point of the power supply voltage VCC and a source of a P-channel MOSFETP1 which is the component of a CMOS logic gate of a logic circuit section LC, and the P-channel MOSFETP51 whose gate potential VM is selected to be a 3rd potential that is a negative potential lower than a ground potential VSS in a normal operation and selected to be a 4th potential, that is the same as the ground potential VSS or slightly higher than the ground potential VSS in a standby state is provided between the point of the ground potential VSS and a source of the N-channel MOSFETN1 which the component of the CMOS logic gate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, for example, a single chip microcomputer including a logic circuit having a CMOS logic gate as a basic element and the like, and is particularly effective when used for high speed and low power consumption. Technology.

[0002]

2. Description of the Related Art P-channel and N-channel MOSFs
A so-called CMOS (complementary MOS) logic gate in which an ET (metal oxide semiconductor type field effect transistor; in this specification, a MOSFET is used as a generic term for an insulated gate field effect transistor) is used as its basic element. There is a semiconductor integrated circuit device such as a single-chip microcomputer (hereinafter simply referred to as a microcomputer) including such a logic circuit.

On the other hand, in recent years, the technology for miniaturization and high integration of semiconductor integrated circuits has been remarkably advanced, and microcomputers and the like have also benefited from the technology and are on a large scale. Further, in order to prevent breakdown voltage breakdown of elements due to miniaturization of semiconductor integrated circuits and to reduce power consumption of large-scale microcomputers and the like, the operating power supply has been reduced in voltage, for example, + 3.3V. Microcomputers and the like that use a power supply voltage VCC having a small absolute value such as (volts) or +2.5 V as an operation power supply are being developed. However, miniaturization of semiconductor integrated circuits is not
Does not contribute to the lowering of the threshold voltage, and the lowering of the operating power supply, on the other hand, lowers the operating current of the MOSFET and hinders high-speed operation of a microcomputer or the like.

To cope with this, there is a method of reducing the threshold voltage of the MOSFET to ensure high-speed operation of the CMOS logic gate. However, when the threshold voltage of the MOSFET is reduced, for example, during standby (about 32 KHz). The leakage current of the CMOS logic gate during a low-speed operation or a standby mode increases, and the power consumption during standby of a microcomputer or the like increases. Therefore,
In recent microcomputers and the like, the MO
The substrate voltage of the SFET is made shallow, its threshold voltage is made small, and high-speed operation is prioritized. During standby, that is, in the standby mode, the substrate voltage of the MOSFET is made deep and its threshold voltage is made large, thereby reducing power consumption. So-called VT (Variable Threshold-vol)
stage) or a so-called MT (Multi-Thres) in which a MOSFET having a large threshold voltage is provided in a power supply path of a CMOS logic gate and operation power is supplied to the CMOS logic gate via the MOSFET during standby.
hold) system is increasing.

The VT method and the MT method are described in, for example, “Nikkei Micro Devices”, August 1996, No. 5
It is described on page 0 to page 66.

[0006]

However, when the above-mentioned VT method is employed, a relatively large-scale substrate voltage generating circuit is required, the required number of elements such as microcomputers increases, and the substrate voltage becomes deep during standby. Being done
The power consumption of the substrate voltage generation circuit during standby cannot be ignored, and the power consumption of the microcomputer or the like during standby cannot be reduced as desired. Further, for example, in order to reduce the threshold voltage of the N-channel MOSFET to about 0.1 V to 0.5 V at which sufficient reduction in power consumption is expected, it is necessary to set the substrate voltage to about -3.3 V. However, in this case, VCC is applied to the gate oxide film of the MOSFET.
+ 3.3V is applied, which causes the MOSFE
T withstand voltage breakdown is caused, and the reliability of the microcomputer or the like is reduced.

On the other hand, when the above-mentioned MT method is adopted, the MOSFET having a high threshold voltage is turned off during standby, so that data retention at each internal node is required. And the number of required elements increase. In addition, each MOSFE
In consideration of the element destruction of T, a so-called IddQ test for determining a standby current performed by applying a power supply voltage having a relatively large absolute value becomes difficult, and the reliability of a microcomputer or the like decreases.

An object of the present invention is to provide a microcomputer or the like which suppresses an increase in the number of required elements and reduces power consumption during low-speed operation or standby. Another object of the present invention is to reduce the voltage applied to the gate oxide film of the MOSFET at the time of standby so that an IddQ test or the like for determining the standby current can be easily performed, thereby improving the reliability of the microcomputer and the like. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a semiconductor integrated circuit device such as a microcomputer using a CMOS logic gate as a basic element, the gate potential between the source of the P-channel type first MOSFET constituting the CMOS logic gate and the power supply voltage VCC is: Power supply voltage VCC during normal operation
An N-channel type second MOS having a first potential having a larger absolute value and having the same potential as the power supply voltage VCC or a second potential having a smaller absolute value than the power supply voltage VCC during standby.
An FET is provided, and a negative third potential whose gate potential is lower than the ground potential VSS during normal operation is provided between the source of the N-channel type third MOSFET constituting the CMOS logic gate and the ground potential VSS. In a standby state, a P-channel type fourth MO which is set to the same potential as the ground potential VSS or a fourth potential slightly higher than the ground potential VSS is provided.
An SFET is provided. Also, first and third MOSFETs
During normal operation, the source potential or the power supply voltage VCC or the ground potential VSS of each MOSFET is supplied to the substrate portion, and during standby, the power supply voltage VCC or the ground potential VSS is supplied.
Respectively.

According to the above-mentioned means, during normal operation, the power supply voltage VCC and the ground potential VSS are used as they are without being affected by the threshold voltage of the second or fourth MOSFET. Supplied as
Alternatively, an externally supplied power supply voltage VCC or ground potential V
A relatively stable operation power supply which is not affected by the SS potential fluctuation is supplied as the operation power supply of the CMOS logic gate, and its absolute value is reduced by the threshold voltage of the P-channel or N-channel MOSFET during standby. The power supply voltage VCC and the ground potential VSS can be supplied as operation power of the CMOS logic gate, and the first and third MOs can be supplied during standby without applying a very deep substrate voltage.
A leak current can be reduced by setting a reverse bias state between the source and the substrate of the SFET. As a result, it is possible to reduce the power consumption during standby of the microcomputer or the like, and to improve its reliability.

[0012]

FIG. 1 is a block diagram showing an embodiment of a microcomputer (semiconductor integrated circuit device) to which the present invention is applied. First, an outline of the configuration and operation of the microcomputer of this embodiment will be described with reference to FIG. The microcomputer of this embodiment uses a CMOS logic gate as a basic element, and a circuit element constituting each block of FIG. It is formed on the substrate surface.

In FIG. 1, the microcomputer of this embodiment is not particularly limited, but a central processing unit CPU of a stored program type and a clock generation circuit CPG
And a direct memory access controller DMA coupled to the central processing unit CPU via an internal bus IBUS
C, a read only memory ROM, a random access memory RAM, and a bus controller BSC.
The bus controller BSC is further coupled to an internal bus PBUS. The internal bus PBUS further includes a timer circuit TIM, a serial communication interface SCI, and nine input / output ports IOP1.
ＩIOP9 are combined. I / O ports IOP1-IO
P5 is further coupled to an internal bus IBUS.

The microcomputer has an external terminal VC.
A power supply voltage V serving as an operation power supply through C and VSS
CC and ground potential VSS are supplied, respectively. Also,
The central processing unit CPU of the microcomputer is supplied with the mode control signal MODE, the standby signal STBY and the reset signal RES via the external terminals MODE, STBY and RES, respectively. The clock generating circuit CPG is supplied with the external terminals XTAL and EXTAL. A predetermined clock signal is supplied through the terminal. The microcomputer further includes a power supply control unit VC that receives the power supply voltage VCC and generates various internal voltages (not shown).
The specific configuration and operation of the power control unit VC and related circuits will be described later in detail.

In this embodiment, in the microcomputer, the operating power supply has been reduced in voltage, and the power supply voltage VCC has been reduced.
Is a positive potential having a relatively small absolute value such as + 3.3V. Needless to say, the ground potential VSS is set to 0V.

The clock generation circuit CPG has an external terminal XT
An internal clock signal having a predetermined number of phases is generated based on the clock signal supplied via the AL and EXTAL, and supplied to each unit of the microcomputer. The central processing unit CPU is step-controlled in accordance with a program stored in advance in a read-only memory ROM, performs predetermined arithmetic processing, and controls and controls each unit of the microcomputer. The central processing unit CPU further includes:
The operation mode of the microcomputer is selectively set according to the mode control signal MODE, the standby signal STBY or the reset signal RES, or the microcomputer is selectively set to a standby state, that is, a standby state.
Alternatively, it is selectively reset to an initial state.

On the other hand, the direct memory access controller DMAC assists, for example, direct and continuous data transfer between the central processing unit CPU and the read only memory ROM, the random access memory RAM, or the input / output ports IOP1 to IOP5. . The read-only memory ROM is composed of a nonvolatile semiconductor memory such as a mask ROM or a flash memory, and has a central processing unit C.
Stores programs, fixed data, and the like necessary for the step operation of the PU. Furthermore, random access memory RAM
Is composed of a volatile semiconductor memory such as a static RAM, for example, and stores calculation results and control data by the central processing unit CPU.

Next, the timer circuit TIM performs time management in accordance with the clock signal supplied from the clock generation circuit CPG, and provides it to interrupt processing of the central processing unit CPU. The serial communication interface SCI is connected to an external input / output device and a central processing unit CPU or a random access memory RA of a microcomputer.
M supports high-speed serial data transfer to and from the internal buses IBUS and PBU.
Supervises and controls bus access to S. Further, the input / output ports IOP1 to IOP9 function as interface devices for assisting transmission and reception of signals with various input / output devices provided outside.

In this embodiment, each section of the microcomputer is constituted by CMOS logic gates as basic elements, except for blocks formed as modules such as a read only memory ROM and a random access memory RAM. The constituent P-channel and N-channel MOSFETs are designed to have a relatively small threshold voltage in order to ensure a high-speed operation.

As described above, the microcomputer of this embodiment is selectively put in the standby state by setting the standby signal STBY to the valid level, and the power consumption in the standby state is set to an extremely small value. However, since the CMOS logic gate, which is the basic element, is composed of a low threshold voltage MOSFET,
The sub-threshold current, that is, the leakage current of the OSFET increases, which increases the power consumption of the microcomputer during standby. In order to deal with this, the microcomputer of this embodiment uses a CM
A power supply controller VC is provided for selectively switching the source of the P-channel or N-channel MOSFET constituting the OS logic gate and the potential of the substrate to reduce the leakage current during standby. This will be described later in detail. Will be described.

FIG. 2 shows a power control unit VC1 included in the microcomputer of FIG. 1 (here, the power control unit shown as VC in FIG. 1 is shown with an additional number in order to be classified according to each embodiment. The same applies to the following) and a circuit diagram of a first embodiment of the logic circuit section LC. FIG. 3 shows a signal waveform diagram of the first embodiment. Based on these figures, a power supply controller VC1 included in the microcomputer of this embodiment
The specific configuration and operation of the logic circuit unit LC and the features thereof will be described. Note that the logic circuit section LC comprehensively refers to the central processing unit CPU, the clock generation circuit CPG, the direct memory access controller DMAC, and the like, which are configured using CMOS logic gates as basic elements instead of modules. Shows only an inverter V1 which is only a part of the CMOS logic gates constituting the logic circuit portion LC. In the following circuit diagrams, MOSFs whose gates are marked with circles
ET is a P-channel type (first conductivity type) N-channel type (second conductivity type) MOSFET without a circle mark
Are shown separately from

In FIG. 2, the logic circuit portion LC of the microcomputer of this embodiment is, as described above, a CMOS circuit.
These CMOS devices are configured using logic gates as basic elements.
The logic gate is a P-channel MOSFET P1 (first MOSFET) whose drain and gate are commonly coupled as represented by the inverter V1 in the figure.
And N-channel MOSFET N1 (third MOSFET
T). The source of the MOSFET P1 serving as the high-potential power supply node of the inverter V1 is coupled to the internal voltage supply line VCLP, and the source of the MOSFET N1 serving as the low-potential power supply node of the inverter V1 is directly coupled to the ground potential VSS. . A source of a P-channel MOSFET serving as a high-potential power supply node of another CMOS logic gate (not shown) is commonly coupled to internal voltage supply line VCLP.

In this embodiment, M of the inverter V1
P-channel and N-channel MOSFETs of CMOS logic gates represented by OSFETs P1 and N1 are designed such that, for example, the impurity concentration in the channel region is relatively high and the thickness of the gate oxide film is relatively small. You. Therefore, MOSFETP
1 and N1, etc., have relatively small withstand voltage, but have a sufficiently small threshold voltage, so that in a normal operating state where the substrate voltage is the same as the source potential, It can operate at high speed.

Inverter V1 constituting logic circuit portion LC
The internal signal s1 is supplied from an unillustrated preceding circuit of the logic circuit portion LC to the input terminal of the logic circuit portion LC, that is, the commonly coupled gates of the MOSFETs P1 and N1, and the potential at the output terminal thereof, that is, the commonly coupled drain of the MOSFETs P1 and N1 is The internal signal s2 is supplied to a subsequent circuit (not shown) of the logic circuit unit LC. The power supply voltage VCC is supplied to the back gate of the MOSFET P1, that is, its substrate. The power supply voltage VCC is, as described above,
For example, it is set to +3.3 V, and the ground potential VSS is set to 0 V.

Next, the power supply controller VC1 includes an N-channel MOSFET N11 (second MOSFET) provided between a power supply voltage supply point, that is, the power supply voltage VCC, and the internal voltage supply line VCLP, that is, the source of the MOSFET P1. The gate of the MOSFET N11 is supplied with the internal voltage VP as its output from the charge pump circuit CP1, and its substrate is coupled to the ground potential VSS. A power control signal CV is supplied to the charge pump circuit CP1 from a control unit (not shown). Note that MOSFET N1
Reference numeral 1 is designed so that the thickness of the gate oxide film is relatively large, and has a sufficient withstand voltage. Also,
The power supply control signal CV is, as shown in FIG. 3, a ground potential V when the microcomputer is in a normal operation state.
When the microcomputer is in a standby state, that is, in a standby state, it is at a high level such as the power supply voltage VCC.

Charge pump circuit C of power supply control unit VC1
P1 includes a pump capacity, and the microcomputer is set to a normal operation state and selectively set to an operation state when the power supply control signal CV is set to a low level. In this operation state, the charge pump circuit CP1 generates a predetermined internal voltage VP based on the power supply voltage VCC, and
1 gate. At this time, as shown in FIG. 3, the potential of the internal voltage VP is such that the absolute value of the power supply voltage VCC is VCC, and the threshold voltage of the MOSFET N11 is Vt.
hn, the absolute value VP is set to a high potential V11 (first potential) larger than VCC + Vthn, for example, + 5V.

When the microcomputer is set to the low-speed operation state or the standby state and the power supply control signal CV is set to the high level, the charge pump circuit CP1 stops its charge pump operation, and the internal voltage VP becomes equal to the power supply voltage VCC. The same potential, that is, + 3.3V. The potential of the internal voltage VP at the time of standby is the power supply voltage V
A predetermined positive potential (second potential) having an absolute value slightly smaller than CC may be used.

When the microcomputer is set in a normal operation state and the internal voltage VP is set to a high potential V11 such as +5 V, the power supply control unit VC1 controls the MOSFET N11.
Is completely turned on, and power supply voltage VCC is transmitted to internal voltage supply line VCLP as it is without being affected by the threshold voltage of MOSFET N11. Therefore, the MOSFET P of the inverter V1 of the logic circuit portion LC
In No. 1, the substrate potential and the source potential become the same potential, and the device can operate at relatively high speed. This is the same for other CMOS logic gates whose high-potential-side power supply node is commonly coupled to internal voltage supply line VCLP. Is secured.

On the other hand, when the microcomputer is set to a low-speed operation state or a standby state and the internal voltage VP is set to a low potential such as the power supply voltage VCC, that is, +3.3 V, the MOSFET N11 is turned on in the power supply control unit VC1. However, the power supply voltage VCC is connected to the internal voltage supply line VCLP by the threshold voltage Vth of the MOSFET N11.
n minus VCC−Vthn, for example +
It is transmitted as a potential V12 of 2.3V. For this reason,
CMOS represented by the inverter V1 of the logic circuit section LC
The operation speed of the logic gate is reduced by the compression of the absolute value of the operation power supply itself, the operation current is reduced, and the logic gate P1 represented by MOSFET P1 is used.
A reverse bias state is established between the substrate and the source of the channel MOSFET, the threshold voltage increases due to the body effect, and the operating current is further reduced.

As is apparent from the above description, the charge pump circuit CP1 of the power supply control unit VC1 operates at the power supply voltage VC
What is necessary is just to generate the internal voltage VP of a potential slightly higher than C,
The circuit configuration is relatively simplified. The charge pump circuit CP1 stops its charge pump operation when the microcomputer is in a standby state, and does not require an operating current. Furthermore, a P-channel MOSFET of a CMOS logic gate represented by the inverter V1
The power supply voltage VCC, which is an operation power supply during normal operation, may be supplied to P1 and the like as it is, and an unnecessary high voltage is not applied between the gate substrates.
As a result, in the microcomputer of this embodiment, the operating current in the standby state can be reduced while preventing the breakdown voltage of the MOSFET, thereby reducing the power consumption of the microcomputer in the standby state and improving its reliability. Can be done.

As described above, the MOSFET N11 constituting the power supply controller VC1 of this embodiment is designed so that its gate oxide film has a relatively large thickness, and has a sufficient withstand voltage. You. Therefore, in the microcomputer of this embodiment, the so-called IddQ for the standby current determination is performed while the potential of the power supply voltage VCC is changed relatively largely without regard to the withstand voltage of the P-channel MOSFET constituting the logic circuit portion LC. The test can be easily performed, thereby improving the reliability of the microcomputer.

FIG. 4 is a circuit diagram of a second embodiment of the power supply control unit VC2 and the logic circuit unit LC of the microcomputer of FIG. 1, and FIG. 5 is a signal waveform diagram of one embodiment. It is shown. Note that this embodiment basically follows the embodiment of FIGS. 2 and 3, and therefore, a description will be added only for portions different from this.

In FIG. 4, the logic circuit section L of this embodiment is shown.
C is configured using a CMOS logic gate represented by the inverter V1 as a basic element. The source of the MOSFET P1 serving as the high-potential-side power supply node of the inverter V1 is coupled to the internal voltage supply line VCLP as in the case of the embodiment of FIG. 2, and the back gate serving as its substrate is connected to the internal voltage supply line VCBP. Be combined. Internal voltage supply line VCLP
, A source of a P-channel MOSFET serving as a high-potential-side power supply node of another CMOS logic gate (not shown) is commonly coupled, and a back gate of these P-channel MOSFETs, that is, a substrate is commonly coupled to an internal voltage supply line VCBP. Is done.

Next, the power supply control unit VC2 outputs the power supply voltage VC
An N-channel MOSFET N21 (second MOSFET) provided between C and the internal voltage supply line VCLP;
It includes a P-channel MOSFET P21 provided between the power supply voltage VCC and the internal voltage supply line VCBP, and a P-channel MOSFET P22 provided between the internal voltage supply lines VCLP and VCBP. Among them, MOSFET
The output of the internal voltage VP is supplied to the gate of N21 from the charge pump circuit CP2 receiving the power supply control signal CV.
Connected to SS. The power supply control signal CV is supplied to the gate of the MOSFET P22,
The inverted signal from the inverter V21 is supplied to one gate. These MOSFETs P21 and P22
Is supplied with a power supply voltage VCC. Note that M
The OSFET N21 is designed such that its gate oxide film has a relatively large thickness, and has a sufficient withstand voltage.

Charge pump circuit C of power supply control unit VC2
At P2, the microcomputer is set to a normal operation state, and is selectively set to an operation state when the power supply control signal CV is set to a low level. In this operation state, the charge pump circuit CP2 generates the internal voltage VP based on the power supply voltage VCC and supplies the internal voltage VP to the gate of the MOSFET N21. At this time, the potential of the internal voltage VP is higher than the power supply voltage VCC as shown in FIG.
The potential V21 is lower than the potential obtained by adding the threshold voltage Vthn of the OSFET N21, for example, + 4.0V.

When the microcomputer is set to the normal operation state and the internal voltage VP is set to the potential V21 such as +4.0 V, the power supply control unit VC2 sets the MOSFET N2
1 is turned on. However, as described above, the potential V21 of the internal voltage VP is changed to the potential of the power supply voltage VCC by the MOSFET.
Since the potential is lower than the potential obtained by adding the threshold voltage Vthn of the TN21, the internal voltage supply line VCLP has a threshold voltage Vt of the MOSFET N21 higher than the internal voltage VP.
hn lower than V21−Vthn, that is, for example, +3.
A potential V23 such as 0 V is transmitted.

At this time, in the power supply control section VC2, the MOSFET P22 is turned on in response to the low level of the power control signal CV, and the MOSFET P21 is turned off. A potential V23 such as +3.0 V is transmitted. For this reason, M of the inverter V1 of the logic circuit portion LC
The OSFET P1 has the same substrate potential and source potential, and can operate at a relatively high speed. This means that the high potential side power supply node is connected to the internal voltage supply line VCLP.
, And a substrate portion of the P-channel MOSFET is commonly coupled to the internal voltage supply line VCBP.
The same applies to logic gates, which ensures high speed during normal operation of the microcomputer.

On the other hand, when the microcomputer is set to a low-speed operation state or a standby state and the internal voltage VP is set to a relatively low potential such as the power supply voltage VCC, that is, +3.3 V, in the power supply control unit VC2, the MOSFET N21 is turned on. However, the power supply voltage VCC is lowered to the internal voltage supply line VCLP by the threshold voltage Vthn of the MOSFET N21, and transmitted as VCC-Vthn, that is, a potential V22 such as + 2.3V. At this time, in the power control unit VC2, the MOSFET P
22 is turned off in response to the high level of the power supply control signal CV, the MOSFET P21 is turned on, and the power supply voltage VCC is transmitted to the internal voltage supply line VCBP as it is. Thereby, the inverter V of the logic circuit portion LC
The operation speed of the CMOS logic gate represented by 1 is reduced by compressing the absolute value of the operation power supply itself, the operation current is reduced, and the MOSF
A reverse bias state is applied between the substrate and the source of the P-channel MOSFET represented by ETP1, and the threshold voltage increases due to the body effect, thereby further reducing the operating current.

As is apparent from the above description, in this embodiment, the same operation and effect as those of the embodiments shown in FIGS. 2 and 3 can be obtained, and low power consumption during standby of the microcomputer can be achieved. IddQ for standby current determination
The test can be easily performed, thereby increasing the reliability of the microcomputer.

Further, in this embodiment, as described above,
When the microcomputer is in normal operation,
The potential 21 of the internal voltage VP supplied to the gate of the MOSFET N21 of the power supply control unit VC2 is, for example, +4.0 V higher than the power supply voltage VCC and lower than the potential obtained by adding the threshold voltage Vthn of the MOSFET N21 to the power supply voltage VCC; Logic circuit section LC via internal voltage supply line VCLP
Of the high-potential-side operation power supply supplied to the high-potential-side power supply node of the CMOS logic gate
For example, +3.0 V lower by the threshold voltage Vthn of 21
It is said. Therefore, the potential of the power supply voltage VCC is, for example, +
Even when the voltage fluctuates to about 3.6 V, C
The potential of the high-potential-side operation power supply supplied to the high-potential-side power supply node of the MOS logic gate can be fixed at +3.0 V, whereby the operation of the microcomputer can be stabilized. In addition, since MOSFET N21 is provided between internal voltage supply line VCLP, that is, the high-potential power supply node of the CMOS logic gate of logic circuit portion LC and power supply voltage VCC, conversely, the potential fluctuation of the high-potential power supply node is reduced by the power supply voltage. It can be prevented from being transmitted to VCC, thereby suppressing the potential fluctuation of the power supply voltage VCC,
The operation of the microcomputer and thus the system including the microcomputer can be further stabilized.

FIG. 6 is a circuit diagram of a third embodiment of the power supply control unit VC3 and the logic circuit unit LC included in the microcomputer of FIG. Note that the power supply control unit VC3 and the logic circuit unit LC of this embodiment basically follow the embodiment of FIG. 2, and therefore, a description will be added only for parts different from this.

In FIG. 6, the logic circuit section L of this embodiment is shown.
C is configured using a CMOS logic gate represented by the inverter V1 as a basic element. The source of the MOSFET P1 serving as the high-potential power supply node of the inverter V1 is directly coupled to the power supply voltage VCC, and the N-channel MOSFET N1 (the third power supply node) serves as the low-potential power supply node of the inverter V1.
MOSFET) is connected to the internal voltage supply line VCLS.
Is combined with The ground potential VSS is supplied to the back gate of the MOSFET N1, that is, the substrate portion. The internal voltage supply line VCLS is connected to an N-channel MOSFE serving as a low-potential power supply node of another CMOS logic gate (not shown).
The sources of T are commonly coupled.

Next, the power supply controller VC3 includes a P-channel MOSFET P31 (fourth MOSFET) provided between the internal voltage supply line VCLS, that is, the source of the MOSFET N1, and the ground potential supply point, that is, the ground potential VSS. The gate of the MOSFET P31 is supplied with the internal voltage VM as its output from the charge pump circuit CP3, and its substrate is coupled to the power supply voltage VCC. The power supply control signal CV is supplied to the charge pump circuit CP3. The MOSFET P31 is designed so that its gate oxide film has a relatively large thickness, and has a sufficient withstand voltage. Further, as described above, the power control signal CV is set to a low level such as the ground potential VSS when the microcomputer is in a normal operation state,
When in the standby state, it is at a high level like the power supply voltage VCC.

Charge pump circuit C of power supply control section VC3
At P3, the microcomputer is set to a normal operation state, and is selectively set to an operation state when the power supply control signal CV is set to a low level. In this operation state, the charge pump circuit CP3 generates a predetermined internal voltage VM based on the power supply voltage VCC, and supplies it to the gate of the MOSFET P31. At this time, as shown in FIG. 6, when the threshold voltage of the MOSFET P31 is Vthp, the potential of the internal voltage VM is lower than VSS−Vthp (Vthp is an absolute value), for example, −2V. It is set to a negative potential (third potential).

When the microcomputer is in the standby state and the power supply control signal CV is at the high level, the charge pump circuit CP3 stops its charge pump operation, and the internal voltage VP becomes the same potential as the ground potential VSS, that is, 0V. It is said. The potential of the internal voltage VM during the standby may be, for example, a positive potential (fourth potential) having the same polarity as the power supply voltage VCC and having a small absolute value.

When the microcomputer is set to a normal operation state and the internal voltage VP is set to a negative potential such as -2 V, in the power supply control unit VC3, the MOSFET P31 is completely turned on, and the internal voltage supply line VCLS is , The ground potential VSS is transmitted as it is without being affected by the threshold voltage of MOSFET P31. Therefore, the MOSFET N1 of the inverter V1 of the logic circuit portion LC has the same substrate potential and source potential, and can operate at a relatively high speed. The same applies to the case of another CMOS logic gate whose low potential side power supply node is commonly coupled to the internal voltage supply line VCLS, whereby the logic circuit portion LC and thus the microcomputer including the same during normal operation are provided. High speed is ensured.

On the other hand, when the microcomputer is set to the low-speed operation state or the standby state and the internal voltage VP is set to the ground potential VSS, that is, 0 V, the power supply control unit VC3
In this case, although the MOSFET P31 is turned on, the ground potential VSS is applied to the internal voltage supply line VCLS.
The voltage is increased by the threshold voltage Vthp of ETP31, and
The power is transmitted as SS + Vthp, that is, for example, +1.0 V. For this reason, the operation speed of the CMOS logic gate represented by the inverter V1 of the logic circuit portion LC is reduced by compressing the absolute value of the operation power supply itself,
The operating current is reduced and the MOSFET N1
, A reverse bias state is applied between the substrate and the source of the N-channel MOSFET, the threshold voltage increases due to the body effect, and the operating current of each CMOS logic gate is further reduced.

As a result, also in this embodiment, the same operation and effect as those of the embodiments of FIGS. 2 and 3 can be obtained, whereby the power consumption of the microcomputer at the time of standby can be reduced. The reliability can be improved, and the IddQ test for determining the standby current can be easily performed, whereby the reliability of the microcomputer can be improved.

FIG. 7 is a circuit diagram of a fourth embodiment of the power supply control unit VC4 and the logic circuit unit LC included in the microcomputer of FIG. Since the power supply control section VC4 and the logic circuit section LC of this embodiment basically follow the embodiment shown in FIG. 6, only the different parts will be described.

In FIG. 7, the logic circuit section L of this embodiment is shown.
C is configured using a CMOS logic gate represented by the inverter V1 as a basic element. The source of P-channel MOSFET P1, which is the high-potential power supply node of inverter V1, is directly coupled to power supply voltage VCC. Further, an N-channel M serving as a low potential side power supply node of the inverter V1
The source of the OSFET N1 (third MOSFET) is coupled to the internal voltage supply line VCLS, and its back gate or substrate is coupled to the internal voltage supply line VCBN.
Another CMO (not shown) is connected to the internal voltage supply line VCLS.
The sources of the N-channel MOSFETs serving as the low-potential-side power supply nodes of the S logic gates are commonly coupled, and the substrate portion is commonly coupled to the internal voltage supply line VCBN.

Next, the power control unit VC4 includes a P-channel MOSFET P41 (fourth MOSFET) provided between the internal voltage supply line VCLS and the ground potential VSS,
An N-channel MOSFET N41 provided between the internal voltage supply line VCBN and the ground potential VSS, and an N-channel MOSFET N42 provided between the internal voltage supply lines VCLS and VCBN are included. Among them, MOSFET
The output of the internal voltage VM is supplied to the gate of P41 from the charge pump circuit CP4 that receives the power supply control signal CV.
Connected to CC. The power supply control signal CV is supplied to the gate of the MOSFET N41.
The inverted signal from the inverter V41 is supplied to the gate of No. 2. These MOSFETs N41 and N42
Is supplied with the ground potential VSS. Note that M
The OSFET P41 is designed so that its gate oxide film has a relatively large thickness, and has sufficient withstand voltage.

Charge pump circuit C of power supply control unit VC4
At P4, the microcomputer is set to a normal operation state, and is selectively set to an operation state when the power supply control signal CV is set to a low level. In this operation state, the charge pump circuit CP4 generates the internal voltage VM based on the power supply voltage VCC and supplies the internal voltage VM to the gate of the MOSFET P41. At this time, as shown in FIG. 7, the potential of the internal voltage VM is lower than the ground potential VSS and higher than a potential obtained by subtracting the threshold voltage Vthp of the MOSFET P41 from the ground potential VSS, such as -0.7 V. Negative potential.

When the microcomputer is set to a normal operation state and the internal voltage VM is set to a negative potential such as -0.7 V, the MOSFET P41 is turned on in the power supply control section VC4. However, as described above, the internal voltage VM
Is higher than the potential obtained by subtracting the threshold voltage Vthp of the MOSFET P41 from the ground potential VSS, the internal voltage supply line VCLS is connected to the internal voltage VMS.
A potential such as +0.3 V higher than the threshold voltage Vthp of MOSFET P31 is transmitted. At this time, the power supply control unit VC4 further includes a MOSFET N4
2 is turned on in response to the low level of the power supply control signal CV, the MOSFET N41 is turned off, and the same voltage as that of the internal voltage supply line VCLS, for example, +0.3 V is transmitted to the internal voltage supply line VCBN. Therefore, the MOSFET N1 of the inverter V1 of the logic circuit portion LC has the same substrate potential and source potential, and can operate at a relatively high speed. The same applies to other CMOS logic gates whose low-potential-side power supply nodes are commonly coupled to the internal voltage supply line VCLS and whose N-channel MOSFET substrate is commonly coupled to the internal voltage supply line VCBN.
As a result, high speed operation during normal operation of the microcomputer is ensured.

On the other hand, the microcomputer is set to the standby state, and the internal voltage VM is set to the ground potential VSS, that is, 0V.
In the power control unit VC4, the MOSFET P4
1 is turned on, but the internal voltage supply line VCLS
, The ground potential VSS is raised by the threshold voltage Vthp of the MOSFET P41, and transmitted as VSS + Vthp, that is, a potential V22 such as +1.0 V, for example. At this time, in the power supply control unit VC4, the MOSFET N
42 is turned off in response to the high level of the power supply control signal CV, the MOSFET N41 is turned on, and the ground potential VSS is transmitted to the internal voltage supply line VCBN as it is. Thereby, the inverter V of the logic circuit portion LC
The operation speed of the CMOS logic gate represented by 1 is reduced by compressing the absolute value of the operation power supply itself, the operation current is reduced, and the MOSF
A reverse bias state is established between the substrate and the source of the N-channel MOSFET represented by ETN1, the threshold voltage increases due to the body effect, and the operating current of the CMOS logic gate is further reduced.

As a result, in this embodiment, the same operation and effect as those of the embodiment of FIG. 6 can be obtained, whereby the power consumption of the microcomputer during standby can be reduced, and its reliability can be improved. In addition, the IddQ test for determining the standby current can be easily performed, thereby improving the reliability of the microcomputer.

Further, in this embodiment, as described above,
When the microcomputer is in normal operation,
The potential of the internal voltage VM supplied to the gate of the MOSFET P41 of the power supply control unit VC4 is lower than the ground potential VSS and higher than a potential obtained by subtracting the threshold voltage Vthp of the MOSFET P41 from the ground potential VSS, for example, -0.7.
V, and the potential of the low-potential-side operation power supply supplied to the low-potential power supply node of the CMOS logic gate of the logic circuit portion LC via the internal voltage supply line VCLS is
TP41 lower by threshold voltage Vthp, for example, +0.
3V. Therefore, even when the potential of the ground potential VSS fluctuates, the potential of the low-potential-side operation power supply supplied to the low-potential power supply node of the CMOS logic gate of the logic circuit portion LC can be fixed at +0.3 V. Thereby, the operation of the microcomputer can be stabilized.
Also, the internal voltage supply line VCLS, that is, the low potential side power supply node of the CMOS logic gate of the logic circuit portion LC and the ground potential V
By providing the MOSFET P41 between SS and SS,
Conversely, it is possible to prevent the potential fluctuation of the low potential side power supply node from being transmitted to the ground potential VSS, thereby further suppressing the potential fluctuation of the externally supplied ground potential VSS,
The operation of the microcomputer and thus the system including the microcomputer can be further stabilized.

FIG. 8 is a circuit diagram of a fifth embodiment of the power supply control units VC51 and VC52 and the logic circuit unit LC included in the microcomputer of FIG. Note that this embodiment corresponds to a combination of the embodiments of FIGS. 2 and 6, and therefore, a description will be added only for parts different from these embodiments.

In FIG. 8, the logic circuit section L of this embodiment is shown.
C is configured using a CMOS logic gate represented by the inverter V1 as a basic element. The source of a P-channel MOSFET P1 (first MOSFET) serving as a high-potential power supply node of the inverter V1 is connected to an internal voltage supply line VCL.
The power supply voltage VCC is supplied to its back gate, that is, the substrate portion. An N-channel MOSFET N1 serving as a low potential side power supply node of the inverter V1
The source of the (third MOSFET) is the internal voltage supply line V
The ground potential VSS is supplied to the substrate of the CLS. A source of a P-channel MOSFET serving as a high-potential power supply node of another CMOS logic gate (not shown) of the logic circuit portion LC is commonly coupled to the internal voltage supply line VCLP, and a low-potential side is connected to the internal voltage supply line VCLS. Sources of N-channel MOSFETs serving as power supply nodes are commonly coupled.

Next, the power supply controller VC51 outputs the power supply voltage V
An N-channel MOSFET N51 (second MOSFET) provided between CC and the internal voltage supply line VCLP is included. The gate of the MOSFET N51 is supplied with the output of the internal voltage VP from the charge pump circuit CP51, and its substrate is coupled to the ground potential VSS. The MOSFET N51 is designed so that its gate oxide film has a relatively large thickness, and has sufficient withstand voltage.

Similarly, power supply control unit VC52 is provided between internal voltage supply line VCLS and ground potential VSS.
Channel MOSFET P51 (fourth MOSFET)
including. The gate of the MOSFET P51 is supplied with the internal voltage VM output from the charge pump circuit CP52, and its substrate is coupled to the power supply voltage VCC. The MOSFET P51 is designed so that its gate oxide film has a relatively large thickness, and has a sufficient withstand voltage.

The charge pump circuits CP51 and CP52 of the power supply control units VC51 and VC52 each include a pump capacitor, and are selectively activated when the microcomputer is in a normal operation state and the power supply control signal CV is at a low level. . In this operation state, the charge pump circuits CP51 and CP52 generate predetermined internal voltages VP and VM based on the power supply voltage VCC, respectively.
It is supplied to the gate of the FET N51 or P51, respectively.
At this time, as shown in FIG. 8, the potential of the internal voltage VP is set to a high potential such as +5 V whose absolute value VP is larger than VCC + Vthn, and the potential of the internal voltage VM is changed from the ground potential VSS to the potential of the MOSFET P51. For example, a negative potential such as −2.0 V lower than the potential VSS−Vthp obtained by subtracting the threshold voltage Vthp. When the microcomputer is in the standby state and the power supply control signal CV is at the high level, the charge pump circuits CP51 and CP52 stop the charge pump operation, and
The internal voltages VP and VM are set to the same potential as the power supply voltage VCC or the ground potential VSS, respectively.

When the microcomputer is brought into a normal operation state, the internal voltage VP is set to a high potential such as +5 V, and the internal voltage VM is set to a negative potential such as -2.0 V, the power supply control unit VC51 uses the MOSFET N51. Is completely turned on, and power supply voltage VCC is transmitted to internal voltage supply line VCLP as it is without being affected by the threshold voltage of MOSFET N51. Also, the power control unit V
In C52, the MOSFET P51 is completely turned on, and the ground potential VSS is applied to the internal voltage supply line VCLS.
The signal is transmitted without being affected by the threshold voltage of the OSFET P51. Therefore, the MOSFETs P1 and N1 that constitute the inverter V1 of the logic circuit unit LC are:
In both cases, the substrate potential and the source potential become the same potential, and the device can operate at a relatively high speed. The same applies to other CMOS logic gates whose high-potential-side power supply nodes are commonly coupled to the internal voltage supply line VCLP and whose low-potential-side power supply nodes are commonly coupled to the internal voltage supply line VCLS. High speed during normal operation of the computer is ensured.

On the other hand, when the microcomputer is set to the low-speed operation state or the standby state, the internal voltage VP is set to the low potential such as the power supply voltage VCC, that is, +3.3 V, and the internal voltage VM is set to the ground potential VSS, that is, 0 V, In the control unit VC51, although the MOSFET N51 is turned on, the power supply voltage VCC is applied to the internal voltage supply line VCLP by the threshold voltage Vthn of the MOSFET N51.
Lower by VCC-Vthn, for example, +2.
The potential is transmitted as 3V. In the power supply control unit VC52, although the MOSFET P51 is turned on, the internal voltage supply line VCLS is connected to the ground potential VS.
S is raised by the threshold voltage Vthp of the MOSFET P51, and transmitted as VSS + Vthp, that is, for example, + 1.0V. Therefore, the operation speed of the CMOS logic gate represented by the inverter V1 of the logic circuit portion LC is reduced by compressing the absolute value of the operation power supply itself, the operation current is reduced, and M
P-channel MOSFET represented by OSFET P1
And N-channel M represented by MOSFET N1
A reverse bias is applied between the substrate and the source of the OSFET, and the threshold voltage increases due to the substrate effect.
The operating current of each CMOS logic gate is further reduced.

As a result, in this embodiment, the operation and effect of the embodiment shown in FIGS. 2 and 6 can be obtained together, thereby further reducing the power consumption during standby of the microcomputer and improving its reliability. In addition, the IddQ test for determining the standby current can be easily performed, and the reliability of the microcomputer can be further improved.

FIG. 9 is a circuit diagram of a power supply control section VC6 and a logic circuit section LC included in the microcomputer of FIG. 1 according to a sixth embodiment. Since the power supply control unit and the logic circuit unit of this embodiment basically follow the embodiment of FIG. 4, only the parts different from this will be described.

In FIG. 9, the logic circuit section L of this embodiment is shown.
C is configured using a CMOS logic gate represented by the inverter V1 as a basic element. MOSFE to be a high-potential-side power supply node of inverter V1 constituting logic circuit portion LC
The source of TP1 is coupled to internal voltage supply line VCLP, and its substrate is coupled to internal voltage supply line VCBP. The internal voltage supply line VCLP has another C (not shown).
The sources of the P-channel MOSFETs serving as the high-potential power supply nodes of the MOS logic gates are commonly coupled, and the substrate portion is commonly coupled to the internal voltage supply line VCBP.

Next, the power supply controller VC6 supplies the power supply voltage VC
C and an N-channel MOSFET N provided between the internal voltage supply line VCLP, that is, the source of the MOSFET P1.
61 (second MOSFET). This MOSFET
The gate of N61 is supplied with the internal voltage VP as its output from the charge pump circuit CP6, and its substrate is coupled to the ground potential VSS. The MOSFET N61 is designed such that its gate oxide film has a relatively large thickness, and has a sufficient withstand voltage.

In this embodiment, the microcomputer has an external terminal or test pad TPAD coupled to the internal voltage supply line VCLP, that is, the source of the MOSFET P1 of the inverter V1 of the logic circuit portion LC. When the microcomputer is put into a normal operation state, for example, a power supply smoothing capacitor having a relatively large capacitance value can be coupled to the test pad TPAD. The potential of the potential side operation power supply can be stabilized. Also,
When the microcomputer is set to the predetermined test mode, the potential of the high-potential-side operating power supply on the internal voltage supply line VCLP can be monitored via the test pad TPAD to confirm its normality. The internal voltage VP output from the pump circuit CP6 is forcibly set to the ground potential VSS, and the power supply control unit V
When the MOSFET N61 of C6 is turned off, an arbitrary high-potential-side operation power supply can be input from the test pad TPAD, whereby the test operation of the microcomputer can be efficiently performed.

FIG. 10 shows first input / output buffers IOB1 and IOB2 included in the microcomputer shown in FIG.
FIG. 11 is a circuit diagram of the embodiment, and FIG. 11 is a signal waveform diagram of the embodiment. FIG. 12 also shows FIG.
Input / output buffer IO included in microcomputer
A circuit diagram of a second embodiment of B1 and IOB2 is shown. The specific configuration and operation of the input / output buffer included in the microcomputer of this embodiment and the features thereof will be described with reference to these drawings. The input / output buffer IOB1 of FIGS. 10 and 12 is an application example using the gist of the present invention. Also, input / output buffer IO
B1 is, for example, a central processing unit C of a microcomputer.
PU or direct memory access controller DMA
C and the like, one of which is provided corresponding to each bit of the internal bus IBUS. The input / output buffer IOB2 is connected to the input / output ports IOP1 to IOP5 by the internal bus IBUS.
Is provided corresponding to each of the bits. Further, the input / output buffer IOB1 of FIG. 12 is obtained by adding a bus data holding circuit BDH to the input / output buffer IOB1 of FIG. 10, and the other parts have the same configuration.

In FIG. 10, input / output buffer IOB1
Is an N-channel MOSFET N71 (second
MOSFET) and P-channel MOSFET P71
(First MOSFET). Of these, MOSFE
The gate of the TN 71 is supplied with the internal voltage VP output from the charge pump circuit CP7, and the substrate thereof is supplied with the ground potential VSS. The output signal of a NAND gate NA71 is supplied to the gate of MOSFET P71, and its substrate is coupled to its source, that is, internal node n2. Internal node n1 is further coupled to ground potential VSS via N-channel MOSFET N72. The output signal of the NOR (NOR) gate NO71 is supplied to the gate of the MOSFET N72, and the ground potential VSS is supplied to its substrate.

In this embodiment, the input / output buffer IO
The power supply voltage VCC1 serving as the high-potential-side operation power supply of B1 is not particularly limited, but is, for example, +2.0 V, and the ground potential VSS serving as the low-potential-side operation power supply is 0 V.

The charge pump circuit CP7 of the input / output buffer IOB1 is supplied with an input / output control signal IOC from a control unit (not shown). An output enable signal OE1 is supplied to one input terminal of the NAND gate NA71, and an inverted signal from the inverter V71 is supplied to one input terminal of the NOR gate NO1. The internal output data OD1 is commonly supplied to the other input terminal of the NAND gate NA71 and the other input terminal of the NOR gate NO71 from a register (not shown) in a preceding stage.

The input / output buffer IOB1 further includes a NAND gate NA72 at one input terminal for receiving the input / output control signal IOC. The other input terminal of NAND gate NA72 is connected to internal node n1, that is, internal bus IBU.
S, whose output signal is the internal input data ID1
Are supplied to a subsequent circuit (not shown).

Next, the input / output buffer IOB2 is, although not particularly limited, P-channel MOSFETs P81 and N
Includes a channel MOSFET N81. These MOS
The commonly coupled drains of FETs P81 and N81 are:
It is coupled to the corresponding bit of the internal bus IBUS. The gate of the MOSFET P81 has a NAND gate N
The output signal of A81 is supplied, and the output signal of NOR gate NO81 is supplied to the gate of MOSFET N81. Output enable signal OE2 is supplied to one input terminal of NAND gate NA81, and NOR gate NO81
Is supplied with an inverted signal from the inverter V81. The other input terminals of the NAND gate NA81 and the NOR gate NO81 have internal output data O.
D2 is supplied in common.

The input / output buffer IOB2 further includes a level conversion circuit LC whose input terminal is coupled to a corresponding bit of the internal bus IBUS. This level conversion circuit L
The output signal of C is supplied as internal input data ID2 to a subsequent circuit (not shown) of the input / output buffer IOB2. The power supply voltage VCC2 serving as the high-potential-side operation power supply of the input / output buffer IOB2 is, for example, + 3.3V.

Here, the input / output control signal IOC is not particularly limited, but is selectively set to a low level such as the ground potential VSS when the input / output buffer IOB1 is set to the output mode, as shown in FIG. I / O buffer IO
When B1 is set to the input mode, power supply voltage VCC is selectively applied.
It is set to a high level such as 1. The output enable signal OE1 is selectively set to a high level like the power supply voltage VCC1 when the input / output buffer IOB1 is set to the output mode and the output operation is enabled, and the internal output data OD1 is set to the output enable signal OE1. Are selectively set to the low level of the logic "0" or the high level of the logic "1" during the high level.

On the other hand, the charge pump circuit CP7 of the input / output buffer IOB1 is selectively activated when the input / output buffer IOB1 is set to the output mode and the input / output control signal IOC is set to the low level. In this operation state, the charge pump circuit CP7 generates the internal voltage VP based on the power supply voltage VCC1 and supplies the internal voltage VP to the gate of the MOSFET N71. At this time, the potential of the internal voltage VP is
As shown in FIG. 1, the power supply voltage VCC2, which is the high-potential-side operation power supply of the input / output buffer IOB2, that is, for example, +3.3
V. When input / output buffer IOB1 is set to the input mode and input / output control signal IOC is set to the high level, charge pump circuit CP7 stops its operation, and internal voltage VP is set to power supply voltage VCC1, that is, + 2.0V.

When the input / output buffer IOB1 is set to the output mode, the input / output control signal IOC is set to the low level, and the output enable signal OE1 is set to the high level, the charge pump circuit CP7 is set in the input / output buffer IOB1.
Is in an operating state, and internal voltage VP is set to a high potential such as power supply voltage VCC2. At this time, MOSFET N71
Is completely turned on in response to the high potential of the internal voltage VP, and the power supply voltage VCC1 is directly affected by the MOSFET P7
1 to the internal node n2. Also,
The output signals of the NAND gate NA71 and the NOR gate NO71 are selectively and complementarily set to the high level or the low level according to the logical value of the internal output data OD1.

That is, when the internal output data OD1 is at logic "0", that is, at a low level such as the ground potential VSS, the output signal of the NOR gate NO71 becomes the power supply voltage VC.
It becomes a high level like C1, and the NAND gate NA71
Also becomes a high level like the power supply voltage VCC1. Therefore, the MOSFET P71 is turned off,
MOSFET N71 is turned on, and internal bus IB
A low level such as the ground potential VSS is output to the corresponding bit of US.

On the other hand, when the internal output data OD1 is logic "1"
That is, when a high level such as the power supply voltage VCC1 is set, the output signal of the NOR gate NO71 becomes a low level such as the ground potential VSS, and the output signal of the NAND gate NA71 also becomes a high level such as the ground potential VSS. Therefore, the MOSFET N71 is turned off, the MOSFET P71 is turned on instead, and the internal bus IB is turned off.
A high level such as the power supply voltage VCC1 is output to the corresponding bit of US.

Needless to say, the input / output buffer IOB1
Is set to the output mode, the input / output buffer IOB2 is set to the input mode, and the output enable signal OE2 is set to the low level such as the ground potential VSS. In the input / output buffer IOB2, the output signal of the NAND gate NA81 receives the low level of the output enable signal OE2, and
It is set to a high level like CC2, and NOR gate NO81
Is at a low level such as the ground potential VSS. Therefore, both the MOSFETs P81 and N81 are turned off, and the potential viewed from the input / output buffer IOB2 side of the internal bus IBUS is in the high impedance state Hz.
It is said. At this time, the ground potential V output from the input / output buffer IOB1 in the output mode to the internal bus IBUS.
The low level such as SS or the high level such as the power supply voltage VCC1 is set by the level conversion circuit LC of the input / output buffer IOB2 so that the internal input data ID in which the ground potential VSS is set to the low level and the power supply voltage VCC2 is set to the high level.
2 and transmitted to a subsequent circuit (not shown) of the input / output buffer IOB2.

Next, when the input / output buffer IOB1 is set to the input mode and the input / output control signal IOC is set to a high level like the power supply voltage VCC1, the input / output buffer IOB1 is set to the input mode.
At 1, the charge pump operation of the charge pump circuit CP7 is stopped, and the internal voltage VP is set to a relatively low potential such as the power supply voltage VCC1, that is, + 2.0V. At this time, the MOSFET N71 is turned on for the time being, but the power supply voltage VCC1 becomes the threshold voltage V
The potential becomes lower by thn, that is, for example, +1.0 V and transmitted to the source of MOSFET N71, that is, internal node n2. In response to the low level of the output enable signal OE1, the output signal of the NAND gate NA71 is set to a high level like the power supply voltage VCC1, and the NOR gate NO7
1 is at a low level such as the ground potential VSS. Therefore, both the MOSFETs P71 and N72 are turned off, and the potential viewed from the input / output buffer IOB1 side of the internal bus IBUS becomes the high impedance state H
z.

When input / output buffer IOB1 is set to the input mode, input / output buffer IOB2 is set to the output mode, and output enable signal OE2 is set to the high level such as power supply voltage VCC2. Therefore, the input / output buffer I
In OB2, in response to the high level of the output enable signal OE2, the output signals of the NAND gate NA81 and the NOR gate NO81 are selectively and complementarily set to the low level or the high level. In response to this, the MOSFETs P81 and N8
1 is selectively and complementarily turned on, and an output signal of logic "0" such as ground potential VSS or logic "1" such as power supply voltage VCC2 is selectively transmitted to internal bus IBUS. You. These output signals become internal input data ID1 via the NAND gate NA72 of the input / output buffer IOB1, and are transmitted to a subsequent circuit (not shown) of the input / output buffer IOB1.

By the way, the input / output buffer IOB1 is set to the input mode, and the power supply voltage VC is input via the internal bus IBUS.
When a high level of a high potential such as C2, ie, +3.3 V, is transmitted, the input / output buffer IOB1
The PN junction between the drain and the channel of the ETP 71 is in a forward-biased state, and the source of the MOSFET N 71, ie, the internal node n 2, is connected to the MOSF from the power supply voltage VCC 2.
High potential that is lower by the forward voltage α of ETP71, that is, VC
C2-α is transmitted. However, in this embodiment, as described above, when the input / output buffer IOB1 is set to the input mode, the internal voltage V which is the output of the charge pump circuit CP7 is output.
Since the potential of P is set to the power supply voltage VCC1, that is, +2.0 V, the MOSFET N71 is in a reverse bias state and is turned off. Therefore, power supply voltage VCC1 is not affected by the high potential of internal node n1, and its potential fluctuation can be prevented.

As described above, in this embodiment, a signal is transmitted / received to / from the input / output buffer IOB2 which uses the power supply voltage VCC2 of a different potential as the high-potential-side operation power supply and has a relatively simple configuration. Input / output buffer IOB capable of suppressing potential fluctuation of power supply voltage VCC1 as a potential side operation power supply
1 can be configured.

When the microcomputer is in the standby state, a high potential such as the power supply voltage VCC2 is kept output to the internal bus IBUS, and the signal on the internal bus IBUS is kept at the same logical level. If the data is to be held, a bus data holding circuit BDH as shown in FIG. 12 may be added to the input / output buffer IOB1. The bus data holding circuit BDH includes an inverter V91 including a P-channel MOSFET 91 and an N-channel MOSFET N91, and an inverter V92 including a P-channel MOSFET P92 and an N-channel MOSFET N92.
And an inverter V93 including P-channel MOSFETs P93 and N94 and N-channel MOSFETs N93 and N94. Among them, inverter V9
1 and V93 are selectively cross-coupled by setting the output signal of the inverter V92 to a high level when the microcomputer is in a standby state and the internal control signal STBYN is at a low level, thereby forming one latch circuit. . This latch circuit has its input / output terminals coupled to corresponding bits of internal bus IBUS, and holds the logical level of internal bus IBUS during standby.

In this embodiment, the sources of P-channel MOSFETs P91, P92 and P93 of the latch circuit are N-channel MOSFETs N.sub.1 which receive the internal voltage VP output from charge pump circuit CP9 at their gates.
90 (fifth MOSFET) through the power supply voltage VCC1
Is combined with The potential of the internal voltage VP is equal to the power supply voltage V when the microcomputer is in a normal operation state.
For example, power supply voltage VCC2 higher than CC1, that is, +3.3
V and a high potential (fifth potential) such as V, and at the time of standby, the same potential as the power supply voltage VCC1, that is, + 2.0V. Thus, even when the microcomputer is in a normal operating state and MOSFETs P91 to P94 are off, the internal bus I
It is possible to prevent the internal voltage VCC1 from being affected by a high potential such as the power supply voltage VCC2 output to the BUS and fluctuating the potential.

The operational effects obtained from the above embodiment are as follows. That is, (1) In a semiconductor integrated circuit device such as a microcomputer using a CMOS logic gate as a basic element, a CMOS
P-channel first MOSF constituting a logic gate
An N-channel type in which the gate potential between the source of ET and the power supply voltage VCC is a first potential having an absolute value greater than the power supply voltage VCC during normal operation, and is the same as the power supply voltage VCC during standby. And a second MOSFET of
Alternatively, between the source of the N-channel type third MOSFET constituting the CMOS logic gate and the ground potential VSS, the gate potential is set to a negative third potential lower than the ground potential VSS during normal operation, and the standby state is established. Sometimes the ground potential VS
P-channel type fourth MOSFE having the same potential as S
By providing T, during normal operation, without being affected by the threshold voltage of the second or fourth MOSFET,
The power supply voltage VCC and the ground potential VSS are directly used in CMOS.
The effect is obtained that the power is supplied as the operation power of the logic gate and the high speed of the CMOS logic gate can be secured.

(2) According to the above item (1), during standby,
The absolute value is the above P channel or N channel MOS
Power supply voltage VCC compressed by the threshold voltage of FET
In addition, by supplying the ground potential VSS as the operation power supply of the CMOS logic gate, the effect of reducing the operation current of the CMOS logic gate can be obtained. (3) According to the above item (1), the first and third MOSFs can be supplied during standby without applying a very deep substrate voltage.
An effect is obtained that a reverse bias state is provided between the source and the substrate of the ET so that the leakage current can be reduced.

(4) In the above items (1) to (3), the gate potential during the normal operation of the second MOSFET is slightly higher than the potential obtained by adding the threshold voltage of the second MOSFET to the power supply voltage VCC. Low potential and the fourth MOS
The gate potential during normal operation of the FET is changed to the ground potential V
By setting the negative potential slightly lower than the potential obtained by subtracting the threshold voltage of the fourth MOSFET from SS, the first and third source potentials of the CMOS logic gate, which are the source potentials, are not affected by the potential fluctuation of the power supply voltage. The effect that the potential of the high potential side operation power supply can be stabilized can be obtained. (5) According to the above items (1) to (4), it is possible to reduce the power consumption during standby and increase the reliability thereof while stabilizing the operation of a microcomputer or the like having a CMOS logic gate as a basic element. The effect that it can be obtained is obtained.

(6) In the above item (1), the input / output buffer of the microcomputer or the like is formed based on the first and second MOSFETs, so that the power supply voltage having a relatively simple configuration and a large absolute value is obtained. This enables an input / output buffer to transmit and receive signals to and from another input / output buffer whose power supply is the operating power supply and to suppress the potential fluctuation of the power supply voltage even when a signal having a large absolute value is transmitted. can get. (7) In the above item (6), by providing a bus data holding circuit including a MOSFET similar to the first and second MOSFETs in the input / output buffer, the microcomputer or the like is in a standby state, and a signal path is provided. Even when the high potential is kept output, the input / output buffer that can hold the signal level while suppressing the potential fluctuation of the power supply voltage can be realized.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the block configuration of the microcomputer is not restricted by this embodiment. 2 and 4, and FIGS. 6 to 9, the logic circuit portion LC may include various logic gates other than the inverter, and the logic configuration, the polarity of the power supply voltage, the conductivity type of the MOSFET, and the like according to each embodiment. No restrictions. 3 and 5, the effective level of the power supply control signal CV can be arbitrarily set, and the absolute values of the power supply voltage and the respective internal voltages and their level relationships do not affect the gist of the present invention.

In FIG. 8, power supply control units VC51 and VC51
C52 is a MOSFET P1 constituting the inverter V1.
And N1 are connected to the internal voltage supply line VCBP or VCB.
N, the power control unit VC2 of FIG.
Alternatively, it may be replaced with the power control unit VC4 of FIG. FIG.
In, the test pad TPAD may be an external terminal. Further, test pad TPAD may be coupled to internal voltage supply line VCLP via a transfer gate that is selectively turned on in the test mode.
The microcomputer may include, for example, a test pad coupled to the internal voltage supply line VCLS of FIG. 6, or may include, for example, a test pad for monitoring and setting the potential of the internal voltage VP or VM.

10 and 12, the specific configuration of the input / output buffers IOB1 and IOB2 can take various embodiments, and the polarities and absolute values of the power supply voltages VCC1 and VCC2 can be set arbitrarily. In FIG. 11, the specific level and time relationship of each control signal and the like do not affect the gist of the present invention.

In the above description, the case where the invention made by the present inventor is mainly applied to a single-chip microcomputer, which is the field of application, has been described. However, the present invention is not limited to this. The present invention can also be applied to various logic integrated circuit devices and memory integrated circuit devices having a logic gate as a basic element. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor integrated circuit device having at least a MOSFET logic gate as a basic element and a device or system including the same.

[0096]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a semiconductor integrated circuit device such as a single-chip microcomputer having a CMOS logic gate as a basic element, the gate potential is applied between the source of the P-channel type first MOSFET constituting the CMOS logic gate and the power supply voltage VCC. However, during normal operation, it is set to a first potential having an absolute value larger than the power supply voltage VCC, and during standby, it is set to the same potential as the power supply voltage VCC or the power supply voltage V
An N-channel type second MOSFET having a second potential smaller in absolute value than CC is provided.
N-channel type third MOSF constituting a logic gate
The gate potential between the source of ET and the ground potential VSS is a third negative potential lower than the ground potential VSS during normal operation, and is equal to or slightly higher than the ground potential VSS during standby. A fourth P-channel MOSFET having a fourth potential is provided. Also, CMOS
The source potential or power supply voltage VCC or ground potential VSS of each MOSFET is supplied to the substrate portion of the first and third MOSFETs constituting the logic gate during normal operation, and the power supply voltage VCC or ground potential VSS is supplied during standby. Supply as is.

As a result, during normal operation, the power supply voltage VCC and the ground potential VSS are not changed by the threshold voltage of the second or fourth MOSFET.
A relatively stable operation power supply which is supplied as an operation power supply of a MOS logic gate or which is not affected by potential fluctuations of a power supply voltage VCC or a ground potential VSS externally supplied is used as a CMO.
The power supply voltage VCC and the ground potential VS whose absolute values are compressed by the threshold voltage of the P-channel or N-channel MOSFET during standby are supplied to the S logic gate.
S can be supplied as an operating power supply for the CMOS logic gate, and during standby, the first and third MOSFETs can be supplied without applying a very deep substrate voltage.
Between the source and the substrate in a reverse bias state, thereby reducing the leakage current. As a result, it is possible to reduce the power consumption during standby of the microcomputer or the like, and to improve its reliability.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a single-chip microcomputer to which the present invention is applied.

FIG. 2 is a partial circuit diagram showing a first embodiment of a power supply control unit and a logic circuit unit included in the single-chip microcomputer of FIG. 1;

FIG. 3 is a signal waveform diagram illustrating an embodiment of a power supply control unit and a logic circuit unit of FIG. 2;

FIG. 4 is a partial circuit diagram showing a second embodiment of a power supply control unit and a logic circuit unit included in the single-chip microcomputer of FIG. 1;

FIG. 5 is a signal waveform diagram illustrating an embodiment of a power supply control unit and a logic circuit unit of FIG. 4;

FIG. 6 is a partial circuit diagram showing a third embodiment of a power supply control unit and a logic circuit unit included in the single-chip microcomputer of FIG. 1;

FIG. 7 is a partial circuit diagram showing a fourth embodiment of a power supply control unit and a logic circuit unit included in the single-chip microcomputer of FIG. 1;

FIG. 8 is a partial circuit diagram showing a fifth embodiment of a power supply control unit and a logic circuit unit included in the single-chip microcomputer of FIG. 1;

FIG. 9 is a partial circuit diagram showing a sixth embodiment of a power supply control unit and a logic circuit unit included in the single-chip microcomputer of FIG. 1;

FIG. 10 is a circuit diagram showing a first embodiment of an input / output buffer included in the single-chip microcomputer of FIG. 1;

11 is a circuit diagram showing one embodiment of the input / output buffer of FIG.

FIG. 12 is a circuit diagram showing a second embodiment of the input / output buffer included in the single-chip microcomputer of FIG.

[Explanation of symbols]

CPU central processing unit, CPG clock generation circuit, IBUS, PBUS internal bus, DMAC direct memory access controller, ROM read-only memory, RAM random access memory, TIM timer circuit SCI: Serial communication interface, BSC: Bus controller, IOP1 to IOP9: Input / output port, VC
...... Power control unit, XTAL, EXTAL, MODE, S
TBY, RES, VCC, VSS ... External terminals. LC ...
... Logic circuit sections, VC1 to VC6, VC51 to VC52 ...
... Power supply control units, CP1 to CP9, CP51 to CP52 ...
... charge pump circuit. CV: power control signal, VP,
VCLP, VCBP... Internal voltage. TPAD ... Test pad. IOB1 to IOB2 ... I / O buffer, LC ...
... Level conversion circuit. BDH: Bus data holding circuit. I
OC: input / output control signal, OE1 to OE2: output enable signal, OD1 to OD2: internal output data, ID
1 to ID2: internal input data, VP: internal voltage, n
1 to n2 ... internal nodes. P1, P21 to P22, P3
1, P41, P51, P71, P81, P91 to P94
... P-channel MOSFET, N1, N11, N2
1, N41 to N42, N51, N61, N71 to N7
2, N81, N90 to N94 ... N-channel MOSF
ET, V1, V21, V41, V71, V81, V91
To V93 ... inverter, NA71 to NA72, NA8
1 ... NAND gate, NO71, NO81
... NOR gate (NOR), s1 to s2 ... internal signal,
VCC, VCC1, VCC2 ... power supply voltage, VSS ...
Ground potential.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H03K 19/094 (72) Inventor Masamichi Fujito 5-22-1, Josuihoncho, Kodaira-shi, Tokyo Hitachi, Ltd.・ Inside I-Systems (72) Inventor Hirozo Kawai 5-22-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Super-LSI Systems Inc. (72) Inventor Hiroshi Shinagawa Kodaira, Tokyo 5-22-1, Ichimizu Honcho, Ichimizu Inside Hitachi Cho LSI Systems Co., Ltd.

Claims (8)

[Claims] 1. A first MOSFET of a first conductivity type is provided between a source of the first MOSFET and a power supply voltage supply point, and a gate potential of the first MOSFET has an absolute value larger than the power supply voltage during normal operation. A second potential of the second conductivity type which is the same potential as the power supply voltage or a second potential whose absolute value is smaller than the power supply voltage during standby.
A semiconductor integrated circuit device comprising an FET. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is further provided between a third MOSFET of a second conductivity type, a source of the third MOSFET, and a ground potential supply point. The gate potential is a third potential having a polarity opposite to the power supply voltage during normal operation, and a fourth potential having the same potential as the ground potential or the same polarity as the power supply voltage and having a relatively small absolute value during standby. And a fourth MOSFET of a first conductivity type. 3. The method according to claim 1, wherein an absolute value of the first potential is greater than a value obtained by adding a threshold voltage of the second MOSFET to the power supply voltage. Is the absolute value of the fourth MOSFE.
The power supply voltage is supplied to a substrate portion of the first MOSFET, and the ground potential is supplied to a substrate portion of the third MOSFET. A semiconductor integrated circuit device. 4. The method according to claim 1, wherein an absolute value of the first potential is smaller than a value obtained by adding a threshold voltage of the second MOSFET to the power supply voltage. Is the absolute value of the fourth MOSFE.
The source voltage is supplied to the substrate portions of the first and third MOSFETs during normal operation, and the power supply voltage or the ground potential is supplied during standby. Are supplied, respectively. 5. The semiconductor integrated circuit device according to claim 1, wherein the first or third MOS transistor is provided.
A semiconductor integrated circuit device comprising a pad or an external terminal for monitoring or setting a substantial source potential of an FET. 6. The second and fourth MOSFETs according to claim 1, wherein said second and fourth MOSFETs have a gate oxide film thickness of said first and third MOSFETs. A semiconductor integrated circuit device which is made larger than the MOSFET described in (1). 7. The device according to claim 1, wherein the first and second MOSFETs correspond to another input / output buffer whose absolute value is another power supply voltage larger than the power supply voltage. An input / output buffer for transmitting and receiving a predetermined signal via a signal path, wherein a drain of the first MOSFET is coupled to the corresponding signal path, and a substrate portion of the input / output buffer is commonly coupled to the source. A semiconductor integrated circuit device. 8. The semiconductor integrated circuit device according to claim 7, further comprising a bus data holding circuit including a latch circuit whose input / output terminal is coupled to the corresponding signal path. In the circuit, the gate potential during normal operation,
The power supply voltage is set to a fifth potential having an absolute value larger than the power supply voltage. During standby, the power supply voltage is supplied to the high-potential-side operation power supply via a second conductivity-type fifth MOSFET which is set to the same potential as the power supply voltage. A semiconductor integrated circuit device characterized by being supplied as a device.