JP3737240B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device intended to achieve both high speed and low power consumption.
In recent years, CPUs have been remarkably increased in speed, and those having a clock speed exceeding 200 MHz have been put into practical use. In order to bring out the full performance of the CPU, it is indispensable to increase the speed of the peripheral circuit. However, simply increasing the speed increases the power consumption in proportion to the clock frequency (see equation (1)), and particularly battery driven. There is no denying the inconvenience for equipment.
[0002]
Power consumption = clock frequency x load capacity x power supply voltage ……… ▲ 1 ▼
[0003]
[Prior art]
From equation (1), reducing the power supply voltage is effective for power saving. In fact, portable OA devices often employ a low power supply voltage of about 3.3V. However, simply lowering the power supply voltage reduces the operation speed of the circuit and impairs high speed performance. For example, a circuit with a low threshold transistor (hereinafter referred to as a low threshold circuit) is used. Although it is configured, the low threshold transistor has the disadvantage that the subthreshold current (* 1) is large, so the power saving performance is lost this time, and eventually both high speed and power saving performance are achieved. Can not. * 1: Channel current that flows when the gate voltage is below the threshold voltage and the surface is in a weakly inverted state. In a typical MOS transistor, the subthreshold current increases 10 times when the threshold value decreases by 0.1V.
[0004]
For example, the following are known as conventional semiconductor integrated circuit devices intended to achieve both high speed and low power consumption.
(1) The so-called multi-threshold method (see Fig. 6)
In Japanese Patent Laid-Open No. 6-29834, power is supplied to the low threshold circuit 1 from the high potential power line Vcc through the first high threshold transistor 2 and from the low potential power line Vss. A configuration in which power is supplied via the second high threshold transistor 3 is shown. The first high threshold transistor 2 is a PMOS transistor, and the second high threshold transistor 3 is an NMOS transistor. A pair of complementary control signals CTa and CTa bars are applied to the gates of the transistors.
[0005]
In such a configuration, when CTa is set to L level and CTa bar is set to H level, the first and second high threshold transistors 2 and 3 are both turned on, and Vcc and Vss are supplied to the low threshold circuit 1. Then, the low threshold circuit 1 starts operation. As described, the disadvantage of the low threshold circuit 1 is that the power consumption during standby is large. This disadvantage can be solved by setting CTa to H level and CTa bar to L level. The first high threshold transistor 2 and the second high threshold transistor 3 are completely turned off (because the threshold is high and the subthreshold current does not flow), and the power supply to the low threshold circuit 1 is cut off. Because it is.
(2) What is called substrate potential control method (see Fig. 7)
Japanese Patent Application Laid-Open No. 60-229363 discloses PMOS transistors 5 and 6 constituting a logic circuit 4 (in the figure, an example in which CMOS inverter gates which are basic logic circuits are connected in multiple stages is shown for convenience) A configuration including first and second substrate potential control units 9 and 10 for controlling the substrate potentials (* 2) of the NMOS transistors 7 and 8 is shown. Vbp is the substrate potential of the PMOS transistors 5 and 6 produced by the first substrate potential control unit 9, and Vbn is the substrate potential of the NMOS transistors 7 and 8 produced by the second substrate potential control unit 10. * 2: When the source potential Vs of the MOS transistor is set to 0V and viewed from one point in the channel, the positive potential of the gate potential turns on the channel, but the substrate potential Vb becomes reverse bias under normal operating conditions, and turns off the MOS transistor. . This is because Vb is more negative than Vs in the NMOS transistor. For this reason, the substrate is often regarded as a second gate (or back gate). That is, increasing Vb causes the transistor to decrease conductivity and increase the threshold voltage, resulting in an increase in the transistor's enhancement threshold. Conversely, when Vb is decreased, the transistor increases its conductivity and acts to decrease the enhancement threshold of the transistor as a result of decreasing the threshold voltage.
[0006]
In such a configuration, if Vbp is lowered and Vbn is raised, the threshold values of the MOS transistors 5 to 8 of the logic circuit 4 are lowered, and the high-speed operation is ensured while operating as a low threshold circuit. If Vbp is increased and Vbn is decreased, the threshold value of each of the MOS transistors 5 to 8 of the logic circuit 4 is increased, and the subthreshold current is suppressed to ensure power saving. Coexistence is achieved.
[0007]
[Problems to be solved by the invention]
However, although the above-described multi-threshold method and substrate potential control method are beneficial in that both high speed and low power consumption can be achieved, for example, process cost, layout area, or logic circuit operation start. Focusing on the loss time is still insufficient, and there are technical issues to be solved.
[0008]
That is, in the multi-threshold method, it is necessary to build in two types of transistors, a low threshold value and a high threshold value, which causes an increase in process cost and a high threshold transistor has a low saturation current. The lack of responsiveness inevitably increases the size of the high threshold transistor (especially the channel width) from the standpoint of ensuring high speed, but this has the disadvantage of increasing the layout area. In the substrate potential control method, in order to control the substrate potential of the entire logic circuit, it is necessary to charge and discharge a large substrate capacity. Therefore, the substrate potential switching time becomes long and the operation of the logic circuit is started. There is an inconvenience that the loss time increases.
[0009]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a useful circuit technology that can reduce the process cost and the layout area while reducing the loss time until the operation of a logic circuit starts, while achieving both high speed and low power consumption.
[0010]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a low threshold circuit comprising low threshold transistors; a source connected to a high potential power supply; and a drain having a high potential of the low threshold circuit. A low-threshold first PMOS transistor connected to the power supply node, a source connected to a power supply having a higher potential than the high-potential power supply, and a drain connected to the back gate of the first PMOS transistor. A second PMOS transistor having a threshold value; a resistor inserted between the back gate of the first PMOS transistor and the high-potential power supply; a source connected to the low-potential power supply; and a drain connected to the low threshold voltage A first NMOS transistor having a low threshold value connected to a low-potential power supply node of the circuit; a source connected to a power supply having a lower potential than the low-potential power supply; and a drain connected to the first potential A low threshold second NMOS transistor connected to the back gate of the NMOS transistor, and a resistor inserted between the back gate of the first NMOS transistor and the low potential power source, ON / OFF of the first PMOS transistor and the first NMOS transistor is controlled by a complementary signal, and ON / OFF of the second PMOS transistor and the second NMOS transistor is controlled by a second complementary signal. To do .
[0011]
According to this, if the substrate potential of the first PMOS transistor is controlled to be high and the substrate potential of the first NMOS transistor is controlled to be low by the substrate potential control means comprising the second PMOS and NMOS transistors , The threshold values of the PMOS transistor and the first NMOS transistor are increased, and the first PMOS transistor and the first NMOS transistor are completely turned off to cut off the power supply to the low threshold circuit to ensure power saving. it can.
[0012]
In addition, if the substrate potentials of the first PMOS transistor and the first NMOS transistor at the time of non-control coincide with the substrate potentials of the transistors of the low threshold circuit, the first PMOS transistor and the first PMOS transistor In addition, since the second NMOS transistor can be formed as a low threshold transistor and only one type of transistor is required, the process cost can be reduced, and the first PMOS transistor when operating as the low threshold transistor Since the saturation current of the first NMOS transistor is large and the response is good, the first NMOS transistor can be small and the layout area can be reduced. Further, since the substrate potential only needs to control two transistors ( the first PMOS transistor and the first NMOS transistor) and the substrate capacitance is extremely small, the potential can be switched quickly, and a low threshold value is obtained. Loss time until the start of circuit operation can be greatly reduced.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention.
First, the configuration will be described. In FIG. 1, reference numeral 20 denotes a logic circuit (hereinafter referred to as a low threshold circuit) composed of a low threshold MOS transistor, and a high potential power supply node 21 and a low potential power supply node 22 of the low threshold circuit 20. A high potential power supply Vcc and a low potential power supply Vss are supplied to be turned on and off via a first potential supply circuit 23 and a second power supply circuit 24, respectively.
[0014]
The first power supply circuit 23 includes a low threshold first PMOS transistor 25 having a source connected to Vcc and a drain connected to the high potential power supply node 21 of the low threshold circuit 20, and a source connected to Vcc. Is inserted between the back gate of the first PMOS transistor 25 and Vcc, the second PMOS transistor 26 having a drain connected to the high-potential power supply Vcc 'and the drain connected to the substrate (back gate) of the first PMOS transistor 25. The second power supply circuit 24 includes a low threshold first resistor having a source connected to Vss and a drain connected to the low potential power supply node 22 of the low threshold circuit 20. NMOS transistor 28, a source connected to power supply Vss ′ having a potential lower than Vss, and a drain connected to the substrate (back gate) of first NMOS transistor 28. A second NMOS transistor 29 connected to g), and a inserted resistor 30 between the back gate and Vss of the first NMOS transistor 28. The second PMOS transistor 26 and the resistor 27 constitute the first substrate potential control means according to claim 1, and the second NMOS transistor 29 and the resistor 30 constitute the second substrate potential control means according to claim 1. Configure.
[0015]
CTa and CTa bar are complementary signals for controlling on / off of the first PMOS transistor 25 and the first NMOS transistor 28, and CTb and CTb bar control on / off of the second PMOS transistor 26 and the second NMOS transistor 29. Complementary signal.
In such a configuration, when CTb is set to H level (CTb bar is set to L level), the second PMOS transistor 26 and the second NMOS transistor 29 are turned off, and the first PMOS transistor 25 and the first NMOS transistor 28 are turned off. Are supplied as Vcc and Vss through resistors 27 and 30, respectively, and operate as a low threshold transistor. Therefore, if CTa is set to L level (CTa bar is set to H level) in this state, the first PMOS transistor 25 and the first NMOS transistor 28 are turned on, and Vcc and Vss are supplied to the low threshold circuit 20. Is done.
[0016]
On the other hand, when CTb is set to L level (CTb bar is set to H level), the second PMOS transistor 26 and the second NMOS transistor 29 are turned on, and the substrate potentials of the first PMOS transistor 25 and the first NMOS transistor 28 are Are given by Vcc ′ and Vss ′, respectively, and Vcc ′> Vcc and Vss ′ <Vss, the first PMOS transistor 25 and the first NMOS transistor 28 operate as high threshold transistors (that is, subthreshold currents). There will be less). Therefore, if CTa is set to H level (CTa bar is set to L level) in this state, the first PMOS transistor 25 and the first NMOS transistor 28 are completely turned off, and the power supply to the low threshold circuit 20 is performed. Is cut off.
[0017]
As described above, according to this embodiment, when the low threshold circuit 20 is operated, the first PMOS transistor 25 and the first NMOS transistor 28 can be operated as the low threshold transistors to ensure high speed. At the same time, when the low threshold circuit 20 is not in operation (standby mode), the first PMOS transistor 25 and the first NMOS transistor 28 can be operated as high threshold transistors to ensure power saving and high speed performance. In addition to the effect that both power saving can be achieved, the following advantageous effects (a) to (c) can be achieved.
[0018]
That is, (a) the first and second PMOS transistors 25 and 26 and the first and second NMOS transistors 28 and 29 can be formed as low-threshold transistors. (B) Since the saturation current of the first PMOS transistor 25 and the first NMOS transistor 28 when operating as a low threshold transistor is sufficiently large and the response is good, the process cost can be reduced. (C) Since the substrate potential is controlled only by the back gates of the first PMOS transistor 25 and the first NMOS transistor 28, the substrate capacitance to be controlled is extremely small, and the potential of the substrate potential can be reduced. Can be quickly switched, and the loss time until the operation of the low threshold circuit 20 starts. Can be localized, exceptional effects not in the prior art that can be obtained.
[0019]
In the present embodiment, the configuration of the low threshold circuit 20 is not particularly limited, but the point is that any logic circuit including a low threshold MOS transistor may be used. It can be widely applied from CMOS inverter gates) to complicated ones.
For example, as shown in FIG. 2, n (two in the figure) low threshold PMOS transistors 31 and 32 connected in parallel and n low threshold NMOS transistors 33 and 34 connected in series are connected. The first input (A) is added to the gate of the PMOS transistor 31 and the gate of the NMOS transistor 33, and the nth input (B) is added to the gate of the PMOS transistor 32 and the gate of the NMOS transistor 34. Further, the present invention may be applied to a NAND logic circuit in which the output (X) is extracted from the drain of the NMOS transistor 33.
[0020]
Alternatively, as shown in FIG. 3, n (two in the figure) low threshold PMOS transistors 35 and 36 connected in series and n low threshold NMOS transistors 37 and 38 connected in parallel are connected. In addition, a first input (A) is added to the gate of the PMOS transistor 35 and the gate of the NMOS transistor 37, and an nth input (B) is added to the gate of the PMOS transistor 36 and the gate of the NMOS transistor 38. The present invention may be applied to a NOR type logic circuit in which the output (X) is taken out from the drain of the NMOS transistor 38.
[0021]
Alternatively, as shown in FIG. 4, the first stage input and the mth stage output of the m-th (m is an odd number) low-threshold CMOS inverter gates 39 to 42 connected in series are connected to the m-th stage. The present invention can also be applied to a so-called ring oscillator in which the output is taken out from the buffer 43 (low threshold CMOS inverter gate).
Alternatively, as shown in FIG. 5, one PMOS transistor 44 and n (three in the figure) NMOS transistors 45 to 47 are connected in series, and the enable signal is set to L level during standby to make the PMOS transistor 44 Can be applied to, for example, a dynamic NAND type logic circuit used in a word decoder of a memory, in which an output (X) is set to an L level when all n inputs (A to C) are at an H level. (However, in this case, the power supply circuit 23 on the Vcc side is unnecessary).
[0022]
Note that the resistors 27 and 30 in FIG. 1 may be formed of MOS transistors. That is, the source-drain resistance of the PMOS transistor may be used instead of the resistor 27, and the source-drain resistance of the NMOS transistor may be used instead of the resistor 30. Alternatively, if CTb is added to the gate of the PMOS transistor and CTb is added to the gate of the NMOS transistor, the added PMOS transistor is turned off when the PMOS 26 is turned on, and the added NMOS transistor is turned off when the NMOS 29 is turned on. So desirable.
[0023]
【The invention's effect】
According to the present invention, it is possible to provide a useful circuit technology that can reduce the process cost and the layout area while reducing the loss time until the operation of the logic circuit starts, while achieving both high speed and low power consumption.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an embodiment.
FIG. 2 is a configuration diagram (NAND type) of a low threshold circuit according to an embodiment;
FIG. 3 is a configuration diagram (NOR type) of a low threshold circuit according to an embodiment;
FIG. 4 is a configuration diagram (ring oscillator) of a low threshold circuit according to an embodiment;
FIG. 5 is a configuration diagram (dynamic NAND type) of a low threshold circuit according to an embodiment;
FIG. 6 is a configuration diagram (multi-threshold method) of a conventional example.
FIG. 7 is a configuration diagram of a conventional example (substrate potential control method).
[Explanation of symbols]
Vcc: high potential power supply line Vss: low potential power supply line 20: low threshold circuit 21: high potential power supply node 22: low potential power supply node 25: first PMOS transistor (PMOS transistor)
26: Second PMOS transistor (first substrate potential control means)
27: Resistance (first substrate potential control means)
28: First NMOS transistor (NMOS transistor)
29: Second NMOS transistor (second substrate potential control means)
30: Resistance (second substrate potential control means)

Claims (1)

A low threshold circuit composed of low threshold transistors;
A low threshold first PMOS transistor having a source connected to a high potential power supply and a drain connected to a high potential power supply node of the low threshold circuit;
A low-threshold second PMOS transistor having a source connected to a higher-potential power supply than the high-potential power supply and a drain connected to the back gate of the first PMOS transistor;
A resistor inserted between the back gate of the first PMOS transistor and the high potential power supply;
A low threshold first NMOS transistor having a source connected to a low potential power supply and a drain connected to a low potential power supply node of the low threshold circuit;
A low-threshold second NMOS transistor having a source connected to a power supply lower than the low-potential power supply and a drain connected to the back gate of the first NMOS transistor;
A resistor inserted between the back gate of the first NMOS transistor and the low-potential power source;
Controlling on / off of the first PMOS transistor and the first NMOS transistor by a first complementary signal,
A semiconductor integrated circuit device characterized in that on / off of the second PMOS transistor and the second NMOS transistor is controlled by a second complementary signal .

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