JP2003258614A - Analog switch circuit with reverse current blocking function - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a reverse current or a leak current from occurring, even with a system power source set off, and suppress the size of MOS transistors to reduce the cost. <P>SOLUTION: The circuit is composed of: an analog switch 20 composed of a PMOS 21 and an NMOS 22; an analog switch driver circuit 24 connected to gates of the PMOS and the NMOS; and a high-value selector circuit 23 having two inputs inA, inB connected to two input/output terminals 5, 6 of the analog switch and an output OUT connected to a back gate of the PMOS and a power line of the analog switch driver circuit. The back gate of the PMOS 21 is pulled up by its drain and source potentials, whichever higher, and a level shifter 25 keeps the H-level of the gate potential also pulled up to the drain and source potentials, whichever higher. Thus prevents a reverse current or leakage current, even with the analog switch is off. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention prevents a backflow current when a switch is turned off and a backflow current to a power source when a power supply is turned off, and suppresses a MOS transistor size of a switch portion in a mask in any field using an analog switch. The present invention relates to an analog switch circuit in which the chip area is reduced by reducing the layout occupying area and the cost is reduced.

[0002]

2. Description of the Related Art In recent years, reduction of power consumption has been promoted in all fields, and particularly in the field of using a battery, a system power source O is used to extend the life of the battery.
It is necessary to cut off the excess current flowing from the battery to the system power supply line during FF. Therefore, even in an analog switch, which is frequently used for signal transmission and logic inside the system, it is essential to eliminate the backflow current due to the parasitic effect of the PchMOS transistor when the power is turned off.

Further, the system scale is also increasing year by year due to the enhancement of functions, and for low cost, how to design a small mask layout with the same function to suppress the chip area is a major issue.

A conventional analog switch circuit will be described with reference to the drawings.

FIG. 3 shows a configuration example of a conventional analog switch circuit. In FIG. 3, 1 is a power supply terminal, 2 is an analog switch drive terminal (hereinafter referred to as drive terminal), 3 is a ground terminal, 4 is an analog switch driver circuit (hereinafter referred to as driver circuit), and 5 and 6 are analog respectively. Switch input / output terminals (hereinafter referred to as input / output terminals), 7 is a PchMO forming an analog switch
S transistor (hereinafter referred to as PMOS), 8 is an NchMOS transistor (hereinafter referred to as NMOS) forming an analog switch, 9 and 10 are parasitic diodes existing between the back gate and the source and drain of the PMOS 7, and 11 and 12 are Back gate and source of NMOS8,
It is a parasitic diode that exists between the drains.

The above-mentioned structure is a basic analog switch which is generally used, and the drive terminal 2 is H when O
It becomes FF, and it becomes ON at L, and electricity is applied between the input / output terminals 5 and 6. Further, by increasing the sizes of the PMOS 7 and the NMOS 8, the resistance component of this analog switch can be reduced.

However, in the configuration of FIG. 3, when the system power is off, that is, when the power supply terminal 1 becomes 0 V, some voltage externally using the battery is applied to the input / output terminal 5.
Or if it is applied to 6, the PMOS is
A current flows through the power supply terminal 1 through the parasitic diodes 9 and 10 of No. 1.

On the other hand, the structure shown in FIG. 4 is a structure in which measures are taken, in which the back gate of the PMOS 13 is connected to the drain side potential, and the back gate of the PMOS 14 is connected to the source side potential. PMOS 1
It has a two-stage series configuration in which four drains are connected. With this configuration, since the back gates of the PMOSs 13 and 14 are not connected to the power supply terminal 1, current does not flow from the input / output terminal 5 or the input / output terminal 6 even when the power supply terminal 1 becomes 0V. In addition, the parasitic diode 1
Since 5 and 16 are connected in opposite directions so as to prevent a reverse current from flowing through each other, no leakage current is generated from one input / output terminal to the other input / output terminal.

[0009]

However, in this configuration, since two PchMOS transistors are required, the resistance component of the analog switch is doubled. (To be precise, since it is combined with the resistance component of the NchMOS transistor, it depends on the voltage applied to the input / output terminal 5 or the input / output terminal 6.) Therefore, the resistance component when the analog switch is energized is changed to PchMOS. If it is to be equal to the one shown in FIG. 3 which is composed of one transistor, the size must be doubled. Therefore, if the size of the PMOS 7 is assumed to be 1, the total size of the PMOS 13 and the PMOS 14 is 4, and it is necessary to further increase the size of the PchMOS transistor, which is normally large, by 4 times in order to reduce the resistance component when energized. As a result, the chip area also becomes large and the cost is affected.

The present invention solves the above-mentioned conventional problems. An analog switch which does not generate a reverse current or a leakage current even when the system power supply is turned off and which can reduce the size of the MOS transistor to reduce the cost. The purpose is to provide a circuit.

[0011]

In order to achieve this object, an analog switch circuit with a backflow prevention function of the present invention connects and connects each source and each drain of one PchMOS transistor and one NchMOS transistor. An analog switch used as an output terminal and the PchMO
An analog switch driver circuit connected to each gate of the S transistor and the NchMOS transistor, and two inputs connected to two input / output terminals of the analog switch, respectively, and an output of the PchMO
It is characterized by comprising a back gate of an S transistor and a high value selection circuit connected to a power supply line of the analog switch driver circuit.

According to this structure, the back gate potential of the PchMOS transistor forming the analog switch is hung on the higher potential of the two input / output terminals by using the high value selection circuit, and the higher gate potential is used. It is possible to reduce the current consumption because the reverse current due to the parasitic diode when the analog switch is turned off and the leak due to the decrease of the gate potential are prevented by the hanging to the potential of the above, and the back current does not occur to the power supply line when the system power is turned off. M
A circuit that suppresses the size of the OS transistor and contributes to cost reduction can be realized.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an analog switch circuit with a backflow prevention function according to an embodiment of the present invention.
In FIG. 1, 1 is a power supply terminal, 2 is an analog switch drive terminal (hereinafter referred to as drive terminal), 3 is a ground terminal,
5, 6 are analog switch input / output terminals (hereinafter referred to as input / output terminals), 20 are analog switches, and 21 is Pch.
MOS transistor (hereinafter referred to as PMOS), 22
Is an NchMOS transistor (hereinafter referred to as NMOS), 23 is a high value selection circuit, 24 is an analog switch driver circuit (hereinafter referred to as driver circuit), and 25 is a level shifter.

The analog switch 20 has one PMOS.
21 and one NMOS 22, and PMO
The sources and drains of the S21 and NMOS 22 are connected to each other and to the input / output terminals 5 and 6. The gates of the PMOS 21 and the NMOS 22 are connected to the driver circuit 24, respectively.
4 has a built-in level shifter 25. High price selection circuit 2
3, the two inputs inA and inB are connected to the two input / output terminals 5 and 6 of the analog switch 20, respectively, and the output OUT is connected to the back gate of the PMOS 21 and the power supply line of the driver circuit 24, respectively. .

FIG. 2 shows an example of the structure of the level shifter 25 portion.

The operation of the analog switch circuit configured as above will be described below. Input / output terminal 5
And input / output terminal 6 to input inA and input i, respectively.
The high-value selection circuit 23 to which nB is connected is connected to the back gate of the PMOS 21 forming the analog switch 20 and the power supply line of the output stage of the level shifter 25. Therefore, the back gate potential of the PMOS 21 is either the drain potential or the source potential. The level shifter 25 also hangs the H level of the gate potential to the higher one of the drain potential and the source potential. Therefore, even when the analog switch is off, the input / output terminal 5
Also, leakage does not occur from the high potential terminal of the input / output terminal 6 to the low potential terminal through the parasitic diode, or when the H level of the gate potential becomes the intermediate potential.

Further, since there is no current path from the input / output terminal 5 and the input / output terminal 6 to the power supply terminal 1, even if the power supply voltage is OFF and 0 V, either the input / output terminal 5 or the input / output terminal 6 Even if a voltage is applied to either or both, no current flows into the power supply terminal 1.

Further, a PMO forming an analog switch
Since S is only one of the PMOS 21, it is not necessary to increase the size of the transistor.

[0020]

As described above, according to the present invention,
The analog switch is turned off by suspending the potential of the back gate of the PMOS that constitutes the analog switch to the higher potential of the two input / output terminals using the high value selection circuit, and by suspending the gate potential to the higher potential. Sometimes a reverse current due to a parasitic diode or a leak due to a drop in the gate potential is prevented, and a reverse current to the power supply line does not occur when the system power is turned off, enabling low current consumption and reducing the size of the MOS transistor to lower costs. A contributing circuit can be realized.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an analog switch circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a level shifter according to an embodiment of the present invention.

FIG. 3 is a configuration diagram of an analog switch circuit in a conventional example.

FIG. 4 is a block diagram of an analog switch circuit in another conventional example.

[Explanation of symbols]

1 power supply terminal 2 Analog switch drive terminal 3 ground terminal 5,6 Analog switch input / output terminals 20 analog switch 21 PchMOS transistor 22 Nch MOS transistor 23 High price selection circuit 24 Analog Switch Driver Circuit 25 level shifter

Continued front page    F term (reference) 5J055 AX28 BX17 CX24 DX22 DX52                       DX74 EX02 EY01 EY12 EY21                       EZ00 EZ20 FX18 GX01

Claims (2)

[Claims] 1. An analog switch which connects each source and each drain of one PchMOS transistor and one NchMOS transistor as an input / output terminal, and is connected to each gate of the PchMOS transistor and the NchMOS transistor, respectively. High-value selection having an analog switch driver circuit and two inputs respectively connected to two input / output terminals of the analog switch, and an output connected to the back gate of the PchMOS transistor and the power supply line of the analog switch driver circuit. An analog switch circuit with a backflow prevention function. 2. The analog switch circuit with a backflow prevention function according to claim 1, wherein the analog switch driver circuit has a level shifter at an input portion thereof.