JP3538480B2 - Power supply switching circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply switching circuit,
More specifically, the present invention relates to a power supply switching circuit for selectively supplying either a main power supply or a backup sub-power supply to a load.

Since a semiconductor integrated circuit such as a microcontroller has a semiconductor memory, it has a main power supply supplied during normal operation and a backup sub-power supply for supplying power to the semiconductor memory when the main power supply is turned off. ing. Therefore, a power supply switching circuit that can reliably switch between the main power supply and the sub power supply when the main power supply is turned off is required.

[0003]

2. Description of the Related Art FIG. 3 shows a power supply switching circuit 43 in a conventional microcontroller. The microcontroller includes a main power supply circuit 41, a sub power supply circuit 42, a power supply switching circuit 43, a first load 49, and a semiconductor memory 50 as a second load.

The main power supply circuit 41 is turned on when a power switch (not shown) is turned on, and turned off when the power switch is turned off. When the main power supply circuit 41 is turned on, the main power supply circuit 41 supplies the main power of the voltage Vm to the first load 49. A semiconductor memory 50 is connected to the main power supply circuit 41 via a power supply switching circuit 43 in parallel with a load 49. When the main power supply circuit 41 is turned on, the semiconductor memory 50 is also connected to the semiconductor memory 50 via the power supply switching circuit 43. Supply. When the main power supply circuit 41 is turned off, the main power supply circuit 41 stops outputting the main power supply.

The sub power supply circuit 42 includes a main power supply circuit 41
Is turned off, a sub power supply of the voltage Vs (<Vm) is supplied to the semiconductor memory 50 for backup. The power supply switching circuit 43 includes a PMOS transistor 44, a CMOS inverter 45, and four backflow prevention diodes D3 and D3.
D4, D5, and D6. PMOS transistor 4
4 is connected in series between the main power supply circuit 41 and the semiconductor memory 50;
The control signal S4 output from the S inverter 45 is input.

The CMOS inverter 45 comprises a PMOS transistor 46 and an NMOS transistor 47 connected in series. The source of the PMOS transistor 46 is connected to the main power supply circuit 41 and the sub power supply circuit 42 via backflow prevention diodes D3 and D4.
The source of the transistor 47 is connected to the ground GND. Accordingly, the CMOS inverter 45 is provided with a power supply having a voltage lower by the base-emitter voltage V _{BE of the} backflow prevention diodes D3 and D4 than the voltage of the power supply having the higher voltage value of the main power supply and the sub power supply. , And the ground GND is supplied as a low-potential power supply.

The input terminal of the CMOS inverter 45 is connected to the ground GND via a resistor R5, and the input terminal of the CMOS inverter 45 is connected to the control terminal CTL via two reverse current prevention diodes D5 and D6 connected in series. The control signal S3 has been input. When the main power supply circuit 41 is turned on based on the turning on operation of the power switch, the control signal S3 goes to H level. Conversely, when the main power supply circuit 41 is turned off based on the operation of turning off the power switch, the control signal S3 becomes L level.

The CMOS inverter 45 outputs a voltage of a high potential power supply or a ground GND based on the level of the control signal S3.
The PMOS transistor 44 is turned on and off by outputting the control signal S4 having the voltage That is, when the control signal S3 becomes H level, the CMOS inverter 45 becomes L level.
A control signal S4 of a level (voltage of the ground GND) is output. Based on the L-level control signal S4, the PMOS
The transistor 44 is turned on, and the main power of the main power supply circuit 41 is supplied to the semiconductor memory 50 via the PMOS transistor 44. When the control signal S3 goes low, the CMOS inverter 45 outputs a high-level (high-potential power supply voltage) control signal S4. The PMOS transistor 44 is turned off based on the H-level control signal S4, and the sub power supply of the sub power supply circuit 42
Supplied to and backed up.

[0009]

However, the power supply switching circuit 43 is used to supply the CMOS inverter 45 with a power supply having a higher voltage value among the main power supply and the sub power supply as a high-potential power supply. Diode D
3, D4 are used. Leakage current flows through the diodes D3 and D4 at high temperatures, and leakage current flows even at room temperature due to variations in output characteristics.
The current values I3 and I4 of the diodes D3 and D4 increase. Then, the base-emitter voltage V _{BE of} the diodes D3 and D4 increases, and the voltage of the high-potential power supply supplied to the CMOS inverter 45 decreases.

Therefore, when the main power supply circuit 41 is turned off, an L level control signal S is supplied to the control terminal CTL.
When 3 is input, the CMOS inverter 45 outputs the control signal S4 at H level. Then, the sub power is supplied to the CMOS inverter 45 via the backflow prevention diode D4. At this time, the base-emitter voltage V _{BE of the} diode D4 rises due to the leakage current, and V _BE ≒
Assuming that the voltage is 0.7 volts, the gate voltage of the PMOS transistor 44 and the voltage Vs of the source-side sub power supply
And a potential difference of 0.7 volts is generated. as a result,
At the time of backup, the PMOS transistor 44 is erroneously turned on when it should be off, and the sub power is also supplied to the first load 49 to increase the current of the sub power. Therefore, when the sub power supply circuit 42 generates the sub power by boosting the battery voltage, there is a problem that the power consumption of the battery increases and the backup time of the semiconductor memory 50 decreases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to prevent a malfunction of a PMOS transistor for supplying a main power supply to a load, thereby ensuring that a main power supply and a sub power supply are securely connected. It is another object of the present invention to provide a power supply switching circuit which can switch the power supply.

[0012]

FIG. 1 is a diagram illustrating the principle of the present invention. The PMOS transistor 3 is for supplying the main power 1 to the load 7.

The control circuit 4 is supplied with a high-potential power supply and a low-potential power supply as operating power supplies, and based on the first control signal S1, a second control signal S of a voltage of the high-potential power supply or the low-potential power supply.
2 is output to turn on / off the PMOS transistor 3.

The comparison circuit 5 performs a level comparison between the voltage Vm of the main power supply 1 and the voltage Vs of the sub power supply 2, and outputs a signal corresponding to the comparison result. The selection circuit 6 selects a power supply having a high voltage value from the main power supply 1 and the sub-power supply 2 as a high-potential power supply for supplying the control circuit 4 based on an output signal of the comparison circuit 5, and sets the selected power supply to the voltage. The power is supplied to the control circuit 4 while being maintained.

According to a second aspect of the present invention, a selection circuit is connected between a main power supply and a control circuit, and is turned on / off based on an output signal of a comparison circuit.
A second switch circuit connected between the sub-power supply and the control circuit and turned on and off based on a signal obtained by inverting the level of the output signal of the comparison circuit.

[0016]

Therefore, when the main power supply 1 is turned off, the comparison circuit 5 determines that the voltage Vs of the sub power supply 2 is higher than the voltage Vm of the main power supply 1. The sub power supply 2 is selected by the selection circuit 6 based on the output signal corresponding to the comparison result, and the sub power supply 2 is supplied to the control circuit 4 as a high potential power supply while maintaining the voltage Vs. The sub power supply 2 is supplied to the load 7 to be backed up.

At this time, the control circuit 4 turns off the PMOS transistor 3 based on the first control signal S1.
As a result, the second control signal S2 of the voltage Vs is output.
Since the voltage Vs of the sub power supply 2 is applied to the source side of the PMOS transistor 3, the PMOS transistor 3
No potential difference occurs between the gate voltage of the source and the voltage on the source side. Therefore, the PMOS transistor 3 is reliably turned off at the time of backup, and malfunction of the PMOS transistor 3 is prevented.

According to the second aspect of the present invention, the main power supply is supplied to the control circuit via the first switch circuit, and the sub power supply is supplied to the control circuit via the second switch circuit. Power is supplied to the control circuit while maintaining the voltage.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment in which the present invention is embodied in a power supply switching circuit in a microcontroller will be described with reference to FIG.

The microcontroller is a main power supply circuit 1
1, a sub power supply circuit 12, a power supply switching circuit 13, a first load 35, and a semiconductor memory 36 as a second load. The main power supply circuit 11 is turned on when a power switch (not shown) is turned on, and turned off when the power switch is turned off. When the main power supply circuit 11 is turned on,
The main power supply circuit 11 supplies main power of the voltage Vm to the first load 35. When the main power supply circuit 11 is turned off,
The main power supply circuit 11 stops the output of the main power supply.

The main power supply circuit 11 includes a power supply switching circuit 13
, A semiconductor memory 36 is connected in parallel with the load 35, and when the main power supply circuit 11 is on, the main power supply is also supplied to the semiconductor memory 36 via the power supply switching circuit 13.

The sub power supply circuit 12 boosts the voltage of a built-in battery (not shown) to generate a voltage Vs (<Vm).
Of the semiconductor memory 36
Supply to backup. In this embodiment, the sub power supply circuit 12 generates and outputs a sub power supply regardless of the on / off operation of the power switch.

The power supply switching circuit 13 includes a PMOS transistor 14, a CMOS inverter 15 as a control circuit, a comparator 18 as a comparison circuit, and a selection circuit 19.

The PMOS transistor 14 is connected in series between the main power supply circuit 11 and the semiconductor memory 36, and has a CMOS inverter 15
Output signal is input.

The non-inverting input terminal (+ input terminal) of the comparator 18 is connected to the main power supply circuit 11, and the voltage Vm of the main power supply is input to the non-inverting input terminal. The inverting input terminal (-input terminal) of the comparator 18 is connected to the sub power supply circuit 12, and the voltage Vs of the sub power supply is input to the inverting input terminal.

The comparator 18 has a backflow preventing diode.
High-potential power is supplied via the gates D1 and D2.
Is supplied with a ground GND as a low potential power supply.
You. This high-potential power supply can be a main power supply or a sub-power supply.
In other words, the backflow prevention die is
Base-emitter voltage V of diodes D1 and D2_BEOnly low
Voltage. Therefore, when the main power supply circuit 11 is turned on,
When the main power supply is
It is supplied as power and its voltage is (Vm-V_BE)
You. When the main power supply circuit 11 is off,
Means that the sub power supply of the sub power supply circuit 12 is
The voltage supplied to the comparator 18 is (Vs-V _BE)
It becomes.

The comparator 18 receives the input signal (Vm) of the non-inverting input terminal and the input signal (Vm) of the inverting input terminal.
s), and outputs a signal corresponding to the comparison result to the selection circuit 19. That is, when the comparator 18 determines that the voltage Vm is higher than the voltage Vs, the voltage (V
m-V _BE ) is output. Conversely, when the comparator 18 determines that the voltage Vs is higher than the voltage Vm, it outputs an L-level (ground GND) signal.

The selection circuit 19 selects a power supply having a high voltage value from the main power supply and the sub-power supply as a high-potential power supply for supplying the CMOS inverter 15 based on an output signal of the comparator 18, and selects the selected power supply as the high-potential power supply. The voltage is supplied to the CMOS inverter 15 while maintaining the voltage.

The selection circuit 19 includes a CMOS inverter 20
And first and second switch circuits 24A and 24B. The CMOS inverter 20 includes a PM connected in series.
It comprises an OS transistor 21 and an NMOS transistor 22. The source of the PMOS transistor 21 is connected to the main power supply circuit 1 through the backflow prevention diodes D1 and D2.
1 and the sub power supply circuit 12, and the source of the NMOS transistor 22 is connected to the ground GND. Accordingly, the CMOS inverter 20 is provided with a power supply having a voltage lower by the base-emitter voltage V _{BE of the} backflow preventing diodes D1 and D2 than the voltage of the power supply having the higher voltage value of the main power supply and the sub power supply. Supplied as The output signal of the comparator 18 is input to the CMOS inverter 20, and the CMOS inverter 20 outputs a signal obtained by inverting the input signal to the second switch circuit 24.
Output to B.

The first switch circuit 24A has two PMs.
OS transistors 25 and 26, two NMOS transistors 27 and 28, and two pull-up resistors R1 and R2
And The two PMOS transistors 25 and 26 are connected in series between the main power supply circuit 11 and the node N1. The gates of the PMOS transistors 25 and 26 are connected to the ground GND via the NMOS transistors 27 and 28, respectively. NMOS transistor 2
The output signals of the comparator 18 are input to the gates 7 and 28.

A pull-up resistor R1 is connected between the source and the gate of the PMOS transistor 25, and a pull-up resistor R2 is connected between the drain and the gate of the PMOS transistor 26. Pull-up resistors R1, R2
Is P when the NMOS transistors 27 and 28 are off.
The generation of a potential difference between the source and the gate of the MOS transistors 25 and 26 is prevented.

The second switch circuit 24B has the same configuration as the first switch circuit 24A, and includes two PMOS transistors 29 and 30 and two NMOS transistors 3
1 and 32 and two pull-up resistors R3 and R4. The two PMOS transistors 29 and 30 are connected in series between the sub power supply circuit 12 and the node N1.
The gates of the PMOS transistors 29 and 30 are N
Ground GND via MOS transistors 31 and 32
It is connected to the. The inverted signal of the output signal of the comparator 18 is input to the gates of the NMOS transistors 31 and 32 via the CMOS inverter 20.

A pull-up resistor R3 is connected between the source and the gate of the PMOS transistor 29, and a pull-up resistor R4 is connected between the drain and the gate of the PMOS transistor 30. Pull-up resistors R3, R4
Is P when the NMOS transistors 31 and 32 are off.
The generation of a potential difference between the source and the gate of the MOS transistors 29 and 30 is prevented.

Therefore, when the voltage Vm of the main power supply is higher than the voltage Vs of the sub power supply and the output signal of the comparator 18 is at the H level, the NM of the first switch circuit 24A
The OS transistors 27 and 28 turn on, and the PMOS transistors 25 and 26 turn on. As a result, the main power is supplied to the voltage Vm by the PMOS transistors 25 and 26.
Is maintained and transmitted to the node N1. At this time,
NMOS transistor 3 of second switch circuit 24B
1 and 32 are turned off. Since the voltage Vm of the node N1 is applied to the drain and the gate of the PMOS transistor 30, and no potential difference occurs between the drain and the gate of the transistor 30, the PMOS transistor 30 is turned off, and the PMOS transistor 30 is turned off.
The MOS transistor 29 is also turned off.

The voltage Vs of the sub power supply is higher than the voltage Vm of the main power supply, and the output signal of the comparator 18 is low.
Level, the NMO of the second switch circuit 24B
The S transistors 31 and 32 turn on, and the PMOS transistors 29 and 30 turn on. As a result, the sub power
The voltage is transmitted to the node N1 by the OS transistors 29 and 30 while maintaining the voltage Vs. At this time, the first
NMOS transistors 27 and 2 of the switch circuit 24A of FIG.
8 turns off. Since the voltage Vs of the node N1 is applied to the drain and the gate of the PMOS transistor 26 and no potential difference occurs between the drain and the gate of the transistor 26, the PMOS transistor 26 is turned off and the PMOS transistor 26 is turned off.
The transistor 25 is also turned off.

The CMOS inverter 15 comprises a PMOS transistor 16 and an NMOS transistor 17 connected in series. The source of the PMOS transistor 16 is connected to the node N1, and the NMOS transistor 17
Are connected to the ground GND. Therefore,
To the CMOS inverter 15, a power supply having a higher voltage value selected by the selection circuit 19 among the main power supply and the sub-power supply is supplied as a high-potential power supply, and the ground GND is supplied as a low-potential power supply. That is, when the voltage Vm of the main power supply is higher than the voltage Vs of the sub power supply, the main power supply is supplied to the CMOS inverter 15 as a high potential power supply. Conversely, when the voltage Vs of the sub power supply is higher than the voltage Vm of the main power supply, the sub power supply is supplied to the CMOS inverter 15 as a high potential power supply.

The input terminal of the CMOS inverter 15 receives a first control signal S1 from a control terminal CTL. When the main power supply circuit 11 is turned on based on the turning on operation of the power switch, the first control signal S1 goes to H level. Conversely, when the main power supply circuit 11 is turned off based on the turning off operation of the power switch, the control signal S1 becomes L
Level.

The CMOS inverter 15 turns on and off the PMOS transistor 14 by outputting a high-potential power supply voltage or a ground GND voltage second control signal S2 based on the level of the first control signal S1.

The power supply switching circuit 13 configured as described above
When the power switch is turned on, the main power circuit 11 is turned on to output the main power, and the main power is supplied to the first load 35. Main power supply voltage Vm
Becomes higher than the voltage Vs of the sub power supply, the output signal of the comparator 18 becomes H level. Accordingly, the first
Switch circuit 24A is turned on, and the second switch circuit 2
4B is turned off, and the main power is supplied to the CMOS inverter 15 by the first switch circuit 24A while maintaining the voltage Vm.

Further, C is determined based on the operation of turning on the power switch.
The first control signal S1 at H level is input to the MOS inverter 15 from the control terminal CTL. Then
The L level (ground GN) is output from the CMOS inverter 15.
A second control signal S2 (a voltage of D) is output. At this time, since the voltage Vm of the main power supply is supplied to the source of the PMOS transistor 14, the PMOS transistor 14 is turned on, and the main power is supplied to the semiconductor memory 36 via the PMOS transistor 14.

Conversely, when the power switch is turned off, the main power circuit 11 is turned off, and the supply of the main power to the first load 35 is stopped. With the stop of the supply of the main power, the voltage Vm of the main power drops to the voltage of the ground GND. When the voltage Vs of the sub power supply becomes higher than the voltage Vm of the main power supply, the output signal of the comparator 18 becomes L level. Accordingly, the second switch circuit 24B is turned on, the first switch circuit 24A is turned off, and the CMOS
The sub power is supplied to the inverter 15 by the second switch circuit 24B while maintaining the voltage Vs. Further, based on the turning-off operation of the power switch, the CMOS inverter 15 supplies the L-level first signal from the control terminal CTL.
Is input. Then, the CMOS inverter 15 outputs the H-level (sub-power supply voltage Vs) second
Is output. At this time, since the voltage Vs of the sub power supply is supplied to the drain of the PMOS transistor 14, no potential difference occurs between the drain and the gate of the PMOS transistor 14, and the PMOS transistor 14 is turned off. Therefore, the sub power supply is
6 and backed up. When the PMOS transistor 14 is turned off, the supply of the sub power supply to the first load 35 is cut off, so that an increase in the power consumption of the battery of the sub power supply circuit 12 is suppressed.

The CMOS inverter of the selection circuit 19
20 has a high voltage value of the main power supply or the sub power supply.
Power supply via the backflow prevention diode D1 or D2
Supplied. Backflow prevention diodes D1 and D2
Base-emitter voltage V _BEIs the leakage current at high temperature
Increase due to leakage current due to variations in characteristics.
The voltage supplied to the CMOS inverter 20 is
Voltage V1 between bases and emitters of gates D1 and D2_BEOnly drop
I do. However, the CMOS inverter 20 has a low level.
The voltage of the ground GND can be output as an output signal.
The NMOS transistor of the second switch circuit 24B
Problems can be caused because 31, 32 can be reliably turned off.
There is no.

As described above, the power supply switching circuit 13 of this embodiment
Indicates that PM is at the time of backup of the semiconductor memory 36.
The OS transistor 14 can be reliably turned off to prevent its malfunction, the increase in the power consumption of the battery of the sub power supply circuit 12 can be suppressed, and the normal backup time can be maintained.

The first and second switch circuits 24A and 24B in the selection circuit 19 of the present embodiment use a PMOS transistor to connect the main power supply and the sub power supply to the CMOS.
Since the power is supplied to the inverter 15, the main power and the sub power can be supplied to the CMOS inverter 15 with a simple configuration while maintaining the voltage Vm of the main power and the voltage Vs of the sub power.

The present invention can be arbitrarily modified and embodied as follows. (1) The sub power supply circuit 12 in the above embodiment is configured to be turned on only when the first control signal S1 is at the L level to generate a sub power supply, and the second switch circuit 24B in the selection circuit 19 The PMOS transistor 30, the NMOS transistor 32, and the pull-up resistor R4 may be omitted. In this case, even if the PMOS transistor 29 of the second switch circuit 24B is turned on when the sub power supply circuit is turned off, the sub power supply circuit is insulated from the semiconductor memory 36, so that the main power supply to the sub power supply circuit This is because there is no effect.

(2) The control circuit only needs to be capable of outputting a second control signal of the voltage of the high potential power supply or the low potential power supply supplied to the control circuit. May be prepared as a buffer in which two CMOS inverters 15 are connected in series. In this case, the main power supply is
6, the first control signal S1 is set to L level, and when the sub power is supplied to the semiconductor memory 36, the first control signal S1 is set to the L level.
May be set to the H level.

[0047]

As described above in detail, according to the first and second aspects of the present invention, the PM for supplying the main power to the load is provided.
Malfunction of the OS transistor can be prevented, and the main power supply and the sub power supply can be reliably switched.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a power supply switching circuit according to one embodiment;

FIG. 3 is a circuit diagram showing a conventional power supply switching circuit.

[Explanation of symbols]

1 Main power supply 2 Sub power supply 3 PMOS transistor 4 Control circuit 5 Comparison circuit 6 Selection circuit 7 Load 24A First switch circuit 24B Second switch circuit S1 First control signal S2 Second control signal Vm Main power supply voltage Vs Sub power supply voltage

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-6-86481 (JP, A) JP-A-6-152351 (JP, A) JP-A-6-6934 (JP, A) 235517 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H02J 9/00-11/00 H02J 1/00-1/16 H03K 17/693

Claims (2)

(57) [Claims] 1. A PM for supplying main power to a load.
An OS transistor for supplying the main power to the load by turning on the PMOS transistor based on a first control signal input from the outside when the main power is turned on; Is turned off based on a first control signal.
A power supply switching circuit configured to supply a sub power supply to the load by turning off a transistor, wherein a high potential power supply and a low potential power supply are supplied as operation power supplies,
A control circuit for turning on and off the PMOS transistor by outputting a second control signal having a voltage level of a high-potential power supply or a low-potential power supply based on the first control signal; A comparison circuit that performs a level comparison with the voltage of the sub power supply and outputs a signal corresponding to the comparison result; and a power supply having a higher voltage value among the main power supply and the sub power supply based on an output signal of the comparison circuit. A selection circuit for selecting a high-potential power supply for supplying to the control circuit, and supplying the selected power supply to the control circuit while maintaining the voltage. A first switch circuit that is connected between the main power supply and the control circuit, and that is turned on and off based on an output signal of the comparison circuit; Connected between the control circuit and
2. The power supply switching circuit according to claim 1, further comprising a second switch circuit that is turned on and off based on a signal obtained by inverting a level of an output signal of the comparison circuit. 3.