JP2001313559A - Buffer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a buffer circuit where a chip area is reduced while reducing a leak current. SOLUTION: Transistors(TRs) P1, N1 are output TRs and require a large size because they conduct current amplification. However, there is no TR requiring a large current except them. On the other hand, P-channel TRs P1-P6 and a P-channel TR being a component of a NAND circuit NAND are formed on a common bulk kept to a floating state. Thus, a voltage Vt at an input output terminal T3 is higher than a power supply voltage VDD and even when a parasitic diode D1 is conductive, the common bulk is biased only and no leak current flows via the bulk.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer circuit having an output terminal capable of bidirectionally inputting and outputting data.

[0002]

2. Description of the Related Art In semiconductor integrated circuit technology, it is important to increase the degree of integration of elements and reduce power consumption. In order to reduce the power consumption of the integrated circuit, it is effective to lower the power supply voltage. Conventionally, during the transition period, when the power supply voltage is changed from 5 V to 3.3 V, some circuits in the integrated circuit are designed to operate at a standard voltage of 5 volts, while others are designed to operate at a standard voltage of 5 volts. A multi-supply voltage mixing circuit designed to operate at the lower 3.3 volts will be used. In such a mixed circuit, when a signal is input from a circuit operating at 5 V to a circuit operating at 3.3 V, a current leakage path is formed in some elements in the circuit operating at 3.3 V, or an input is made. When a voltage higher than the power supply voltage is applied to the terminal, P
The SCR having the pnpn structure of the MOS and the NMOS becomes conductive, causing a problem such as a latch-up in which a large current flows and generates heat.

As a circuit for solving the above problem, Japanese Patent Publication No.
Japanese Patent Application Laid-Open No. 79232/1995 discloses a driver circuit shown in FIG. The power supply voltage VDD of this driver circuit is 3.3 V, and when the enable signal EN supplied to the output enable terminal 10 is at H level (3.3 V), the data D supplied to the data input terminal 28 is output to the data output terminal. When the enable signal EN is at L level (0 V), the output impedance of the data output terminal 24 is in a high impedance state. Therefore, a signal of 5 V can be externally supplied to the bus connected to the data output terminal 24. Also,
This driver circuit is formed using a p-type silicon substrate, and the N-channel transistor is formed on an N-well formed on the p-type silicon substrate. In particular, N-channel transistors 30, 32, 36, and 38 are formed on the same N-well that is brought into a floating state.

First, consider the case where enable signal EN is at H level. In this case, the N-channel transistor 1
Since transistor 2 is turned on, transistor 34 is also turned on, and the gate voltage of P-channel transistor 32 goes low. P-channel transistor 32 is turned on. Further, since the gate voltage of the N-channel transistor 26 is always VDD, this transistor is also turned on. On the other hand, the gate voltages of the P-channel transistor 30 and the N-channel transistor 22 are both data D inverted. Therefore, when data D is at H level, the voltage at data output terminal 24 is at H level, and when data D is at L level, the voltage at data output terminal 24 is at L level.

Next, consider the case where enable signal EN is at L level. In this case, the N-channel transistor 12 is turned off, and the N-channel transistor 22
Becomes L level, and N-channel transistor 22 is turned off. Further, the gate voltage of P-channel transistor 30 attains an H level, which is turned off. Therefore, the output impedance of the data output terminal 24 becomes a high impedance state.

At this time, when the switch 44 is turned on, the L level becomes 0 V and H
It is assumed that the output signal S whose level is 5 V is supplied to the driver circuit. Assuming that the threshold voltage of P-channel transistor 30 is 0.7 V and the voltage of signal S is 5 V, P-channel transistor 30 is turned on. Then, while the voltage of the node B becomes 5V, the gate voltage of the P-channel transistor 36 is 0V,
Is turned on. Therefore, the P-channel transistor 32 is turned off, and the current is supplied to the first voltage source 28 (VD
D) Leakage to the side can be prevented.

Further, P-channel transistors 30, 3
The N-wells 2, and 36 are self-biased by parasitic diodes formed between their drains and the N-well. Therefore, there is no current feedback through the parasitic pnp transistor including the N-well and the p-type silicon substrate. Further, by providing P channel transistor 38, the N well is biased to power supply voltage VDD whenever the voltage of data output terminal 24 is at L level. This minimizes the possibility that the parasitic pnp transistor is turned on while the signal S transitions from the L level to the H level. Thus, according to the driver circuit shown in FIG. 4, there is no current leakage path leading to the semiconductor substrate, and the latch-up problem can be prevented.

[0008]

By the way, in the above-mentioned driver circuit, the data D terminal is connected to the data D terminal.
When trying to increase the output current when outputting
It is necessary to increase the current drawn from the channel transistors 32 and 30 and the N-channel transistors 22 and 26, and to increase the gate width. Therefore, the chip size increases. In an actual circuit, a plurality of transistors are connected in parallel to form P-channel transistors 32 and 30 and N-channel transistors 22 and
26 constitutes each transistor. However, as the chip size of the driver circuit increases, the manufacturing cost increases, and the production yield of the circuit decreases because a large number of elements must be used.

The present invention has been made in view of the above circumstances, and has as its object to provide a driver circuit capable of reducing a chip size while eliminating a current leakage path leading to a semiconductor substrate.

[0010]

In order to solve the above-mentioned problems, a buffer circuit according to the present invention comprises a first power supply terminal to which a high potential voltage is supplied and a second power supply terminal to which a low potential voltage is supplied. And controlling whether to output a signal from an output terminal based on an enable signal or to set the output terminal to a high impedance state, wherein a signal between the first power supply terminal and the output terminal is provided. Connected to the first
P-channel transistor, the output terminal and the second
A first N-channel transistor connected between the output terminal and a power supply terminal, a second P-channel transistor having a gate electrode connected to the output terminal, and provided between the output terminal and a node; A gate electrode is connected to the first power terminal, a third P-channel transistor provided between the output terminal and the node, and a gate electrode connected to the first power terminal. A fourth P-channel transistor provided between the output terminal and the gate electrode of the first P-channel transistor, and a signal obtained by inverting the enable signal supplied to the gate electrode; A fifth P-channel transistor provided between a power supply terminal and a gate electrode of the first P-channel transistor; and a first to fifth P-channel transistor. A sixth P-channel transistor formed on a common bulk with the transistor, a drain electrode connected to the bulk, a source electrode connected to the first power supply terminal, and a gate electrode connected to the node; An inverted enable signal is supplied to the gate electrode, and a second N-channel transistor provided between the node and the second power supply terminal, and an inverted input signal when the enable signal is active. And a logic circuit for applying the generated signal to the gate electrode of the first P-channel transistor and the gate electrode of the first N-channel transistor.

In this buffer circuit, the logic circuit includes a first circuit and a second circuit, and the first circuit converts a signal obtained by inverting the input signal when the enable signal is active. Applying the high potential voltage to the gate electrode of the first N-channel transistor while the enable signal is inactive while applying the high potential voltage to the gate electrode of the first N-channel transistor; Seventh and eighth P-channel transistors provided in series between a terminal and a connection point, and ninth and tenth P-channel transistors provided in series between the first power supply terminal and the connection point. A channel transistor; and third and fourth N-channel transistors provided between the connection point and the second power supply terminal. Is formed on a bulk, wherein the gate electrodes of the first 7 P-channel transistor and said third N-channel transistor of the input signal is supplied, the ninth P-channel transistor and the fourth N
Preferably, the enable signal is supplied to each gate electrode of the channel transistor, and the gate electrodes of the eighth and tenth P-channel transistors are connected to the node.

Further, in the buffer circuit described above, it is desirable to use a fifth P-channel transistor having a higher on-resistance than other transistors. In addition, it is preferable that the buffer circuit includes a delay circuit that delays a signal obtained by inverting the enable signal and outputs the delayed signal to the gate electrode of the second N-channel transistor.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [A. First Embodiment] A buffer circuit according to a first embodiment of the present invention will be described below with reference to the drawings.

[1. Configuration of First Embodiment] FIG. 1 is a circuit diagram showing a main configuration of a buffer circuit according to one embodiment of the present invention. FIG. 5 is a sectional view of a main part of the buffer circuit. As shown in FIG. 1, the buffer circuit 100 includes P-channel transistors P1 to P6 and P11 and P12, N-channel transistors N1, N2, N5, and N6, a NAND circuit NAND, a NOR circuit NOR, and an inverter circuit INV.
1, an input terminal T1, an enable terminal T2, and an input / output terminal T3. Note that D1 is a parasitic diode formed between the drain electrode and the bulk of the P-channel transistor P1.

The buffer circuit 100 includes first and second buffers.
(Not shown), a high-potential-side power supply voltage VDD is supplied from a first power supply terminal, and a low-potential-side power supply voltage GND is supplied to a second power supply terminal. ing. VDD is, for example, 3.3V. An enable signal OE that becomes active at the L level is supplied to the enable terminal T2, and first input data Din1 is supplied to the input terminal T1. The logic level voltage of the enable signal OE and the first input data Din1 is such that the L level is GND and the H level is VDD.

When the enable signal OE is at L level, output data Dout is output from the input / output terminal T3. The logical level voltage of the output data Dout is such that the L level is GND and the H level is VDD. On the other hand, when the enable signal OE is at the H level, the output impedance of the input / output terminal T3 is in a high impedance state. At this time, the external circuit 110
Supplies the second input data Din2. The logic level voltage of the second input data Din2 is such that the L level is GND and the H level is VDD '. V
DD ′ is, for example, 5V. That is, the buffer circuit 100 has an output mode for buffering the first input data Din1 and outputting the output data Dout from the input / output terminal T3, and an input mode for receiving the second input data Din2 via the input / output terminal T3. There is.

Next, the P-channel transistor P1 and the N-channel transistor N1 are output transistors for current amplification, have a large cell area, and are formed by connecting a plurality of transistors in parallel on an actual integrated circuit. You.

As shown in FIG. 5, P-channel transistors P2, P3,...
Are configured as P-channel transistors P7 to P10.
It has a common bulk region 103a. In FIG. 1 and FIG. 2, which will be described later, a common bulk portion is indicated by a thick line. In this example, a p-type silicon substrate 101 is used, and the bulk region 103a is
It is an n-well formed thereon. The silicon substrate 1
When the n-type is used for 01, the bulk region becomes an n-type silicon substrate. Further, the common bulk region 103a is not provided with a terminal for supplying the power supply voltage VDD or the ground voltage GND, and the common bulk region 103a is in a floating state. In the following description, the voltage of the common bulk region 103a will be referred to as Vddf.

More specifically, a p-well 103 and an n-well 104 are formed on a p-type silicon substrate 101. The p-well 103 and the n-well 105 are, for example, LO
They are separated by a silicon oxide layer 107 formed by a COS (Local Oxidation of Silicon) method.

The p well 103 has a silicon oxide layer 107
And includes a plurality of regions separated by. In FIG. 5, the first p-well region and the second p-well region 103
b, and the first p-well region is specifically referred to as a common bulk region 103a. In the common bulk region 103a, a first P-channel transistor P1 and second to sixth P-channel transistors P2 to P6 are formed. In addition, the common bulk region 103a has
Seventh to tenth P-channel transistors P7 to P10 included in an output buffer circuit BUF described later are formed.

Each transistor has a gate electrode G, a source electrode S, and a drain D electrode formed via a gate insulating film 111 formed of silicon oxide. A high-concentration n-type region 113 is formed in contact with the drain electrode D of the sixth P-channel transistor P6. A common electrode 115 is formed on the drain D and the high-concentration n-type region 113. The first n-type transistor N1 is included in the n-well 105. The first n
The drain electrode D of the channel transistor N1 is connected to the first P-channel transistor P1, and the output terminal T
Form 3 The common bulk region includes a plurality of regions, each of which may be commonly wired.

Next, the P-channel transistors P2 and P2
3 is interposed between the node X and the input / output terminal T3, and functions as a switch. Particularly, in the input mode, the P-channel transistor P3 operates when the voltage Vt3 of the input / output terminal T3 exceeds the power supply voltage VDD, ie,
When the second input data Din2 is at the H level, the second input data Din2 is turned on to supply Vt3 to the node X.

Next, the P-channel transistor P5 is
It is turned on in the output mode, and the power supply voltage VDD is applied to the gate electrode of the P-channel transistor P1.
There is a function to surely turn this off. The P-channel transistor P4 has the voltage Vt3 of the power supply voltage VDD.
In the case where the power supply voltage exceeds the threshold voltage, the power supply is turned on and has a function of supplying VDD.

Next, the P-channel transistor P6 is turned on in the output mode, and the common bulk region 10 is turned on.
While the power supply voltage VDD is supplied to the common bulk region 103a while the power supply voltage VDD is supplied to the common bulk region 103a, the common bulk region 103a is turned off in the input mode. Further, the N-channel transistor N2 has a function of turning on in the output mode and biasing the node X to 0V.

FIG. 2 is a circuit diagram showing a configuration of the NAND circuit NAND. As shown in FIG.
The ND includes P-channel transistors P7 to P10 and N-channel transistors N3 and N4. The NAND circuit NAND is characterized in that, first, the common bulk region 103a described above is used as the bulk of the P-channel transistors P7 to P10, and second, that the P-channel transistors P8 and P10 are provided. There is. Since the voltage Vx of the node X is supplied to each gate electrode of the P-channel transistors P8 and P10,
When the voltage Vx is at the H level, these transistors P8 and P10 are turned off.

In the above configuration, since the transistor at the output stage is constituted only by the P-channel transistor P1 and the N-channel transistor N1, even when a large output current is taken out from the input / output terminal T3 in the output mode, these transistors can be used. Since it is sufficient to increase the transistor size only for the transistors P1 and N1, the chip area of the buffer circuit 100 can be reduced. In addition, P-channel transistors P2 to P
Since the ten common bulk regions 103a are in a floating state, even if the input / output terminal voltage Vt3 exceeds the power supply voltage VDD in the input mode, only the common bulk region 103a is biased via the parasitic diode D1. There is no occurrence of a large leak current and latch-up.

As shown in FIG. 1, the buffer circuit 100 has an output buffer circuit BUF connected to the output terminal T3. The output buffer circuit BUF includes an eleventh P-type transistor P11, a first CMOS inverter OB1 including a fifth n-type transistor N5, a twelfth P-type transistor P12, and a sixth n-type transistor N6. And a second CMOS inverter OB2. The output signal is amplified by the output buffer circuit BUF.

[2. Operation of First Embodiment] Next, the operation of the buffer circuit 100 will be described separately for an output mode and an input mode. [2-1: Input Mode] In the input mode, the enable signal OE goes high. [2-1-1: 0V <Vt3 <VDD] P-channel transistors P1 to P6 cause pn between VDD and Vddf.
A junction diode is inserted. Therefore V
ddf is the on-state voltage V of the diode in the forward direction from VDD.
The value becomes lower by f.

Since the enable signal OE supplied to the terminal T2 is at the H level, the NAND circuit NAND
Output signal na1 attains an H level, and the voltage of the output signal na1 should originally match the power supply voltage VDD. However, the voltage of the output signal na1 is given on the path of the power supply voltage VDD → P7, P8 or P9, P10 → na1. For this reason,
With only the NAND circuit NAND, the gate voltage of the P-channel transistor P1 cannot be reliably matched with the power supply voltage VDD. In order to solve this problem, a P-channel transistor P5 is provided. That is, since the inversion enable signal ENN is supplied to the gate electrode of the P-channel transistor P5, it is turned on in the input mode. Therefore, the voltage of the output signal na1 can be made equal to the power supply voltage VDD, whereby the P-channel transistor P1 can be reliably turned off. Therefore, the buffer circuit 100
It operates normally without unnecessary leak current flowing.

[2-1-2: Vt3> VDD] Next, Vt
Consider the case where 3> VDD. For example, the second input data D
This is the case where the voltage of in2 becomes 5V. Also in this case, since the voltage of the signal nr1 becomes 0 V, the N-channel transistor N1 is turned off. Further, since Vt3> VDD, the P-channel transistor P2 is turned off, while the P-channel transistor P3 is turned on. Therefore, voltage Vx at node X matches Vt3, and P-channel transistor P6 is turned off.

Incidentally, the P-channel transistor P1
A parasitic diode D1 is attached between the drain electrode and the common bulk. When the voltage Vt3 of the input / output terminal T3 exceeds the power supply voltage VDD, the parasitic diode D1 turns on. If the forward drop voltage of the parasitic diode D1 is represented by Vf, the common bulk voltage Vddf
Is Vddf = Vt3-Vf. Next, since the inversion enable signal ENN is 0V, the N-channel transistor N2 is turned off. Further, since Vt3> VDD, the P-channel transistor P3 is turned on, and the voltage Vt3 is supplied to the node X. Vx is Vt3
And Vddf = Vt3-Vf, the P-channel transistors P8 and P10 constituting the NAND circuit NAND are turned off. Further, since the voltage of the inversion enable signal ENN is 0 V, the N-channel transistor N4 is turned off.

When ENN = 0 V and the P-channel transistor P4 is turned on, na1 = Vt3, Vd
Since df = Vt3-Vf, the drain voltage of the P-channel transistor P5 becomes Vt3. On the other hand, since the source voltage of the P-channel transistor P5 becomes VDD,
P-channel transistor P5 is turned on, and a current slightly flows. At this time, the gate voltage of the P-channel transistor P1 becomes Vt3. Since the voltage Vt3 is higher than the common bulk voltage Vddf, the P-channel transistor P
1 is turned off. Therefore, in this case, there is no path through which an unnecessary leak current flows except for the P-channel transistor P5. The P-channel transistor P2
Is that when Vt> VDD, Vx = Vt3 and Vt3 are 0V
, Vx is reduced to 0V. However, even if there is only P-channel transistor P3 and there is no P2,
The same operation can be performed, and the transistor P2 may be arbitrarily provided.

[2-2: Output Mode] Next, the operation in the output mode will be described. In the output mode, the enable signal OE is at L level. The voltage of the inversion enable signal ENN is V
As a result, the N-channel transistor N2 is turned on, and the voltage Vx of the node X becomes 0V. In the output mode, the voltage Vt3 of the input / output terminal T3 is equal to the power supply voltage VD.
D, the P-channel transistor P2
And P3 are turned off.

On the other hand, since the voltage Vx (= 0 V) is supplied to the gate electrode of the P-channel transistor P6, it is turned on. Therefore, the power supply voltage V
DD is supplied, and its voltage Vdff matches VDD. Therefore, since the bulk voltages of the P-channel transistors P7 to P10 constituting the NAND circuit NAND also become VDD, the NAND circuit NAND operates as a general logical product inverting circuit. More specifically, since Vx = 0V, P-channel transistors P7 and P8 are always on, and since ENN = VDD, P-channel transistor P9 is off and N-channel transistor N4 is on. Becomes Therefore, the NAND circuit NAND is equivalent to an inverter circuit in which the P-channel transistor P7 and the N-channel transistor N3 are connected in series. Therefore, the output signal na1 of the NAND circuit NAND is obtained by inverting the first input data Din1. Further, the gate voltage of the P-channel transistor P5 becomes VDD, so that the P-channel transistor P5 is turned off. In addition, P-channel transistor P4
Is also turned off.

From these, the output mode buffer circuit 1
00 is equivalent to a first inversion circuit (corresponding to a NAND circuit NOR and a NOR circuit NOR) and a second inversion circuit including a P-channel transistor P1 and an N-channel transistor N1 connected in series. . Therefore, the buffer circuit 100 can output the current-amplified output data Dout having the same polarity as that of the first input data Din1 from the input / output terminal T3. In the output mode, there is no path through which unnecessary leak current flows.

[2-3: Size of P-Channel Transistor P5] Here, the size of the P-channel transistor P5 will be examined. First, in the input mode, Vt
3> VDD, although a small leak current flows through the P-channel transistor P5, it is actively turned on when 0V <Vt3 <VDD, and the purpose is the gate of the P-channel transistor P1. V on electrode
This is for biasing DD to surely turn off the transistor P1. Therefore, the P-channel transistor P
For the transistor size of 5, a small one is sufficient.

As described above, in the buffer circuit 100 of the first embodiment, although a slight leak current flows through the P-channel transistor P5 when Vt3> VDD in the input mode, an unnecessary current otherwise occurs. Does not flow, and no problem such as latch-up occurs. Further, as compared with the conventional buffer circuit shown in FIG. 4, the number of P-channel transistors and N-channel transistors in the output stage can be reduced, so that the chip area occupied by buffer circuit 100 can be significantly reduced. Becomes

[B. Second Embodiment] In the above-described first embodiment, in the input mode, when Vt3> VDD, a slight leak current flows through the P-channel transistor 5. The second embodiment has been made in view of this point, and aims to further reduce the current consumption of the circuit.

FIG. 3 is a circuit diagram showing a configuration of a buffer circuit 200 according to the second embodiment. As shown in the figure, the buffer circuit 200 uses a P-channel transistor P5 'having a longer gate length than the P-channel transistor P5, and a delay circuit DL for delaying the inversion enable signal ENN is connected to the gates of the inverter INV1 and the N-channel transistor N2. The configuration is similar to that of the buffer circuit 100 of the first embodiment shown in FIG.

Since the P-channel transistor P5 'has a longer gate length, the on-resistance is larger than that of the P-channel transistor P5. Therefore, in the output mode, when a voltage (Vt3−VDD) is applied between the source electrode and the drain electrode of the transistor,
The current flowing there is a P-channel transistor P5 '.
Is smaller. Generally, transistors of an integrated circuit are formed by the same cell, but in this example, P
The channel transistor P5 'is formed by another cell. For example, other P-channel transistors P2 to P1
When the gate length of P2 is 10 μm, the gate length of the P-channel transistor P5 ′ is set to 100 μm. Thereby, when Vt3> VDD in the input mode, the value of the current flowing through P-channel transistor P5 'is reduced by about 1 /
It becomes possible to reduce to 10.

By the way, the gate electrode of the P-channel transistor P1 is accompanied by a stray capacitance due to wiring and the like. Therefore, the P-channel transistor P
When the ON resistance of 5 ′ is increased, the time constant increases.
Therefore, in the output mode, if signal na1 is 0V
When the mode is switched from the output mode to the input mode, the gate voltage of the P-channel transistor P1 gradually (slowly) increases from 0 V to Vt3 due to a large time constant. It may not be possible to turn off reliably (quickly). Therefore, in this example, the delay circuit DL is provided to supply the voltage VDD to the gate electrode of the P-channel transistor P1 immediately after switching to the mode.

As shown in FIG. 3, the delay circuit DL includes a buffer B, inverters INV2 and INV3, a P-channel transistor P13, and an N-channel transistor N7. According to the delay circuit DL, the inverted enable signal ENN is delayed by the propagation delay of each component, and is output as the delayed inverted enable signal ENN '.

Thus, the N-channel transistor N2
Changes from the on state to the off state with a slight delay when the inversion enable signal ENN switches from the H level to the L level, that is, when switching from the output mode to the input mode. As a result, immediately after the mode is switched to the input mode, the N-channel transistor N2 is in the ON state, and the voltage Vx of the node X is maintained at 0 V, so that the P-channel transistors P8 and P10 shown in FIG. Become. At this time, the P-channel transistor P
9, the voltage of the output signal na1 of the NAND circuit NAND is equal to the power supply voltage VD.
It matches D. Thereafter, when a certain time (for example, 15 ns) elapses, the N-channel transistor N2 transitions to the off state. Then, as in the first embodiment, the P-channel transistor P5 is turned on, and the gate electrode of the P-channel transistor P1 is biased to Vt3.

As described above, in the second embodiment, the leakage current is reduced by increasing the gate length of the P-channel transistor P5 'to increase the on-resistance, and the delay circuit DL is used to reduce the leakage current in the input mode. P-channel transistor P1 can be reliably turned off.

[0045]

As described above, according to the present invention, in a buffer circuit whose output terminal can be controlled to a high impedance state, even if a voltage higher than the power supply voltage is applied to the output terminal, the leakage is prevented. Output transistors can be reduced while preventing current and latch-up. As a result, even when a large current is extracted from the output terminal, the chip size of the buffer circuit can be reduced, the cost can be reduced, and the yield can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a buffer circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a NAND circuit used in the embodiment.

FIG. 3 is a circuit diagram of a buffer circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram illustrating a configuration of a conventional buffer circuit.

FIG. 5 is a cross-sectional view illustrating a partial configuration of a buffer circuit used in the first embodiment of the present invention.

[Explanation of symbols]

P1 to P12, P5 ': P-channel transistor, N
1 to N6 N channel transistor, NAND NAND circuit (second circuit), NOR NOR circuit (first circuit), DL delay circuit, 100, 200 buffer circuit.

Claims (4)

[Claims] A first power supply terminal to which a high potential voltage is supplied and a second power supply terminal to which a low potential voltage is supplied, wherein a signal is output from an output terminal based on an enable signal;
Alternatively, a buffer circuit capable of controlling whether to set the output terminal to a high impedance state, comprising: a first P-channel transistor connected between the first power supply terminal and the output terminal; A first N-channel transistor connected between the second power supply terminal, a second P-channel transistor having a gate electrode connected to the output terminal and provided between the output terminal and a node; A transistor having a gate electrode connected to the first power supply terminal and a third electrode provided between the output terminal and the node;
A fourth P-channel transistor having a gate electrode connected to the first power supply terminal and provided between the output terminal and a gate electrode of the first P-channel transistor; A signal obtained by inverting the enable signal is supplied to a gate electrode, and a fifth P-channel transistor provided between the first power supply terminal and a gate electrode of the first P-channel transistor; A sixth electrode formed on a common bulk with the first to fifth P-channel transistors, a drain electrode connected to the bulk, a source electrode connected to the first power supply terminal, and a gate electrode connected to the node; The inverted enable signal is supplied to a gate electrode of the P-channel transistor, and the node is connected to the second power supply. A second N-channel transistor provided between the first N-channel transistor and a source terminal; and a signal obtained by inverting an input signal when the enable signal is active, a gate electrode of the first P-channel transistor and the first N-channel transistor. And a logic circuit for applying a voltage to the gate electrode. 2. The buffer circuit according to claim 1, wherein the logic circuit includes a first circuit and a second circuit, wherein the first circuit is configured to output a signal when the enable signal is active. Applying the signal obtained by inverting the input signal to the gate electrode of the first N-channel transistor, and applying the high potential voltage to the gate electrode when the enable signal is inactive; And a seventh and an eighth P-channel transistor provided in series between the first power supply terminal and the connection point; and a circuit provided in series between the first power supply terminal and the connection point. Ninth and tenth P-channel transistors, and third and fourth N-channel transistors provided between the connection point and the second power supply terminal. P channel A transistor is formed on the bulk, the input signal is supplied to each gate electrode of the seventh P-channel transistor and the third N-channel transistor, and the ninth P-channel transistor and the 4. The buffer circuit according to claim 4, wherein the enable signal is supplied to each gate electrode of the fourth N-channel transistor, and the gate electrodes of the eighth and tenth P-channel transistors are connected to the node. 3. The buffer circuit according to claim 1, wherein the fifth P-channel transistor has a higher on-resistance than other transistors. 4. A delay circuit for delaying a signal obtained by inverting the enable signal and outputting the delayed signal to a gate electrode of the second N-channel transistor.
3. The buffer circuit according to 1.