JPH0567963A - Integrated logic circuit - Google Patents
Integrated logic circuitInfo
- Publication number
- JPH0567963A JPH0567963A JP3226888A JP22688891A JPH0567963A JP H0567963 A JPH0567963 A JP H0567963A JP 3226888 A JP3226888 A JP 3226888A JP 22688891 A JP22688891 A JP 22688891A JP H0567963 A JPH0567963 A JP H0567963A
- Authority
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- Japan
- Prior art keywords
- circuit
- power supply
- gate
- logic
- supply voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Logic Circuits (AREA)
- Dram (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体集積回路技術さ
らにはレベル変換回路の構成に適用して特に有効な技術
に関し、例えば２電源方式のＭＯＳ論理ＬＳＩの出力バ
ッファ回路に利用して有効な技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit technology, and more particularly to a technology which is particularly effective when applied to the configuration of a level conversion circuit. Regarding technology.
【０００２】[0002]
【従来の技術】近年、ＬＳＩの微細化が進むにつれて、
ＭＯＳＬＳＩにおいては、電源電圧が５Ｖ一定のままで
は短チャネル効果やホットエレクトロンの発生、耐圧の
低下等、素子特性上種々の問題が生じる。そこで、ＬＳ
Ｉ内部に降圧回路を設け、外部から供給された＋５Ｖの
ような電源電圧Ｖｃｃで入出力バッファを駆動するとと
もに、上記降圧回路で降圧した３．３Ｖのような低電圧
でメモリアレイ部やデコーダ等の周辺回路を駆動するよ
うにしたＬＳＩメモリが提案されている（特願平１−６
５８４０号）。2. Description of the Related Art In recent years, as miniaturization of LSI has progressed,
In a MOS LSI, if the power supply voltage is kept constant at 5 V, various problems occur in device characteristics such as short channel effect, generation of hot electrons, and reduction of breakdown voltage. So LS
A step-down circuit is provided inside I to drive the input / output buffer with a power supply voltage Vcc such as +5 V supplied from the outside, and a memory array section, a decoder, etc., with a low voltage such as 3.3 V stepped down by the step-down circuit. An LSI memory in which peripheral circuits of the above are driven has been proposed (Japanese Patent Application No. 1-6).
5840).
【０００３】[0003]
【発明が解決しようとする課題】上記先願発明において
は、素子の耐圧に合わせた電圧で各回路を駆動できると
いう利点がある。しかしながら、３．３Ｖのような電圧
で動作される論理ゲート回路で図６に示すような出力バ
ッファ回路を駆動させるようにすると、論理ゲート回路
Ｇ１，Ｇ２の出力ハイレベルは３．３Ｖであるため、次
段のインバータＩＮＶ１，ＩＮＶ２のＶｃｃ側のＰ−Ｍ
ＯＳＦＥＴが完全にオフしなくなり、貫通電流が流れて
消費電力が増加するという問題点がある。そこで、上述
の先願発明（特願平１−６５８４０号）では、図６のイ
ンバータＩＮＶ１，ＩＮＶ２の代わりに、図７に示すよ
うなラッチ型のレベル変換回路ＬＣ１，ＬＣ２を設ける
ようにしている。しかるに、上記レベル変換回路を設け
た出力バッファ回路にあっては、ゲート段数が多くなる
ため、信号遅延時間が大きくなって出力バッファの動作
速度が遅くなるという問題点があった。The above-mentioned invention of the prior application has the advantage that each circuit can be driven with a voltage that matches the breakdown voltage of the device. However, when the output buffer circuit as shown in FIG. 6 is driven by the logic gate circuit operated at a voltage of 3.3V, the output high level of the logic gate circuits G1 and G2 is 3.3V. , PM on the Vcc side of the next-stage inverters INV1 and INV2
There is a problem that the OSFET does not turn off completely, a through current flows, and power consumption increases. Therefore, in the above-mentioned prior invention (Japanese Patent Application No. 1-65840), latch type level conversion circuits LC1 and LC2 as shown in FIG. 7 are provided instead of the inverters INV1 and INV2 shown in FIG. .. However, in the output buffer circuit provided with the level conversion circuit, the number of gate stages increases, so that there is a problem that the signal delay time increases and the operation speed of the output buffer decreases.
【０００４】本発明の目的は、電源電圧の低い回路によ
って電源電圧の高い回路を動作させる場合に、占有面積
が小さく遅延時間も短いレベル変換回路を提供すること
にある。この発明の前記ならびにそのほかの目的と新規
な特徴については、本明細書の記述および添附図面から
明らかになるであろう。An object of the present invention is to provide a level conversion circuit having a small occupied area and a short delay time when operating a circuit having a high power supply voltage by a circuit having a low power supply voltage. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【０００５】[0005]
【課題を解決するための手段】本願において開示される
発明のうち代表的なものの概要を説明すれば、下記のと
おりである。すなわち、低い電源電圧で動作する論理回
路と高い電源電圧で動作する論理回路との間に、低い電
源電圧で動作する論理部の次段に高い電源電圧で動作す
るラッチ回路部が接続されてなるレベル変換回路を設け
るようにしたものである。上記の場合、例えばラッチ型
レベル変換回路を構成する論理ゲートの一方を複合論理
ゲートとする。The typical ones of the inventions disclosed in the present application will be outlined below. That is, a latch circuit section operating at a high power supply voltage is connected to the next stage of a logic section operating at a low power supply voltage between a logic circuit operating at a low power supply voltage and a logic circuit operating at a high power supply voltage. A level conversion circuit is provided. In the above case, for example, one of the logic gates forming the latch type level conversion circuit is a composite logic gate.
【０００６】[0006]
【作用】上記した手段によれば、レベル変換回路を構成
する素子の数を減らすことができるとともにレイアウト
においてを同一ウェル内にレベル変換回路を構成するＭ
ＯＳＦＥＴを形成することができるため占有面積を減少
させることができ、また論理段数を少なくすることがで
きるため遅延時間も短くなり、回路の動作速度を向上さ
せることができる。According to the above-mentioned means, the number of elements forming the level converting circuit can be reduced and the level converting circuit can be formed in the same well in the layout.
Since the OSFET can be formed, the occupied area can be reduced, and since the number of logic stages can be reduced, the delay time can be shortened and the operating speed of the circuit can be improved.
【０００７】[0007]
【実施例】図１には、本発明を２電源方式の論理ＬＳＩ
におけるレベル変換回路に適用した場合の一実施例が示
されている。この実施例の出力バッファの最終出力段１
は、＋５Ｖのような高い電源電圧端子ＶｃｃＨとＧＮＤ
（接地点）との間に２つのＮチャネル型ＭＯＳＦＥＴ
Ｑ１，Ｑ２が直列接続されてなり、２つのＭＯＳＦＥＴ
Ｑ１，Ｑ２の接続ノードｎ0が出力端子ＯＵＴに接続さ
れている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a logic LSI of a dual power supply system according to the present invention.
One example is shown when applied to the level conversion circuit in FIG. Final output stage 1 of the output buffer of this embodiment
Is a high power voltage terminal VccH such as + 5V and GND
Two N-channel MOSFETs between (ground point)
Two MOSFETs with Q1 and Q2 connected in series
Q1, Q2 of the connection node n 0 is connected to the output terminal OUT.
【０００８】この実施例では、上記出力ＭＯＳＦＥＴ
Ｑ１，Ｑ２のゲート制御信号を形成する論理部は、アウ
トイネーブル信号ＯＥが一方の入力端子に供給され他方
の入力端子に出力データ信号Ｄ，Ｄ’が供給された出力
状態制御用ＮＡＮＤゲートＧ１，Ｇ２と、このＮＡＮＤ
ゲートＧ１，Ｇ２と上記出力ＭＯＳＦＥＴＱ１，Ｑ２の
ゲート端子との間に挿入されたレベル変換回路ＬＣ１，
ＬＣ２とにより構成されている。In this embodiment, the output MOSFET described above is used.
The logic unit that forms the gate control signals of Q1 and Q2 includes an output state control NAND gate G1 in which the output enable signal OE is supplied to one input terminal and output data signals D and D ′ are supplied to the other input terminal. G2 and this NAND
A level conversion circuit LC1, inserted between the gates G1 and G2 and the gate terminals of the output MOSFETs Q1 and Q2.
And LC2.
【０００９】上記レベル変換回路ＬＣ１，ＬＣ２は、そ
れぞれ複合論理ゲートＧ１１とＮＯＲゲートＧ１２の入
出力端子が交差結合されたラッチ回路により構成されて
いる。そして、これらの複合論理ゲートＧ１１とＮＯＲ
ゲートＧ１２は、出力段１と同様高い電源電圧ＶｃｃＨ
で駆動され、上記ＮＡＮＤゲートＧ１，Ｇ２は低い電源
電圧ＶｃｃＬで駆動されるようにされている。これによ
って、ＮＡＮＤゲートＧ１，Ｇ２の出力が３．３Ｖのよ
うなハイレベルになったとき、ラッチ回路内部で帰還が
かかってＮＯＲゲートＧ１２の他方の入力端子に５Ｖの
電圧が印加されてＮＯＲゲートＧ１２のＶｃｃ側のＰ−
ＭＯＳＦＥＴが完全にオフされ、貫通電流が流れるのが
防止されると共に、出力ＭＯＳＦＥＴ Ｑ１，Ｑ２もオ
フの際にゲート端子が接地電位に固定されて完全にオフ
されるようになる。The level conversion circuits LC1 and LC2 are each composed of a latch circuit in which the input / output terminals of the composite logic gate G11 and the NOR gate G12 are cross-coupled. Then, these composite logic gate G11 and NOR
The gate G12 has a high power supply voltage VccH as in the output stage 1.
The NAND gates G1 and G2 are driven by a low power supply voltage VccL. As a result, when the outputs of the NAND gates G1 and G2 become a high level such as 3.3V, feedback is applied inside the latch circuit and a voltage of 5V is applied to the other input terminal of the NOR gate G12 and the NOR gate G12 is applied. P12 on the Vcc side of G12
The MOSFET is completely turned off, a through current is prevented from flowing, and when the output MOSFETs Q1 and Q2 are also turned off, the gate terminals are fixed to the ground potential and completely turned off.
【００１０】また、特に制限されないがこの実施例で
は、出力端子ＯＵＴに負の電圧が印加されたとき出力Ｍ
ＯＳＦＥＴ Ｑ１がオン状態にされて電源電圧Ｖｃｃか
ら出力端子ＯＵＴに向かって大きな電流が流れるのを防
止するため、出力ノードｎ0と出力ＭＯＳＦＥＴ Ｑ１
のゲート端子との間に、カット用ＭＯＳＦＥＴ Ｑｃが
設けられている。Although not particularly limited, in this embodiment, when a negative voltage is applied to the output terminal OUT, the output M
In order to prevent a large current from flowing from the power supply voltage Vcc to the output terminal OUT by turning on the OSFET Q1, the output node n 0 and the output MOSFET Q1 are prevented.
A cutting MOSFET Qc is provided between the gate terminal and the gate terminal.
【００１１】図２には、上記レベル変換回路ＬＣ１，Ｌ
Ｃ２を構成する複合論理ゲートＧ１１の具体的回路例が
示されている。すなわち、この複合論理ゲートＧ１１
は、通常のＮＡＮＤゲートを構成する並列形態のＰ−Ｍ
ＯＳＦＥＴ Ｑ１１，Ｑ１２と直列形態のＮ−ＭＯＳＦ
ＥＴ Ｑ１３，Ｑ１４とともに、上記Ｐ−ＭＯＳＦＥＴ
Ｑ１１，Ｑ１２の共通ドレイン端子と出力ノードｎ1
との間に直列接続されたＰ−ＭＯＳＦＥＴ Ｑ１５と、
出力ノードｎ1と接地点との間に上記Ｎ−ＭＯＳＦＥＴ
Ｑ１３，Ｑ１４と並列に接続されたＮ−ＭＯＳＦＥＴ
Ｑ１６とを備えてなる。この複合論理ゲートＧ１１に
おいて、Ｉ１，Ｉ２はＮＡＮＤ入力、Ｉ３はＮＯＲ入力
である。FIG. 2 shows the above level conversion circuits LC1 and L.
A specific circuit example of the composite logic gate G11 forming C2 is shown. That is, this composite logic gate G11
Is a parallel type P-M that constitutes a normal NAND gate.
N-MOSF in series with OSFETs Q11 and Q12
ET Q13 and Q14 together with the P-MOSFET
Common drain terminal of Q11 and Q12 and output node n 1
A P-MOSFET Q15 connected in series between
The N-MOSFET is provided between the output node n 1 and the ground point.
N-MOSFET connected in parallel with Q13 and Q14
And Q16. In this composite logic gate G11, I1 and I2 are NAND inputs and I3 is a NOR input.
【００１２】上記複合論理ゲートＧ１１を使用すること
により、図１のレベル変換回路ＬＣ１，ＬＣ２は、図７
に示されている回路に比べてインバータＩＮＶ３がない
分だけ信号の遅延時間が短くなる。すなわち、図７の回
路では、論理ゲートＧ１，Ｇ２から出力ＭＯＳＦＥＴ
Ｑ１，Ｑ２までのゲート段数が３段であるのに対し、図
７の回路では、論理ゲートＧ１，Ｇ２から出力ＭＯＳＦ
ＥＴ Ｑ１，Ｑ２までのゲート段数が２段であるため、
動作速度が速くなる。しかも、図７のレベル変換回路Ｌ
Ｃ１（ＬＣ２）は、インバータＩＮＶ３とＮＯＲゲート
を構成するＭＯＳＦＥＴを別々のウェル領域内に形成す
るため占有面積が大きくなるのに対し、図１のレベル変
換回路ＬＣ１（ＬＣ２）は、複合論理ゲートＧ１１を構
成する同一導電型のＭＯＳＦＥＴをすべて同一のウェル
領域内に形成できるため、回路の占有面積を低減させる
ことができる。By using the composite logic gate G11, the level conversion circuits LC1 and LC2 shown in FIG.
As compared with the circuit shown in FIG. 1, the signal delay time is shortened by the amount of the inverter INV3 not provided. That is, in the circuit of FIG. 7, the logic gates G1 and G2 output MOSFETs.
The number of gate stages up to Q1 and Q2 is three, whereas in the circuit of FIG. 7, the logic gates G1 and G2 are connected to the output MOSF.
Since the number of gate stages up to ET Q1 and Q2 is 2,
The operation speed becomes faster. Moreover, the level conversion circuit L of FIG.
The C1 (LC2) occupies a large area because the inverter INV3 and the MOSFET forming the NOR gate are formed in separate well regions, whereas the level conversion circuit LC1 (LC2) in FIG. 1 has a complex logic gate G11. Since all the MOSFETs of the same conductivity type constituting the above can be formed in the same well region, the area occupied by the circuit can be reduced.
【００１３】図３〜図５には、レベル変換回路に論理機
能を持たせた本発明の他の実施例が示されている。上記
実施例では、出力バッファ回路に好適なレベル変換回路
について説明したが、図３〜図５の論理機能付きレベル
変換回路は、異なる電源電圧で動作する論理回路間で信
号を伝達する場合に利用して好適である。このうち、図
３の回路は、ラッチ回路の一方のゲート回路Ｇ１１を３
入力ＮＯＲゲートとしたもので、論理ゲートＧ１１，Ｇ
１２の電源電圧として高電源電圧ＶｃｃＨを供給し、前
段の論理ゲートＧ１の電源電圧として低電源電圧Ｖｃｃ
Ｌを供給するようにして、論理機能として入力Ｘ，Ｙに
対し論理和（Ｘ＋Ｙ）をとりかつ出力ハイレベルとして
ＶｃｃＨレベルの信号Ｚを出力するように構成されてい
る。FIGS. 3 to 5 show another embodiment of the present invention in which the level conversion circuit has a logical function. Although the level conversion circuit suitable for the output buffer circuit has been described in the above embodiment, the level conversion circuit with logical functions shown in FIGS. 3 to 5 is used when signals are transmitted between logic circuits operating at different power supply voltages. Is suitable. Of these, in the circuit of FIG. 3, one gate circuit G11 of the latch circuit is
It is an input NOR gate, and has logic gates G11 and G.
The high power supply voltage VccH is supplied as the power supply voltage of 12 and the low power supply voltage Vcc is supplied as the power supply voltage of the preceding logic gate G1.
By supplying L, the logical function is to take the logical sum (X + Y) with respect to the inputs X and Y, and the signal Z of VccH level is output as the output high level.
【００１４】一方、図４の回路は、ＲＳフリップフロッ
プに適用したもので、低電源電圧ＶｃｃＬで駆動される
ＮＯＲゲートＧ２１とＧ２２からなるラッチ回路の次段
に高電源電圧ＶｃｃＨで駆動されるＮＯＲゲートＧ３
１，Ｇ３２からなるラッチ回路を接続して、０−Ｖｃｃ
Ｌレベルの入力信号を０−ＶｃｃＨレベルの信号Ｑを変
換して出力するように構成されている。On the other hand, the circuit of FIG. 4 is applied to an RS flip-flop, and NOR driven by a high power supply voltage VccH is provided next to a latch circuit composed of NOR gates G21 and G22 driven by a low power supply voltage VccL. Gate G3
0-Vcc by connecting the latch circuit consisting of 1, G32.
The input signal of L level is converted into the signal Q of 0-VccH level and output.
【００１５】また、図５の回路は、同期型フリップフロ
ップに適用したもので、低電源電圧ＶｃｃＬで駆動され
る制御用ＮＯＲゲートＧ２１とＧ２２の次段に高電源電
圧ＶｃｃＨで駆動されるＮＯＲゲートＧ３１，Ｇ３２か
らなるラッチ回路を接続して、０−ＶｃｃＬレベルの入
力信号を０−ＶｃｃＨレベルの信号Ｑに変換して出力す
るように構成されている。なお、上記実施例では、電源
電圧が正である場合のレベル変換回路について説明した
が、この発明はそれに限定されず、電源電圧が負である
場合にも同様に適用することができる。The circuit of FIG. 5 is applied to a synchronous flip-flop, and NOR gates driven by a high power supply voltage VccH are provided next to the control NOR gates G21 and G22 driven by a low power supply voltage VccL. A latch circuit composed of G31 and G32 is connected to convert an input signal of 0-VccL level to a signal Q of 0-VccH level and output the signal Q. In addition, although the level conversion circuit in the case where the power supply voltage is positive has been described in the above embodiments, the present invention is not limited to this, and can be similarly applied to the case where the power supply voltage is negative.
【００１６】以上説明したように、上記実施例は、低い
電源電圧で動作する論理回路と高い電源電圧で動作する
論理回路との間に、低い電源電圧で動作する論理部の次
段に高い電源電圧で動作するラッチ回路部が接続されて
なるレベル変換回路を接続してなるので、レベル変換回
路の構成が簡略化され、素子の数を減らすことができる
とともにレイアウトにおいて同一ウェル内にレベル変換
回路を構成するＭＯＳＦＥＴを形成することができるた
め占有面積を減少させることができ、また論理段数を少
なくすることができるため遅延時間も短くなり、回路の
動作速度を向上させることができるという効果がある。As described above, in the above embodiment, the high power supply is provided in the next stage of the logic unit operating at the low power supply voltage between the logic circuit operating at the low power supply voltage and the logic circuit operating at the high power supply voltage. Since the level conversion circuit is formed by connecting the latch circuit section that operates with voltage, the configuration of the level conversion circuit is simplified, the number of elements can be reduced, and the level conversion circuit can be arranged in the same well in the layout. Since it is possible to form the MOSFET that constitutes the circuit, the occupied area can be reduced, and the number of logic stages can be reduced, so that the delay time can be shortened and the operation speed of the circuit can be improved. ..
【００１７】以上本発明者によってなされた発明を実施
例に基づき具体的に説明したが、本発明は上記実施例に
限定されるものではなく、その要旨を逸脱しない範囲で
種々変更可能であることはいうまでもない。例えば、上
記実施例では低い電源電圧（接地電位）を基準にしてレ
ベル変換を行なっているが、高い電源電圧を基準にして
レベル変換を行なうように回路を構成することも可能で
ある。以上の説明では主として本発明者によってなされ
た発明をその背景となった利用分野である２電源で動作
する論理集積回路に適用した場合について説明したが、
この発明はそれに限定されるものでなく、３電源その他
複数電源の論理集積回路一般に利用することができる。Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, although the level conversion is performed with reference to the low power supply voltage (ground potential) in the above embodiment, the circuit can be configured to perform the level conversion with reference to the high power supply voltage. In the above description, the case where the invention made by the present inventor is mainly applied to a logic integrated circuit which operates with two power sources, which is the field of application of the background, has been described.
The present invention is not limited to this, and can be applied to a logic integrated circuit having three power supplies and a plurality of power supplies in general.
【００１８】[0018]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば下記
のとおりである。すなわち、電源電圧の低い回路によっ
て電源電圧の高い回路を動作させる場合に、占有面積が
小さく遅延時間も短いレベル変換回路を実現することが
できる。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, when operating a circuit having a high power supply voltage with a circuit having a low power supply voltage, a level conversion circuit having a small occupied area and a short delay time can be realized.
【図１】本発明に係るレベル変換回路を備えた出力バッ
ファ回路の一実施例を示す回路構成図である。FIG. 1 is a circuit configuration diagram showing an embodiment of an output buffer circuit including a level conversion circuit according to the present invention.
【図２】図１のレベル変換回路を構成する複合論理ゲー
トの一例を示す回路図である。FIG. 2 is a circuit diagram showing an example of a composite logic gate that constitutes the level conversion circuit of FIG.
【図３】本発明に係るレベル変換回路の他の実施例を示
す回路構成図である。FIG. 3 is a circuit configuration diagram showing another embodiment of the level conversion circuit according to the present invention.
【図４】本発明に係るレベル変換回路の他の実施例を示
す回路図である。FIG. 4 is a circuit diagram showing another embodiment of the level conversion circuit according to the present invention.
【図５】本発明に係るレベル変換回路の他の実施例を示
す回路図である。FIG. 5 is a circuit diagram showing another embodiment of the level conversion circuit according to the present invention.
【図６】従来の出力バッファ回路の一例を示す回路構成
図である。FIG. 6 is a circuit configuration diagram showing an example of a conventional output buffer circuit.
【図７】従来のレベル変換回路を備えた出力バッファ回
路の一実施例を示す回路構成図である。FIG. 7 is a circuit configuration diagram showing an embodiment of an output buffer circuit including a conventional level conversion circuit.
１ 出力段 ＬＣ１，ＬＣ２ レベル変換回路 Ｇ１１，Ｇ１２ 複合論理ゲート ＶｃｃＨ 高い電源電圧 ＶｃｃＬ 低い電源電圧 Ｇ１，Ｇ２，Ｇ２１，Ｇ２２ 論理部を構成する論理ゲ
ート Ｇ１１，Ｇ１２，Ｇ３１，Ｇ３２ ラッチ回路部を構成
する論理ゲート1 output stage LC1, LC2 level conversion circuit G11, G12 composite logic gate VccH high power supply voltage VccL low power supply voltage G1, G2, G21, G22 logic gates constituting a logic section G11, G12, G31, G32 constituting a latch circuit section Logic gate
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 7342−4Ｍ Ｈ０１Ｌ 27/08 ３２１ Ｋ (72)発明者 宮武 伸一 東京都小平市上水本町５丁目20番１号 日 立超エル・エス・アイ・エンジニアリング 株式会社内─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification number Reference number within the agency FI Technical display location 7342-4M H01L 27/08 321 K (72) Inventor Shinichi Miyatake 5, Kamimizumoto-cho, Kodaira-shi, Tokyo No. 20-1 Hitate Super LSI Engineering Co., Ltd.
Claims (3)
電源電圧で動作する論理回路との間に、低い電源電圧で
動作する論理部の次段に高い電源電圧で動作するラッチ
回路部が接続されてなるレベル変換回路が設けられてい
ることを特徴とする論理集積回路。1. A latch circuit section operating at a high power supply voltage is connected to the next stage of a logic section operating at a low power supply voltage between a logic circuit operating at a low power supply voltage and a logic circuit operating at a high power supply voltage. A logic integrated circuit, characterized in that a level conversion circuit is provided.
ゲートは、複合論理回路で構成されていることを特徴と
する請求項１記載の論理集積回路。2. The logic integrated circuit according to claim 1, wherein one of the logic gates forming the latch circuit section is formed of a composite logic circuit.
は、電源電圧端子間に直列接続された一対のＭＯＳＦＥ
Ｔからなる出力回路であることを特徴とする請求項１ま
たは２記載の論理集積回路。3. The logic circuit operating at a high power supply voltage comprises a pair of MOSFEs connected in series between power supply voltage terminals.
3. The logic integrated circuit according to claim 1, which is an output circuit made of T.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3226888A JPH0567963A (en) | 1991-09-06 | 1991-09-06 | Integrated logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3226888A JPH0567963A (en) | 1991-09-06 | 1991-09-06 | Integrated logic circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0567963A true JPH0567963A (en) | 1993-03-19 |
Family
ID=16852158
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3226888A Pending JPH0567963A (en) | 1991-09-06 | 1991-09-06 | Integrated logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0567963A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06343034A (en) * | 1993-06-01 | 1994-12-13 | Nippon Motorola Ltd | Driver device using complementary fet |
| JPH07177019A (en) * | 1993-04-15 | 1995-07-14 | Micron Semiconductor Inc | Improved type inversion output driving circuit that reduces electron injection into substrate |
| US5517132A (en) * | 1994-01-19 | 1996-05-14 | Matsushita Electric Industrial Co., Ltd. | Logic synthesis method and semiconductor integrated circuit |
| EP0744704A2 (en) * | 1995-05-26 | 1996-11-27 | Matsushita Electric Industrial Co., Ltd. | Logic synthesis method, semiconductor integrated circuit and arithmetic circuit |
| JPH09121151A (en) * | 1995-08-18 | 1997-05-06 | Samsung Electron Co Ltd | Data output buffer |
| JP2001144603A (en) * | 1999-11-18 | 2001-05-25 | Oki Micro Design Co Ltd | Level shifter circuit and data output circuit including it |
| JP2003188278A (en) * | 2002-11-01 | 2003-07-04 | Sharp Corp | Semiconductor device |
| KR100469762B1 (en) * | 2002-07-16 | 2005-02-02 | 매그나칩 반도체 유한회사 | C-gate circuit |
| DE10047451B4 (en) * | 1999-09-28 | 2008-01-03 | Samsung Electronics Co., Ltd., Suwon | Data output circuit for a semiconductor device |
| US9941881B1 (en) | 2017-03-23 | 2018-04-10 | Qualcomm Incorporated | Apparatus and method for latching data including AND-NOR or OR-NAND gate and feedback paths |
| CN112383299A (en) * | 2020-10-26 | 2021-02-19 | 中车株洲电力机车研究所有限公司 | Signal logic conversion circuit |
-
1991
- 1991-09-06 JP JP3226888A patent/JPH0567963A/en active Pending
Cited By (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07177019A (en) * | 1993-04-15 | 1995-07-14 | Micron Semiconductor Inc | Improved type inversion output driving circuit that reduces electron injection into substrate |
| JPH06343034A (en) * | 1993-06-01 | 1994-12-13 | Nippon Motorola Ltd | Driver device using complementary fet |
| USRE38152E1 (en) | 1994-01-19 | 2003-06-24 | Matsushita Electric Industrial Co., Ltd. | Logic synthesis method and semiconductor integrated circuit |
| US5517132A (en) * | 1994-01-19 | 1996-05-14 | Matsushita Electric Industrial Co., Ltd. | Logic synthesis method and semiconductor integrated circuit |
| USRE37475E1 (en) | 1994-01-19 | 2001-12-18 | Matsushita Electric Industrial Co., Ltd. | Logic synthesis method and semiconductor integrated circuit |
| EP0863471A3 (en) * | 1994-01-19 | 1999-02-17 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit with two supply voltages |
| EP0862127A2 (en) * | 1994-01-19 | 1998-09-02 | Matsushita Electric Industrial Co., Ltd. | Method of designing semiconductor integrated circuit |
| EP0863472A2 (en) * | 1994-01-19 | 1998-09-09 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit with two supply voltage levels |
| EP0863471A2 (en) * | 1994-01-19 | 1998-09-09 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit with two supply voltages |
| EP0863472A3 (en) * | 1994-01-19 | 1999-02-10 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit with two supply voltage levels |
| EP0862127A3 (en) * | 1994-01-19 | 1999-02-17 | Matsushita Electric Industrial Co., Ltd. | Method of designing semiconductor integrated circuit |
| EP0955594A2 (en) * | 1995-05-26 | 1999-11-10 | Matsushita Electric Industrial Co., Ltd. | Arithmetic circuit with two different voltage levels |
| US5926396A (en) * | 1995-05-26 | 1999-07-20 | Matsushita Electric Industrial Co., Ltd. | Logic synthesis method, semiconductor integrated circuit and arithmetic circuit |
| EP0744704A2 (en) * | 1995-05-26 | 1996-11-27 | Matsushita Electric Industrial Co., Ltd. | Logic synthesis method, semiconductor integrated circuit and arithmetic circuit |
| EP0744704A3 (en) * | 1995-05-26 | 1998-04-08 | Matsushita Electric Industrial Co., Ltd. | Logic synthesis method, semiconductor integrated circuit and arithmetic circuit |
| US5978573A (en) * | 1995-05-26 | 1999-11-02 | Matsushita Electric Industrial Co.Ltd. | Logic synthesis method, semiconductor integrated circuit and arithmetic circuit |
| EP0955594A3 (en) * | 1995-05-26 | 2002-04-10 | Matsushita Electric Industrial Co., Ltd. | Arithmetic circuit with two different voltage levels |
| EP1335309A1 (en) * | 1995-05-26 | 2003-08-13 | Matsushita Electric Industrial Co., Ltd. | Method of designing a semiconductor integrated circuit |
| JPH09121151A (en) * | 1995-08-18 | 1997-05-06 | Samsung Electron Co Ltd | Data output buffer |
| DE10047451B4 (en) * | 1999-09-28 | 2008-01-03 | Samsung Electronics Co., Ltd., Suwon | Data output circuit for a semiconductor device |
| JP2001144603A (en) * | 1999-11-18 | 2001-05-25 | Oki Micro Design Co Ltd | Level shifter circuit and data output circuit including it |
| KR100469762B1 (en) * | 2002-07-16 | 2005-02-02 | 매그나칩 반도체 유한회사 | C-gate circuit |
| JP2003188278A (en) * | 2002-11-01 | 2003-07-04 | Sharp Corp | Semiconductor device |
| US9941881B1 (en) | 2017-03-23 | 2018-04-10 | Qualcomm Incorporated | Apparatus and method for latching data including AND-NOR or OR-NAND gate and feedback paths |
| CN112383299B (en) * | 2020-10-26 | 2024-04-02 | 中车株洲电力机车研究所有限公司 | Signal logic conversion circuit |
| CN112383299A (en) * | 2020-10-26 | 2021-02-19 | 中车株洲电力机车研究所有限公司 | Signal logic conversion circuit |
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