CN112383299B - Signal logic conversion circuit - Google Patents
Signal logic conversion circuit Download PDFInfo
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- CN112383299B CN112383299B CN202011158989.0A CN202011158989A CN112383299B CN 112383299 B CN112383299 B CN 112383299B CN 202011158989 A CN202011158989 A CN 202011158989A CN 112383299 B CN112383299 B CN 112383299B
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- 238000006243 chemical reaction Methods 0.000 title claims abstract description 60
- 239000003990 capacitor Substances 0.000 claims description 16
- 230000010354 integration Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 8
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000012423 maintenance Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
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- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Conversion In General (AREA)
Abstract
The invention provides a signal logic conversion circuit, which comprises an upper tube driving unit, wherein a first input end of the upper tube driving unit is connected with a first pulse input signal, a second input end of the upper tube driving unit is connected with a direct current input voltage, and a third input end of the upper tube driving unit is connected with an enabling signal and is used for outputting a first pulse output signal according to the first pulse input signal, the direct current input voltage and the enabling signal so as to drive an upper IGBT tube of a converter; and the first input end of the lower tube driving unit is connected with the direct current input voltage, the second input end of the lower tube driving unit is connected with a second pulse input signal, and the third input end of the lower tube driving unit is connected with the enabling signal and is used for outputting a second pulse output signal according to the second pulse input signal, the direct current input voltage and the enabling signal so as to drive the lower IGBT tube of the converter. The signal logic conversion circuit has high integration level, simultaneously has the conversion function of the two-level and three-level driving signal logic circuits, and can select output signals to interlock or release the interlocking according to requirements.
Description
Technical Field
The disclosure relates to the field of electronic power control, in particular to a signal logic conversion circuit.
Background
At present, the semiconductor device is widely applied to two-level and three-level structures in the field of rail transit converters, but when the semiconductor device is applied to different main circuit structures, corresponding driving circuits are often required to be designed so as to ensure the normal operation of the semiconductor device, and different driving circuits are often configured for different converter modules. In addition, different application objects generally require the driver to have independent driving capability or output interlocking function, and if the drivers are independently developed, development and maintenance work of the drivers are further complicated.
Disclosure of Invention
In view of the foregoing, the present disclosure provides a signal logic conversion circuit.
The present disclosure provides a signal logic conversion circuit, comprising:
the upper tube driving unit is provided with a first input end connected with a first pulse input signal, a second input end connected with a direct current input voltage and a third input end connected with an enabling signal, and is used for outputting a first pulse output signal according to the first pulse input signal, the direct current input voltage and the enabling signal so as to drive an upper IGBT tube of the converter;
and the first input end of the lower tube driving unit is connected with the direct current input voltage, the second input end of the lower tube driving unit is connected with a second pulse input signal, and the third input end of the lower tube driving unit is connected with the enabling signal and is used for outputting a second pulse output signal according to the second pulse input signal, the direct current input voltage and the enabling signal so as to drive the lower IGBT tube of the converter.
According to an embodiment of the present disclosure, preferably, the upper tube driving unit includes a first nand gate, a second nand gate, a third nand gate, and a first capacitor;
the first input end of the first NAND gate is the first input end of the upper tube driving unit, the second input end of the first NAND gate and the first input end of the second NAND gate are the second input end of the upper tube driving unit, the output end of the first NAND gate is connected with the second input end of the second NAND gate, the output end of the second NAND gate is connected with the first input end of the third NAND gate, the second input end of the third NAND gate is the third input end of the upper tube driving unit, the output end of the third NAND gate is the output end of the upper tube driving unit, the first end of the first capacitor is connected with the second input end of the third NAND gate, and the second end of the first capacitor is grounded.
According to an embodiment of the present disclosure, preferably, the upper tube driving unit further includes a first resistor, a second resistor, a third resistor, and a fourth resistor;
the first resistor is connected between the first input end of the first NAND gate and the first input end of the upper tube driving unit, the second resistor is connected between the second input end of the first NAND gate and the second input end of the upper tube driving unit, the third resistor is connected between the output end of the second NAND gate and the first input end of the third NAND gate, and the fourth resistor is connected between the output end of the third NAND gate and the output end of the upper tube driving unit.
According to an embodiment of the present disclosure, preferably, the down tube driving unit includes a fourth nand gate, a fifth nand gate, and a sixth nand gate;
the first input end of the fourth NAND gate and the first input end of the fifth NAND gate are the first input end of the lower tube driving unit, the second input end of the fourth NAND gate is the second input end of the lower tube driving unit, the output end of the fourth NAND gate is connected with the second input end of the fifth NAND gate, the output end of the fifth NAND gate is connected with the first input end of the sixth NAND gate, the second input end of the sixth NAND gate is the third input end of the lower tube driving unit, and the output end of the sixth NAND gate is the output end of the lower tube driving unit.
According to an embodiment of the present disclosure, preferably, the lower tube driving unit further includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor;
the fifth resistor is connected between the first input end of the fourth NAND gate and the first input end of the lower tube driving unit, the sixth resistor is connected between the second input end of the fourth NAND gate and the second input end of the lower tube driving unit, the seventh resistor is connected between the first input end of the fifth NAND gate and the first input end of the lower tube driving unit, the eighth resistor is connected between the output end of the sixth NAND gate and the output end of the lower tube driving unit, and the ninth resistor is connected between the second input end of the sixth NAND gate and the third input end of the lower tube driving unit and between the second input end of the third NAND gate and the third input end of the upper tube driving unit.
According to an embodiment of the present disclosure, preferably, the upper tube driving unit further includes a seventh nand gate and an eighth nand gate;
the first input end of the seventh NAND gate is connected with the output end of the fifth NAND gate, the second input end of the seventh NAND gate is connected with the first input end of the first NAND gate, the output end of the seventh NAND gate is connected with the first input end of the fifth NAND gate, the first input end of the eighth NAND gate is connected with the output end of the seventh NAND gate, the second input end of the eighth NAND gate is connected with the first input end of the second NAND gate, and the output end of the eighth NAND gate is connected with the first input end of the third NAND gate so as to switch the two-level signal logic conversion circuit into the three-level signal logic conversion circuit.
According to an embodiment of the present disclosure, preferably, the upper tube driving unit further includes a twelfth resistor and a thirteenth resistor;
the twelfth resistor is connected between the output end of the seventh NAND gate and the first input end of the fifth NAND gate, and the thirteenth resistor is connected between the output end of the eighth NAND gate and the first input end of the third NAND gate.
According to an embodiment of the present disclosure, preferably, the upper tube driving unit includes a ninth nand gate, a tenth nand gate, an eleventh nand gate, and a second capacitor, and the lower tube driving unit includes a twelfth nand gate, a thirteenth nand gate, and a fourteenth nand gate;
the first input end of the ninth NAND gate is the first input end of the upper tube driving unit, the second input end of the ninth NAND gate is connected with the output end of the twelfth NAND gate, the output end of the ninth NAND gate is connected with the second input end of the tenth NAND gate, the first input end of the tenth NAND gate is the second input end of the upper tube driving unit, the output end of the tenth NAND gate is connected with the first input end of the eleventh NAND gate, the second input end of the eleventh NAND gate is the third input end of the upper tube driving unit, the output end of the eleventh NAND gate is the output end of the upper tube driving unit, the first end of the second capacitor is connected with the second input end of the eleventh NAND gate, and the second end of the second capacitor is grounded;
the first input end of the twelfth NAND gate is connected with the output end of the ninth NAND gate, the second input end of the twelfth NAND gate is the second input end of the down tube driving unit, the output end of the twelfth NAND gate is connected with the second input end of the thirteenth NAND gate, the first input end of the thirteenth NAND gate is the first input end of the down tube driving unit, the output end of the thirteenth NAND gate is connected with the first input end of the fourteenth NAND gate, the second input end of the fourteenth NAND gate is the third input end of the down tube driving unit, and the output end of the fourteenth NAND gate is the output end of the down tube driving unit.
According to an embodiment of the present disclosure, preferably, the upper tube driving unit further includes a twelfth resistor, a thirteenth resistor, a fourteenth resistor, and a fifteenth resistor, and the lower tube driving unit further includes a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, and a twentieth resistor;
the twelfth resistor is connected between the first input end of the ninth NAND gate and the first input end of the upper tube driving unit, the thirteenth resistor is connected between the second input end of the ninth NAND gate and the output end of the twelfth NAND gate, the fourteenth resistor is connected between the output end of the tenth NAND gate and the first input end of the eleventh NAND gate, and the fifteenth resistor is connected between the output end of the eleventh NAND gate and the output end of the upper tube driving unit;
the sixteenth resistor is connected between the first input end of the twelfth NAND gate and the output end of the ninth NAND gate, the seventeenth resistor is connected between the second input end of the twelfth NAND gate and the second input end of the lower tube driving unit, the eighteenth resistor is connected between the first input end of the thirteenth NAND gate and the first input end of the lower tube driving unit, the nineteenth resistor is connected between the output end of the fourteenth NAND gate and the output end of the lower tube driving unit, and the twentieth resistor is connected between the second input end of the fourteenth NAND gate and the third input end of the lower tube driving unit and between the second input end of the eleventh NAND gate and the third input end of the upper tube driving unit.
By adopting the technical scheme, at least the following technical effects can be achieved:
the invention provides a signal logic conversion circuit, which comprises an upper tube driving unit, wherein a first input end of the upper tube driving unit is connected with a first pulse input signal, a second input end of the upper tube driving unit is connected with a direct current input voltage, and a third input end of the upper tube driving unit is connected with an enabling signal and is used for outputting a first pulse output signal according to the first pulse input signal, the direct current input voltage and the enabling signal so as to drive an upper IGBT tube of a converter; and the first input end of the lower tube driving unit is connected with the direct current input voltage, the second input end of the lower tube driving unit is connected with a second pulse input signal, and the third input end of the lower tube driving unit is connected with the enabling signal and is used for outputting a second pulse output signal according to the second pulse input signal, the direct current input voltage and the enabling signal so as to drive the lower IGBT tube of the converter. The signal logic conversion circuit has high integration level, simultaneously has the conversion function of the two-level and three-level driving signal logic circuits, and can select the interlocking or the unlocking of the two-level output signals according to the requirements; can be copied into similar application scenes, and has higher economic value.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate the disclosure and together with the description serve to explain, but do not limit the disclosure. In the drawings:
FIG. 1 is a connection frame diagram of a signal logic conversion circuit according to an exemplary embodiment of the present disclosure;
FIG. 2 is a circuit diagram of a signal logic conversion circuit shown in an exemplary embodiment of the present disclosure;
FIG. 3 is a circuit diagram of another signal logic conversion circuit shown in an exemplary embodiment of the present disclosure;
FIG. 4 is a circuit diagram of another signal logic conversion circuit shown in an exemplary embodiment of the present disclosure;
FIG. 5 is a circuit diagram of another signal logic conversion circuit shown in an exemplary embodiment of the present disclosure;
FIG. 6 is a circuit diagram of another signal logic conversion circuit shown in an exemplary embodiment of the present disclosure;
fig. 7 is a circuit diagram of another signal logic conversion circuit shown in an exemplary embodiment of the present disclosure.
Detailed Description
The embodiments of the present disclosure will be described in detail below with reference to the drawings and examples, so as to solve the technical problem by applying technical means to the present disclosure, and the implementation process for achieving the corresponding technical effects can be fully understood and implemented accordingly. The embodiments of the present disclosure and various features in the embodiments may be combined with each other without conflict, and the formed technical solutions are all within the protection scope of the present disclosure.
It will be understood that, although the terms "first," "second," "third," etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
For a thorough understanding of the present disclosure, detailed structures will be presented in the following description in order to illustrate the technical solutions presented by the present disclosure. Preferred embodiments of the present disclosure are described in detail below, however, the present disclosure may have other implementations in addition to these detailed descriptions.
Example 1
Fig. 1 is a connection frame diagram of a signal logic conversion circuit 100 according to an exemplary embodiment of the present disclosure. As shown in fig. 1, the embodiment of the present disclosure provides a signal logic conversion circuit 100 including an upper pipe driving unit 101 and a lower pipe driving unit 102.
The upper tube driving unit 101 has a first input terminal connected to the first pulse input signal PWMAS, a second input terminal connected to the dc input voltage VIN, and a third input terminal connected to the Enable signal Enable, and is configured to output the first pulse output signal PWMOUTS according to the first pulse input signal PWMAS, the dc input voltage VIN, and the Enable signal Enable, so as to drive the upper IGBT tube of the current transformer.
The down tube driving unit 102 has a first input terminal connected to the dc input voltage VIN, a second input terminal connected to the second pulse input signal PWMAX, and a third input terminal connected to the Enable signal Enable, and is configured to output a second pulse output signal PWMOUTX according to the second pulse input signal PWMAX, the dc input voltage VIN, and the Enable signal Enable, so as to drive the lower IGBT tube of the converter.
Wherein VIN represents input voltage, and is used for power supply of the logic conversion circuit, and Enable represents Enable signal of the logic conversion circuit, and when Enable is high level, normal logic conversion mode is entered. PWMAS and PWMAX represent pulse input signals of the upper and lower pipes, respectively, and PWMOUTS and PWMOUTX correspond to output signals of the upper and lower pipe driving units after passing through the logic conversion circuit, respectively.
According to the conversion circuit, 3 different conversion circuit functions, namely a three-level driving signal conversion circuit, a driving signal conversion circuit without interlocking two levels and a driving signal conversion circuit with interlocking two levels, can be realized by selectively installing different resistors.
The embodiment of the disclosure provides a signal logic conversion circuit 100, which includes an upper tube driving unit 101, wherein a first input end of the upper tube driving unit is connected to a first pulse input signal PWMAS, a second input end of the upper tube driving unit is connected to a dc input voltage VIN, and a third input end of the upper tube driving unit is connected to an Enable signal Enable, and is configured to output a first pulse output signal PWMOUTS according to the first pulse input signal PWMAS, the dc input voltage VIN and the Enable signal Enable so as to drive an upper IGBT tube of a current transformer; the down tube driving unit 102 has a first input terminal connected to the dc input voltage VIN, a second input terminal connected to the second pulse input signal PWMAX, and a third input terminal connected to the Enable signal Enable, and is configured to output a second pulse output signal PWMOUTX according to the second pulse input signal PWMAX, the dc input voltage VIN, and the Enable signal Enable, so as to drive the lower IGBT tube of the converter. The signal logic conversion circuit has high integration level, simultaneously has the conversion function of the two-level and three-level driving signal logic circuits, and can select the interlocking or the unlocking of the two-level output signals according to the requirements; can be copied into similar application scenes, and has higher economic value.
Example two
On the basis of the first embodiment, the embodiment of the present disclosure provides a specific circuit structure of the signal logic conversion circuit 100.
Specifically, as shown in fig. 2, the upper tube driving unit 101 includes a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, and a first capacitor, and the lower tube driving unit 102 includes a fourth NAND gate NAND4, a fifth NAND gate NAND5, and a sixth NAND gate NAND6.
The first input end of the first NAND gate NAND1 is the first input end of the upper tube driving unit 101 (i.e. connected to the first pulse input signal PWMAS), the second input end of the first NAND gate NAND1 and the first input end of the second NAND gate NAND2 are the second input end of the upper tube driving unit 101 (i.e. the second input end of the first NAND gate NAND1 and the first input end of the second NAND gate NAND2 are connected to the dc input voltage VIN), the output end of the first NAND gate NAND1 is connected to the second input end of the second NAND gate NAND2, the output end of the second NAND gate NAND2 is connected to the first input end of the third NAND gate NAND3, the second input end of the third NAND gate NAND3 is the third input end of the upper tube driving unit 101 (i.e. connected to the Enable signal Enable), the output end of the third NAND gate NAND3 is the output end of the upper tube driving unit 101 (i.e. the first pulse output signal PWMOUTS is output), and the first end of the first capacitor is connected to the second input end of the third NAND gate NAND 3. The first input end of the fourth NAND gate NAND4 and the fifth NAND gate NAND5 is the first input end of the down tube driving unit 102 (i.e. connected to the dc input voltage VIN), the second input end of the fourth NAND gate NAND4 is the second input end of the down tube driving unit 102 (i.e. connected to the second pulse input signal PWMAX), the output end of the fourth NAND gate NAND4 is connected to the second input end of the fifth NAND gate NAND5, the output end of the fifth NAND gate NAND5 is connected to the first input end of the sixth NAND gate NAND6, the second input end of the sixth NAND gate NAND6 is the third input end of the down tube driving unit 102 (i.e. connected to the Enable signal Enable), and the output end of the sixth NAND gate NAND6 is the output end of the down tube driving unit 102 (i.e. outputting the second pulse output signal PWMOUTX).
In this embodiment, the logic conversion circuit is applied at two levels, and at this time, the upper and lower tube driving units 102 are in independent working states, the pulse signals output by the upper tube driving unit 101 and the lower tube driving unit 102 are independent, the two driving signals are not interlocked, and the output signals (i.e. the first pulse output signal PWMOUTS and the second pulse output signal PWMOUTX) can be at the same low level.
In addition, as shown in fig. 3, in the present embodiment, the upper tube driving unit 101 further includes a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4, and the lower tube driving unit 102 further includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9.
The first resistor R1 is connected between the first input end of the first NAND gate NAND1 and the first input end of the upper tube driving unit 101 (i.e., the first end of the first resistor R1 is connected to the first pulse input signal PWMAS, the second end is connected to the first input end of the first NAND gate NAND 1), the second resistor R2 is connected between the second input end of the first NAND gate NAND1 and the second input end of the upper tube driving unit 101 (i.e., the first end of the second resistor R2 is connected to the dc input voltage VIN, the second end is connected to the second input end of the first NAND gate NAND 1), the third resistor R3 is connected between the output end of the second NAND gate NAND2 and the first input end of the third NAND gate NAND3 (i.e., the first end of the third resistor R3 is connected to the output end of the second NAND gate NAND2, the second end is connected to the first input end of the third NAND gate NAND 3), and the fourth resistor R4 is connected between the output end of the third NAND gate NAND3 and the output end of the upper tube driving unit 101 (i.e., the first end of the third resistor R4 is connected to the output end of the third NAND gate output signal uts 101). The fifth resistor R5 is connected between the first input terminal of the fourth NAND gate NAND4 and the first input terminal of the lower tube driving unit 102 (i.e., the first terminal of the fifth resistor R5 is connected to the dc input voltage VIN, the second terminal is connected to the first input terminal of the fourth NAND gate NAND 4), the sixth resistor R6 is connected between the second input terminal of the fourth NAND gate NAND4 and the second input terminal of the lower tube driving unit 102 (i.e., the first terminal of the sixth resistor R6 is connected to the second pulse input signal PWMAX, the second terminal is connected to the second input terminal of the fourth NAND gate NAND 4), the seventh resistor R7 is connected between the first input terminal of the fifth NAND gate NAND5 and the first input terminal of the lower tube driving unit 102 (i.e., the first terminal of the seventh resistor R7 is connected to the dc input voltage VIN, the second terminal is connected to the first input terminal of the fifth NAND gate NAND 5), the eighth resistor R8 is connected between the output terminal of the sixth NAND gate NAND6 and the output terminal of the lower tube driving unit 102 (i.e., the first terminal of the eighth resistor R8 is connected to the second input terminal of the sixth NAND gate NAND6, and the second output terminal of the fifth resistor R6 is connected to the third input terminal of the fifth NAND gate NAND6, and the output terminal of the fifth resistor R9 is connected to the third input terminal of the fifth NAND gate NAND 6).
The circuit shown in fig. 3 is obtained by connecting resistors in series at proper positions on the basis of the circuit shown in fig. 2, and can play roles in voltage division and current limitation.
The embodiment of the disclosure provides a signal logic conversion circuit 100, which includes an upper tube driving unit 101, wherein a first input end of the upper tube driving unit is connected to a first pulse input signal PWMAS, a second input end of the upper tube driving unit is connected to a dc input voltage VIN, and a third input end of the upper tube driving unit is connected to an Enable signal Enable, and is configured to output a first pulse output signal PWMOUTS according to the first pulse input signal PWMAS, the dc input voltage VIN and the Enable signal Enable so as to drive an upper IGBT tube of a current transformer; the down tube driving unit 102 has a first input terminal connected to the dc input voltage VIN, a second input terminal connected to the second pulse input signal PWMAX, and a third input terminal connected to the Enable signal Enable, and is configured to output a second pulse output signal PWMOUTX according to the second pulse input signal PWMAX, the dc input voltage VIN, and the Enable signal Enable, so as to drive the lower IGBT tube of the converter. The signal logic conversion circuit has high integration level, is a conversion function of a two-level driving signal logic circuit, and signals output by the two driving units are mutually independent; can be copied into similar application scenes, and has higher economic value.
Example III
On the basis of the second embodiment, the embodiment of the present disclosure provides a specific circuit structure of the signal logic conversion circuit 200.
Specifically, as shown in fig. 4, the upper tube driving unit 201 includes a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a first capacitor, a seventh NAND gate NAND7, and an eighth NAND gate NAND8, and the lower tube driving unit 202 includes a fourth NAND gate NAND4, a fifth NAND gate NAND5, and a sixth NAND gate NAND6.
Wherein the first input end of the first NAND gate NAND1 is the first input end of the upper tube driving unit 201 (i.e. connected to the first pulse input signal PWMAS), the second input end of the first NAND gate NAND1 and the first input end of the second NAND gate NAND2 are the second input end of the upper tube driving unit 201 (i.e. the second input end of the first NAND gate NAND1 and the first input end of the second NAND gate NAND2 are connected to the dc input voltage VIN), the output end of the first NAND gate NAND1 is connected to the second input end of the second NAND gate NAND2, the output end of the second NAND gate NAND2 is connected to the first input end of the third NAND gate NAND3, the second input end of the third NAND gate NAND3 is the third input end of the upper tube driving unit 201 (i.e. connected to the Enable signal Enable), the output end of the third NAND gate NAND3 is the output end of the upper tube driving unit 201 (i.e. outputting the first pulse output signal PWMOUTS), the first end of the first capacitor is connected with the second input end of the third NAND gate NAND3, the second end of the first capacitor is grounded, the first input end of the seventh NAND gate NAND7 is connected with the output end of the fifth NAND gate NAND5, the second input end of the seventh NAND gate NAND7 is connected with the first input end of the first NAND gate NAND1 (namely, connected with a first pulse input signal PWMA), the output end of the seventh NAND gate NAND7 is connected with the first input end of the fifth NAND gate NAND5, the first input end of the eighth NAND gate NAND8 is connected with the output end of the seventh NAND gate NAND7, the second input end of the eighth NAND gate NAND8 is connected with the first input end of the second NAND gate NAND3 (namely, direct current input voltage VIN), and the output end of the eighth NAND gate NAND8 is connected with the first input end of the third NAND gate NAND3 so as to switch the two-level signal logic conversion circuit into the three-level signal logic conversion circuit. The first input end of the fourth NAND gate NAND4 and the fifth NAND gate NAND5 is the first input end of the down tube driving unit 202 (i.e. connected to the dc input voltage VIN), the second input end of the fourth NAND gate NAND4 is the second input end of the down tube driving unit 202 (i.e. connected to the second pulse input signal PWMAX), the output end of the fourth NAND gate NAND4 is connected to the second input end of the fifth NAND gate NAND5, the output end of the fifth NAND gate NAND5 is connected to the first input end of the sixth NAND gate NAND6, the second input end of the sixth NAND gate NAND6 is the third input end of the down tube driving unit 202 (i.e. connected to the Enable signal Enable), and the output end of the sixth NAND gate NAND6 is the output end of the down tube driving unit 202 (i.e. outputting the second pulse output signal PWMOUTX).
In this embodiment, the logic conversion circuit is applied in three levels, and at this time, the upper and lower tube driving units 202 are in independent working states, the pulse signals output by the upper tube driving unit 201 and the lower tube driving unit 202 are independent, the two paths of driving signals are not interlocked, and the output signals can be in low level. In a three-level application, the upper tube driving unit 201 is an outer tube driving unit, and the lower tube driving unit 202 is an inner tube driving unit. The seventh NAND gate NAND7 and the eighth NAND gate NAND8 are connected on the basis of the second embodiment, so that the two-level logic conversion circuit can be converted into the three-level logic conversion circuit.
In addition, as shown in fig. 5, in the present embodiment, the upper tube driving unit 201 further includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a tenth resistor R10, and an eleventh resistor R11, and the lower tube driving unit 202 further includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9.
The first resistor R1 is connected between the first input end of the first NAND gate NAND1 and the first input end of the upper tube driving unit 201 (i.e., the first end of the first resistor R1 is connected to the first pulse input signal PWMAS, the second end is connected to the first input end of the first NAND gate NAND 1), the second resistor R2 is connected between the second input end of the first NAND gate NAND1 and the second input end of the upper tube driving unit 201 (i.e., the first end of the second resistor R2 is connected to the direct current input voltage VIN, the second end is connected to the second input end of the first NAND gate NAND 1), the third resistor R3 is connected between the output end of the second NAND gate NAND2 and the first input end of the third NAND gate NAND3 (i.e., the first end of the third resistor R3 is connected to the output end of the second NAND gate NAND2, the second end is connected to the first input end of the third NAND gate NAND3, the fourth resistor R4 is connected to the output end of the third NAND gate NAND3, the fifth resistor R5 is connected to the output end of the fifth NAND gate NAND3, the output end of the fifth NAND gate NAND7 is connected to the output end of the fifth NAND gate NAND3, the fifth resistor R7 is connected to the output end of the fifth NAND gate 10 is connected to the output end of the fifth NAND gate NAND 3). The fifth resistor R5 is connected between the first input terminal of the fourth NAND gate NAND4 and the first input terminal of the lower tube driving unit 202 (i.e., the first terminal of the fifth resistor R5 is connected to the dc input voltage VIN, the second terminal is connected to the first input terminal of the fourth NAND gate NAND 4), the sixth resistor R6 is connected between the second input terminal of the fourth NAND gate NAND4 and the second input terminal of the lower tube driving unit 202 (i.e., the first terminal of the sixth resistor R6 is connected to the second pulse input signal PWMAX, the second terminal is connected to the second input terminal of the fourth NAND gate NAND 4), the seventh resistor R7 is connected between the first input terminal of the fifth NAND gate NAND5 and the first input terminal of the lower tube driving unit 202 (i.e., the first terminal of the seventh resistor R7 is connected to the dc input voltage VIN, the second terminal is connected to the first input terminal of the fifth NAND gate NAND 5), the eighth resistor R8 is connected between the output terminal of the sixth NAND gate NAND6 and the output terminal of the lower tube driving unit 202 (i.e., the first terminal of the eighth resistor R8 is connected to the second input terminal of the sixth NAND gate NAND6 and the second input terminal of the fifth resistor R9, and the third output terminal of the fifth resistor R6 is connected to the third input terminal of the fifth NAND gate NAND 6).
The circuit shown in fig. 5 is obtained by connecting resistors in series at proper positions on the basis of the circuit shown in fig. 4, and can play roles in voltage division and current limitation.
The embodiment of the disclosure provides a signal logic conversion circuit 200, which includes an upper tube driving unit 201, wherein a first input end of the upper tube driving unit is connected to a first pulse input signal PWMAS, a second input end of the upper tube driving unit is connected to a dc input voltage VIN, and a third input end of the upper tube driving unit is connected to an Enable signal Enable, and is configured to output a first pulse output signal PWMOUTS according to the first pulse input signal PWMAS, the dc input voltage VIN and the Enable signal Enable so as to drive an upper IGBT tube of a current transformer; the down tube driving unit 202 has a first input terminal connected to the dc input voltage VIN, a second input terminal connected to the second pulse input signal PWMAX, and a third input terminal connected to the Enable signal Enable, and is configured to output a second pulse output signal PWMOUTX according to the second pulse input signal PWMAX, the dc input voltage VIN, and the Enable signal Enable, so as to drive the lower IGBT tube of the converter. The signal logic conversion circuit has high integration level, is a three-level driving signal logic circuit conversion function, and signals output by the two driving units are mutually independent; can be copied into similar application scenes, and has higher economic value.
Example IV
On the basis of the first embodiment, the embodiment of the present disclosure provides another specific circuit structure of the signal logic conversion circuit 300.
Specifically, as shown in fig. 6, the upper tube driving unit 301 includes a ninth NAND gate NAND9, a tenth NAND gate NAND10, an eleventh NAND gate NAND11, and a second capacitor, and the lower tube driving unit 302 includes a twelfth NAND gate NAND12, a thirteenth NAND gate NAND13, and a fourteenth NAND gate NAND14.
The first input end of the ninth NAND gate NAND9 is the first input end of the upper tube driving unit 301 (i.e. connected to the first pulse input signal PWMAS), the second input end of the ninth NAND gate NAND9 is connected to the output end of the twelfth NAND gate NAND12, the output end of the ninth NAND gate NAND9 is connected to the second input end of the tenth NAND gate NAND10, the first input end of the tenth NAND gate NAND10 is the second input end of the upper tube driving unit 301 (i.e. connected to the dc input voltage VIN), the output end of the tenth NAND gate NAND10 is connected to the first input end of the eleventh NAND gate NAND11, the second input end of the eleventh NAND gate NAND11 is the third input end of the upper tube driving unit 301 (i.e. connected to the Enable signal Enable), the output end of the eleventh NAND gate NAND11 is the output end of the upper tube driving unit 301 (i.e. outputting the first pulse output signal PWMOUTS), and the first end of the second capacitor is connected to the second input end of the eleventh NAND gate NAND 11.
The first input end of the twelfth NAND gate NAND12 is connected to the output end of the ninth NAND gate NAND9, the second input end of the twelfth NAND gate NAND12 is the second input end of the down tube driving unit 302 (i.e. connected to the second pulse input signal PWMAX), the output end of the twelfth NAND gate NAND12 is connected to the second input end of the thirteenth NAND gate NAND13, the first input end of the thirteenth NAND gate NAND13 is the first input end of the down tube driving unit 302 (i.e. connected to the dc input voltage VIN), the output end of the thirteenth NAND gate NAND13 is connected to the first input end of the fourteenth NAND gate NAND14, the second input end of the fourteenth NAND gate NAND14 is the third input end of the down tube driving unit 302 (i.e. connected to the Enable signal Enable), and the output end of the fourteenth NAND gate NAND14 is the output end of the down tube driving unit 302 (i.e. outputting the second pulse output signal PWMOUTX).
In this embodiment, the logic conversion circuit is applied at two levels, and at this time, the upper and lower tube driving units 302 are in an interlocked state, the pulse signals output by the upper tube driving unit 301 and the lower tube driving unit 302 are associated with each other, and the output signals may not be allowed to be at the low level. In the present embodiment, since the second input terminal of the ninth NAND gate NAND9 is connected to the output terminal of the twelfth NAND gate NAND12 and the first input terminal of the twelfth NAND gate NAND12 is connected to the output terminal of the ninth NAND gate NAND9, the second input terminal of the ninth NAND gate NAND9 and the first input terminal of the twelfth NAND gate NAND12 can not be connected to the dc input voltage VIN any more, so as to avoid contradiction between the dc signal and the pulse signal of the corresponding NAND gate. Similarly, the second embodiment changes the wiring of the corresponding nand gate on the basis of the second embodiment, that is, the two-level logic conversion circuit in the unlocked state (independent state) can be converted into the two-level logic conversion circuit in the interlocked state.
In addition, as shown in fig. 7, in the present embodiment, the upper tube driving unit 301 further includes a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, and a fifteenth resistor R15, and the lower tube driving unit 302 further includes a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, and a twentieth resistor R20.
The twelfth resistor R12 is connected between the first input end of the ninth NAND gate 9 and the first input end of the upper tube driving unit 301 (i.e., the first end of the twelfth resistor R12 is connected to the first pulse input signal PWMAS, the second end is connected to the first input end of the ninth NAND gate NAND 9), the thirteenth resistor R13 is connected between the second input end of the ninth NAND gate NAND9 and the output end of the twelfth NAND gate NAND12 (i.e., the first end of the thirteenth resistor R13 is connected to the second input end of the ninth NAND gate NAND9, the second end is connected to the output end of the twelfth NAND gate NAND 12), the fourteenth resistor R14 is connected between the output end of the tenth NAND gate NAND10 and the first input end of the eleventh NAND gate NAND11 (i.e., the first end of the fourteenth resistor R14 is connected to the output end of the tenth NAND gate NAND10, the second end is connected to the first input end of the eleventh NAND gate NAND 11), and the fifteenth resistor R15 is connected between the output end of the eleventh NAND gate NAND11 and the output end of the upper tube driving unit 301 (i.e., the first end of the fifteenth resistor R15 is connected to the output end of the first output tube driving unit pws 11).
The sixteenth resistor R16 is connected between the first input terminal of the twelfth NAND gate 12 and the output terminal of the ninth NAND gate NAND9 (i.e., the first terminal of the sixteenth resistor R16 is connected to the output terminal of the ninth NAND gate NAND9, the second terminal is connected to the first input terminal of the twelfth NAND gate NAND 12), the seventeenth resistor R17 is connected between the second input terminal of the twelfth NAND gate NAND12 and the second input terminal of the down tube driving unit 302 (i.e., the first terminal of the seventeenth resistor R17 is connected to the second pulse input signal PWMAX, the second terminal is connected to the second input terminal of the twelfth NAND gate NAND 12), the eighteenth resistor R18 is connected between the first input terminal of the thirteenth NAND gate NAND13 and the first input terminal of the down tube driving unit 302 (i.e. the first terminal of the eighteenth resistor R18 VIN is connected to the dc input voltage, the second end is connected to the first input end of the thirteenth NAND gate NAND 13), the nineteenth resistor R19 is connected between the output end of the fourteenth NAND gate NAND14 and the output end of the down tube driving unit 302 (i.e., the first end of the nineteenth resistor R19 is connected to the output end of the fourteenth NAND gate NAND14, the second end is the output end of the down tube driving unit 302, and outputs the second pulse output signal PWMOUTX), the twentieth resistor R20 is connected between the second input end of the fourteenth NAND gate NAND14 and the third input end of the down tube driving unit 302, and between the second input end of the eleventh NAND gate NAND11 and the third input end of the up tube driving unit 301 (i.e., the first end of the twentieth resistor R20 is connected to the Enable signal Enable, and the second end is connected to the second input end of the fourteenth NAND gate NAND14 and the second input end of the eleventh NAND gate NAND 11).
The circuit shown in fig. 7 is obtained by connecting resistors in series at proper positions on the basis of the circuit shown in fig. 6, and can play roles of voltage division and current limitation.
The embodiment of the disclosure provides a signal logic conversion circuit 300, which includes an upper tube driving unit 301, wherein a first input end of the upper tube driving unit is connected to a first pulse input signal PWMAS, a second input end of the upper tube driving unit is connected to a dc input voltage VIN, and a third input end of the upper tube driving unit is connected to an Enable signal Enable, and is configured to output a first pulse output signal PWMOUTS according to the first pulse input signal PWMAS, the dc input voltage VIN and the Enable signal Enable so as to drive an upper IGBT tube of a current transformer; the down tube driving unit 302 has a first input terminal connected to the dc input voltage VIN, a second input terminal connected to the second pulse input signal PWMAX, and a third input terminal connected to the Enable signal Enable, and is configured to output a second pulse output signal PWMOUTX according to the second pulse input signal PWMAX, the dc input voltage VIN, and the Enable signal Enable, so as to drive the lower IGBT tube of the converter. The signal logic conversion circuit has high integration level, is a conversion function of a two-level driving signal logic circuit, and signals output by the two driving units are interlocked; can be copied into similar application scenes, and has higher economic value.
The foregoing is merely a preferred embodiment of the present disclosure, and is not intended to limit the present disclosure, so that various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure. While the embodiments of the present disclosure are described above, the disclosure is not limited to the embodiments employed for the convenience of understanding the present disclosure. Any person skilled in the art to which this disclosure pertains will appreciate that numerous modifications and variations in form and detail can be made without departing from the spirit and scope of the disclosure, but the scope of the disclosure is still subject to the scope of the appended claims.
Claims (3)
1. A signal logic conversion circuit, comprising:
the upper tube driving unit is provided with a first input end connected with a first pulse input signal, a second input end connected with a direct current input voltage and a third input end connected with an enabling signal, and is used for outputting a first pulse output signal according to the first pulse input signal, the direct current input voltage and the enabling signal so as to drive an upper IGBT tube of the converter;
the first input end of the lower tube driving unit is connected with the direct current input voltage, the second input end of the lower tube driving unit is connected with a second pulse input signal, and the third input end of the lower tube driving unit is connected with the enabling signal and used for outputting a second pulse output signal according to the second pulse input signal, the direct current input voltage and the enabling signal so as to drive a lower IGBT tube of the converter;
the upper tube driving unit comprises a first NAND gate, a second NAND gate, a third NAND gate and a first capacitor;
the first input end of the first NAND gate is the first input end of the upper tube driving unit, the second input end of the first NAND gate and the first input end of the second NAND gate are the second input end of the upper tube driving unit, the output end of the first NAND gate is connected with the second input end of the second NAND gate, the output end of the second NAND gate is connected with the first input end of the third NAND gate, the second input end of the third NAND gate is the third input end of the upper tube driving unit, the output end of the third NAND gate is the output end of the upper tube driving unit, the first end of the first capacitor is connected with the second input end of the third NAND gate, and the second end of the first capacitor is grounded;
the lower tube driving unit comprises a fourth NAND gate, a fifth NAND gate and a sixth NAND gate;
the first input end of the fourth NAND gate and the first input end of the fifth NAND gate are the first input end of the lower pipe driving unit, the second input end of the fourth NAND gate is the second input end of the lower pipe driving unit, the output end of the fourth NAND gate is connected with the second input end of the fifth NAND gate, the output end of the fifth NAND gate is connected with the first input end of the sixth NAND gate, the second input end of the sixth NAND gate is the third input end of the lower pipe driving unit, and the output end of the sixth NAND gate is the output end of the lower pipe driving unit;
the lower tube driving unit further comprises a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor and a ninth resistor;
the fifth resistor is connected between the first input end of the fourth NAND gate and the first input end of the lower tube driving unit, the sixth resistor is connected between the second input end of the fourth NAND gate and the second input end of the lower tube driving unit, the seventh resistor is connected between the first input end of the fifth NAND gate and the first input end of the lower tube driving unit, the eighth resistor is connected between the output end of the sixth NAND gate and the output end of the lower tube driving unit, and the ninth resistor is connected between the second input end of the sixth NAND gate and the third input end of the lower tube driving unit and between the second input end of the third NAND gate and the third input end of the upper tube driving unit;
the upper tube driving unit further comprises a seventh NAND gate and an eighth NAND gate;
the first input end of the seventh NAND gate is connected with the output end of the fifth NAND gate, the second input end of the seventh NAND gate is connected with the first input end of the first NAND gate, the output end of the seventh NAND gate is connected with the first input end of the fifth NAND gate, the first input end of the eighth NAND gate is connected with the output end of the seventh NAND gate, the second input end of the eighth NAND gate is connected with the first input end of the second NAND gate, and the output end of the eighth NAND gate is connected with the first input end of the third NAND gate so as to switch the two-level signal logic conversion circuit into the three-level signal logic conversion circuit.
2. The signal logic conversion circuit according to claim 1, wherein the upper tube driving unit further comprises a first resistor, a second resistor, a third resistor, and a fourth resistor;
the first resistor is connected between the first input end of the first NAND gate and the first input end of the upper tube driving unit, the second resistor is connected between the second input end of the first NAND gate and the second input end of the upper tube driving unit, the third resistor is connected between the output end of the second NAND gate and the first input end of the third NAND gate, and the fourth resistor is connected between the output end of the third NAND gate and the output end of the upper tube driving unit.
3. The signal logic conversion circuit according to claim 1, wherein the upper tube driving unit further comprises a tenth resistor and an eleventh resistor;
the tenth resistor is connected between the output end of the seventh NAND gate and the first input end of the fifth NAND gate, and the eleventh resistor is connected between the output end of the eighth NAND gate and the first input end of the third NAND gate.
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