CN112383299A - Signal logic conversion circuit - Google Patents

Signal logic conversion circuit Download PDF

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Publication number
CN112383299A
CN112383299A CN202011158989.0A CN202011158989A CN112383299A CN 112383299 A CN112383299 A CN 112383299A CN 202011158989 A CN202011158989 A CN 202011158989A CN 112383299 A CN112383299 A CN 112383299A
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nand gate
input end
driving unit
resistor
input
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CN112383299B (en
Inventor
张�荣
魏海山
谢舜蒙
田伟
朱武
荣春晖
刘杰
谭一帆
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CRRC Zhuzhou Institute Co Ltd
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CRRC Zhuzhou Institute Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Conversion In General (AREA)

Abstract

The utility model provides a signal logic conversion circuit, which comprises an upper tube driving unit, a first input end of which is connected with a first pulse input signal, a second input end of which is connected with a direct current input voltage, and a third input end of which is connected with an enable signal, and is used for outputting a first pulse output signal according to the first pulse input signal, the direct current input voltage and the enable signal so as to drive an upper side IGBT tube of a converter; and the first input end of the lower tube driving unit is connected with the direct current input voltage, the second input end of the lower tube driving unit is connected with a second pulse input signal, the third input end of the lower tube driving unit is connected with the enable signal, and the lower tube driving unit is used for outputting a second pulse output signal according to the second pulse input signal, the direct current input voltage and the enable signal so as to drive the lower side IGBT tube of the converter. The signal logic conversion circuit has high integration level, simultaneously has the conversion function of driving the signal logic circuit by two levels and three levels, and can select output signal interlock or release the interlock according to requirements.

Description

Signal logic conversion circuit
Technical Field
The disclosure relates to the field of electronic power control, in particular to a signal logic conversion circuit.
Background
At present, semiconductor devices are widely applied to two-level and three-level structures in the field of rail transit converters, corresponding driving circuits are often required to be designed when the semiconductor devices are applied to different main circuit structures so as to ensure normal work of the semiconductor devices, different driving circuits are often configured aiming at different converter modules at present, although the semiconductor devices are ensured to normally work in the main circuit structures in the mode, the driving plates are also more in demand variety, the circuit development and later maintenance in the early stage are more complicated, and the workload of the development and later maintenance of the driving is increased to a great extent. In addition, different application objects generally require drivers to have independent driving capability or output interlocking function, and if the drivers are separately and independently developed, development and maintenance of the drivers are more complicated.
Disclosure of Invention
In view of the above, the present disclosure provides a signal logic conversion circuit.
The present disclosure provides a signal logic conversion circuit, including:
the upper tube driving unit is connected with a first pulse input signal at a first input end, a direct current input voltage at a second input end and an enable signal at a third input end, and is used for outputting a first pulse output signal according to the first pulse input signal, the direct current input voltage and the enable signal so as to drive an upper IGBT tube of the converter;
and the first input end of the lower tube driving unit is connected with the direct current input voltage, the second input end of the lower tube driving unit is connected with a second pulse input signal, the third input end of the lower tube driving unit is connected with the enable signal, and the lower tube driving unit is used for outputting a second pulse output signal according to the second pulse input signal, the direct current input voltage and the enable signal so as to drive the lower side IGBT tube of the converter.
According to the embodiment of the present disclosure, preferably, the top tube driving unit includes a first nand gate, a second nand gate, a third nand gate, and a first capacitor;
the first input end of the first nand gate is the first input end of the top tube driving unit, the second input end of the first nand gate and the first input end of the second nand gate are the second input end of the top tube driving unit, the output end of the first nand gate is connected with the second input end of the second nand gate, the output end of the second nand gate is connected with the first input end of the third nand gate, the second input end of the third nand gate is the third input end of the top tube driving unit, the output end of the third nand gate is the output end of the top tube driving unit, the first end of the first capacitor is connected with the second input end of the third nand gate, and the second end of the first capacitor is grounded.
According to the embodiment of the present disclosure, preferably, the upper tube driving unit further includes a first resistor, a second resistor, a third resistor, and a fourth resistor;
the first resistor is connected between the first input end of the first nand gate and the first input end of the top tube driving unit, the second resistor is connected between the second input end of the first nand gate and the second input end of the top tube driving unit, the third resistor is connected between the output end of the second nand gate and the first input end of the third nand gate, and the fourth resistor is connected between the output end of the third nand gate and the output end of the top tube driving unit.
According to the embodiment of the present disclosure, preferably, the lower tube driving unit includes a fourth nand gate, a fifth nand gate, and a sixth nand gate;
the first input ends of the fourth nand gate and the fifth nand gate are the first input ends of the tube-down driving unit, the second input end of the fourth nand gate is the second input end of the tube-down driving unit, the output end of the fourth nand gate is connected with the second input end of the fifth nand gate, the output end of the fifth nand gate is connected with the first input end of the sixth nand gate, the second input end of the sixth nand gate is the third input end of the tube-down driving unit, and the output end of the sixth nand gate is the output end of the tube-down driving unit.
According to the embodiment of the present disclosure, preferably, the lower tube driving unit further includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor;
the fifth resistor is connected between the first input end of the fourth nand gate and the first input end of the lower tube driving unit, the sixth resistor is connected between the second input end of the fourth nand gate and the second input end of the lower tube driving unit, the seventh resistor is connected between the first input end of the fifth nand gate and the first input end of the lower tube driving unit, the eighth resistor is connected between the output end of the sixth nand gate and the output end of the lower tube driving unit, and the ninth resistor is connected between the second input end of the sixth nand gate and the third input end of the lower tube driving unit and between the second input end of the third nand gate and the third input end of the upper tube driving unit.
According to the embodiment of the present disclosure, preferably, the top tube driving unit further includes a seventh nand gate and an eighth nand gate;
the first input end of the seventh nand gate is connected with the output end of the fifth nand gate, the second input end of the seventh nand gate is connected with the first input end of the first nand gate, the output end of the seventh nand gate is connected with the first input end of the fifth nand gate, the first input end of the eighth nand gate is connected with the output end of the seventh nand gate, the second input end of the eighth nand gate is connected with the first input ends of the two nand gates, and the output end of the eighth nand gate is connected with the first input end of the third nand gate, so that the two-level signal logic conversion circuit is switched into a three-level signal logic conversion circuit.
According to an embodiment of the present disclosure, preferably, the upper tube driving unit further includes a twelfth resistor and a thirteenth resistor;
the twelfth resistor is connected between the output end of the seventh nand gate and the first input end of the fifth nand gate, and the thirteenth resistor is connected between the output end of the eighth nand gate and the first input end of the third nand gate.
According to the embodiment of the present disclosure, preferably, the upper tube driving unit includes a ninth nand gate, a tenth nand gate, an eleventh nand gate and a second capacitor, and the lower tube driving unit includes a twelfth nand gate, a thirteenth nand gate and a fourteenth nand gate;
a first input end of the ninth nand gate is a first input end of the top tube driving unit, a second input end of the ninth nand gate is connected to an output end of the twelfth nand gate, an output end of the ninth nand gate is connected to a second input end of the tenth nand gate, the first input end of the tenth nand gate is a second input end of the top tube driving unit, an output end of the tenth nand gate is connected to a first input end of the eleventh nand gate, the second input end of the eleventh nand gate is a third input end of the top tube driving unit, an output end of the eleventh nand gate is an output end of the top tube driving unit, a first end of the second capacitor is connected to a second input end of the eleventh nand gate, and a second end of the second capacitor is grounded;
a first input end of the twelfth nand gate is connected to an output end of the ninth nand gate, a second input end of the twelfth nand gate is a second input end of the lower tube driving unit, an output end of the twelfth nand gate is connected to a second input end of the thirteenth nand gate, the first input end of the thirteenth nand gate is a first input end of the lower tube driving unit, an output end of the thirteenth nand gate is connected to a first input end of the fourteenth nand gate, the second input end of the fourteenth nand gate is a third input end of the lower tube driving unit, and an output end of the fourteenth nand gate is an output end of the lower tube driving unit.
According to an embodiment of the present disclosure, preferably, the upper tube driving unit further includes a twelfth resistor, a thirteenth resistor, a fourteenth resistor, and a fifteenth resistor, and the lower tube driving unit further includes a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, and a twentieth resistor;
the twelfth resistor is connected between the first input end of the ninth nand gate and the first input end of the top tube driving unit, the thirteenth resistor is connected between the second input end of the ninth nand gate and the output end of the twelfth nand gate, the fourteenth resistor is connected between the output end of the tenth nand gate and the first input end of the eleventh nand gate, and the fifteenth resistor is connected between the output end of the eleventh nand gate and the output end of the top tube driving unit;
the sixteenth resistor is connected between the first input end of the twelfth nand gate and the output end of the ninth nand gate, the seventeenth resistor is connected between the second input end of the twelfth nand gate and the second input end of the lower tube driving unit, the eighteenth resistor is connected between the first input end of the thirteenth nand gate and the first input end of the lower tube driving unit, the nineteenth resistor is connected between the output end of the fourteenth nand gate and the output end of the lower tube driving unit, and the twentieth resistor is connected between the second input end of the fourteenth nand gate and the third input end of the lower tube driving unit and between the second input end of the eleventh nand gate and the third input end of the upper tube driving unit.
By adopting the technical scheme, the following technical effects can be at least achieved:
the utility model provides a signal logic conversion circuit, which comprises an upper tube driving unit, a first input end of which is connected with a first pulse input signal, a second input end of which is connected with a direct current input voltage, and a third input end of which is connected with an enable signal, and is used for outputting a first pulse output signal according to the first pulse input signal, the direct current input voltage and the enable signal so as to drive an upper side IGBT tube of a converter; and the first input end of the lower tube driving unit is connected with the direct current input voltage, the second input end of the lower tube driving unit is connected with a second pulse input signal, the third input end of the lower tube driving unit is connected with the enable signal, and the lower tube driving unit is used for outputting a second pulse output signal according to the second pulse input signal, the direct current input voltage and the enable signal so as to drive the lower side IGBT tube of the converter. The signal logic conversion circuit has high integration level, simultaneously has the conversion function of driving the signal logic circuit by two levels and three levels, and can select two-level output signals to interlock or release the interlock according to the requirement; can be copied to similar application scenes, and has higher economic value.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:
FIG. 1 is a connection block diagram of a signal logic conversion circuit shown in an exemplary embodiment of the present disclosure;
FIG. 2 is a circuit diagram of a signal logic conversion circuit shown in an exemplary embodiment of the present disclosure;
FIG. 3 is a circuit diagram of another signal logic conversion circuit shown in an exemplary embodiment of the present disclosure;
FIG. 4 is a circuit diagram of another signal logic conversion circuit shown in an exemplary embodiment of the present disclosure;
FIG. 5 is a circuit diagram of another signal logic conversion circuit shown in an exemplary embodiment of the present disclosure;
FIG. 6 is a circuit diagram of another signal logic conversion circuit shown in an exemplary embodiment of the present disclosure;
fig. 7 is a circuit diagram of another signal logic conversion circuit shown in an exemplary embodiment of the present disclosure.
Detailed Description
Embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and examples, so that how to apply technical means to solve technical problems and achieve the corresponding technical effects can be fully understood and implemented. The embodiments and the features of the embodiments of the present disclosure can be combined with each other without conflict, and the formed technical solutions are all within the protection scope of the present disclosure.
It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In order to provide a thorough understanding of the present disclosure, a detailed structure will be set forth in the following description in order to explain the technical solutions proposed by the present disclosure. The following detailed description of the preferred embodiments of the present disclosure, however, the present disclosure may have other embodiments in addition to these detailed descriptions.
Example one
Fig. 1 is a connection block diagram of a signal logic conversion circuit 100 according to an exemplary embodiment of the present disclosure. As shown in fig. 1, an embodiment of the present disclosure provides a signal logic converting circuit 100, which includes a top tube driving unit 101 and a bottom tube driving unit 102.
The upper tube driving unit 101 has a first input terminal connected to the first pulse input signal PWMAS, a second input terminal connected to the dc input voltage VIN, and a third input terminal connected to the Enable signal Enable, and is configured to output the first pulse output signal PWMOUTS according to the first pulse input signal PWMAS, the dc input voltage VIN, and the Enable signal Enable, so as to drive the upper IGBT tube of the converter.
And the lower tube driving unit 102, a first input end of which is connected with the direct current input voltage VIN, a second input end of which is connected with the second pulse input signal PWMAX, and a third input end of which is connected with the Enable signal Enable, is used for outputting a second pulse output signal PWMOUTX according to the second pulse input signal PWMAX, the direct current input voltage VIN and the Enable signal Enable, so as to drive the lower side IGBT tube of the converter.
Where VIN represents an input voltage for power supply of the logic conversion circuit, Enable represents an Enable signal of the logic conversion circuit, and when Enable is high, a normal logic conversion mode is entered. PWMAS and PWMAX represent pulse input signals of the upper and lower tubes, respectively, and PWMOUTS and PWMOUTX correspond to output signals of the upper and lower tube driving units after passing through the logic conversion circuit, respectively.
According to the conversion circuit, 3 different conversion circuit functions, namely a three-level driving signal conversion circuit, a non-interlocking two-level driving signal conversion circuit and an interlocking two-level driving signal conversion circuit, can be realized by selectively installing different resistors.
The disclosed embodiment provides a signal logic conversion circuit 100, which comprises a top tube driving unit 101, a first input end of which is connected with a first pulse input signal PWMAS, a second input end of which is connected with a direct current input voltage VIN, and a third input end of which is connected with an Enable signal Enable, and is used for outputting a first pulse output signal PWMOUTS according to the first pulse input signal PWMAS, the direct current input voltage VIN and the Enable signal Enable to drive an upper side IGBT tube of a converter; and the lower tube driving unit 102, a first input end of which is connected with the direct current input voltage VIN, a second input end of which is connected with the second pulse input signal PWMAX, and a third input end of which is connected with the Enable signal Enable, is used for outputting a second pulse output signal PWMOUTX according to the second pulse input signal PWMAX, the direct current input voltage VIN and the Enable signal Enable, so as to drive the lower side IGBT tube of the converter. The signal logic conversion circuit has high integration level, simultaneously has the conversion function of driving the signal logic circuit by two levels and three levels, and can select two-level output signals to interlock or release the interlock according to the requirement; can be copied to similar application scenes, and has higher economic value.
Example two
On the basis of the first embodiment, the embodiment of the present disclosure provides a specific circuit structure of the signal logic converting circuit 100.
Specifically, as shown in fig. 2, the top tube driving unit 101 includes a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3 and a first capacitor, and the bottom tube driving unit 102 includes a fourth NAND gate NAND4, a fifth NAND gate NAND5 and a sixth NAND gate NAND 6.
Wherein, the first input terminal of the first NAND gate NAND1 is the first input terminal of the top tube driving unit 101 (i.e. is connected with the first pulse input signal PWMAS), the second input terminal of the first NAND gate NAND1 and the first input terminal of the second NAND gate NAND2 are the second input terminal of the top tube driving unit 101 (i.e. the second input terminal of the first NAND gate NAND1 and the first input terminal of the second NAND gate NAND2 are connected with the dc input voltage VIN), the output terminal of the first NAND gate NAND1 is connected with the second input terminal of the second NAND gate NAND2, the output terminal of the second NAND gate NAND2 is connected with the first input terminal of the third NAND gate NAND3, the second input terminal of the third NAND gate 3 is the third input terminal of the top tube driving unit 101 (i.e. is connected with the Enable signal Enable), the output terminal of the third NAND gate 3 is the output terminal of the top tube driving unit 101 (i.e. outputs the first pulse output signal PWMOUTS), the first terminal of the, the second end of the first capacitor is grounded. The first input terminals of the fourth NAND gate 4 and the fifth NAND gate 5 are the first input terminal of the down tube driving unit 102 (i.e., connected to the dc input voltage VIN), the second input terminal of the fourth NAND gate 4 is the second input terminal of the down tube driving unit 102 (i.e., connected to the second pulse input signal PWMAX), the output terminal of the fourth NAND gate 4 is connected to the second input terminal of the fifth NAND gate NAND5, the output terminal of the fifth NAND gate 5 is connected to the first input terminal of the sixth NAND gate 6, the second input terminal of the sixth NAND gate 6 is the third input terminal of the down tube driving unit 102 (i.e., connected to the Enable signal Enable), and the output terminal of the sixth NAND gate 6 is the output terminal of the down tube driving unit 102 (i.e., outputting the second pulse output signal PWMOUTX).
In this embodiment, the logic conversion circuit is applied in two levels, and at this time, the upper tube driving unit 102 and the lower tube driving unit 102 are in an independent working state, the pulse signals output by the upper tube driving unit 101 and the lower tube driving unit 102 are independent from each other, the two driving signals are unlocked, and the output signals (i.e., the first pulse output signal PWMOUTS and the second pulse output signal PWMOUTX) can be at a low level.
In addition, as shown in fig. 3, in the embodiment, the top tube driving unit 101 further includes a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4, and the bottom tube driving unit 102 further includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8 and a ninth resistor R9.
Wherein, the first resistor R1 is connected between the first input terminal of the first NAND gate NAND1 and the first input terminal of the top tube driving unit 101 (i.e. the first end of the first resistor R1 is connected to the first pulse input signal PWMAS, the second end is connected to the first input terminal of the first NAND gate NAND 1), the second resistor R2 is connected between the second input terminal of the first NAND gate NAND1 and the second input terminal of the top tube driving unit 101 (i.e. the first end of the second resistor R2 is connected to the dc input voltage VIN, the second end is connected to the second input terminal of the first NAND gate 1), the third resistor R3 is connected between the output terminal of the second NAND gate 2 and the first input terminal of the third NAND gate 3 (i.e. the first end of the third resistor R3 is connected to the output terminal of the second NAND gate 2, the second end is connected to the first input terminal of the third NAND gate 3), the fourth resistor R6348 is connected between the output terminal of the third NAND gate 39 3 and the output terminal of the top tube driving unit 101 (i.e. the first end of the, the second terminal is the output terminal of the upper tube driving unit 101, outputting the first pulse output signal PWMOUTS). The fifth resistor R5 is connected between the first input terminal of the fourth NAND gate NAND4 and the first input terminal of the down tube driving unit 102 (i.e. the first terminal of the fifth resistor R5 is connected to the dc input voltage VIN, and the second terminal is connected to the first input terminal of the fourth NAND gate NAND 4), the sixth resistor R6 is connected between the second input terminal of the fourth NAND gate NAND4 and the second input terminal of the down tube driving unit 102 (i.e. the first terminal of the sixth resistor R6 is connected to the second pulse input signal PWMAX, and the second terminal is connected to the second input terminal of the fourth NAND gate 4), the seventh resistor R7 is connected between the first input terminal of the fifth NAND gate 5 and the first input terminal of the down tube driving unit 102 (i.e. the first terminal of the seventh resistor R7 is connected to the dc input voltage VIN, and the second terminal is connected to the first input terminal of the fifth NAND gate 5), the eighth resistor R8 is connected between the output terminal of the sixth NAND gate 6 and the output terminal of the down tube driving unit 102 (i.e. the first terminal of the, a second end is an output end of the down tube driving unit 102, and outputs a second pulse output signal PWMOUTX), and a ninth resistor R9 is connected between the second input end of the sixth NAND gate NAND6 and the third input end of the down tube driving unit 102, and between the second input end of the third NAND gate NAND3 and the third input end of the up tube driving unit 101 (i.e., the first end of the ninth resistor R9 is connected to the Enable signal Enable, and the second end is connected to the second input end of the sixth NAND gate NAND6 and the second input end of the sixth NAND gate NAND 6).
Based on the circuit shown in fig. 2, resistors are connected in series at appropriate positions, so that the circuit shown in fig. 3 can perform voltage division and current limiting functions.
The disclosed embodiment provides a signal logic conversion circuit 100, which comprises a top tube driving unit 101, a first input end of which is connected with a first pulse input signal PWMAS, a second input end of which is connected with a direct current input voltage VIN, and a third input end of which is connected with an Enable signal Enable, and is used for outputting a first pulse output signal PWMOUTS according to the first pulse input signal PWMAS, the direct current input voltage VIN and the Enable signal Enable to drive an upper side IGBT tube of a converter; and the lower tube driving unit 102, a first input end of which is connected with the direct current input voltage VIN, a second input end of which is connected with the second pulse input signal PWMAX, and a third input end of which is connected with the Enable signal Enable, is used for outputting a second pulse output signal PWMOUTX according to the second pulse input signal PWMAX, the direct current input voltage VIN and the Enable signal Enable, so as to drive the lower side IGBT tube of the converter. The signal logic conversion circuit has high integration level and is a conversion function of a two-level driving signal logic circuit, and signals output by two driving units are mutually independent; can be copied to similar application scenes, and has higher economic value.
EXAMPLE III
On the basis of the second embodiment, the embodiment of the present disclosure provides a specific circuit structure of the signal logic converting circuit 200.
Specifically, as shown in fig. 4, the top tube driving unit 201 includes a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a first capacitor, a seventh NAND gate NAND7 and an eighth NAND gate NAND8, and the bottom tube driving unit 202 includes a fourth NAND gate NAND4, a fifth NAND gate NAND5 and a sixth NAND gate NAND 6.
Wherein, the first input terminal of the first NAND gate NAND1 is the first input terminal of the top tube driving unit 201 (i.e. the first pulse input signal PWMAS is connected), the second input terminal of the first NAND gate NAND1 and the first input terminal of the second NAND gate NAND2 are the second input terminal of the top tube driving unit 201 (i.e. the second input terminal of the first NAND gate NAND1 and the first input terminal of the second NAND gate NAND2 are connected to the dc input voltage VIN), the output terminal of the first NAND gate NAND1 is connected to the second input terminal of the second NAND gate NAND2, the output terminal of the second NAND gate NAND2 is connected to the first input terminal of the third NAND gate NAND3, the second input terminal of the third NAND gate 3 is the third input terminal of the top tube driving unit 201 (i.e. the Enable signal is connected), the output terminal of the third NAND gate 3 is the output terminal of the top tube driving unit 201 (i.e. the first pulse output signal PWMOUTS is output), the first terminal of the first capacitor, the second end of the first capacitor is grounded, the first input end of the seventh NAND gate NAND7 is connected to the output end of the fifth NAND gate NAND5, the second input end of the seventh NAND gate NAND7 is connected to the first input end of the first NAND gate NAND1 (i.e., connected to the first pulse input signal PWMAS), the output end of the seventh NAND gate NAND7 is connected to the first input end of the fifth NAND gate NAND5, the first input end of the eighth NAND gate NAND8 is connected to the output end of the seventh NAND gate NAND7, the second input end of the eighth NAND gate 8 is connected to the first input end of the second NAND gate (i.e., the dc input voltage VIN), and the output end of the eighth NAND gate 8 is connected to the first input end of the third NAND gate 3, so as to switch the two-level signal logic conversion circuit. The first input terminals of the fourth NAND gate 4 and the fifth NAND gate 5 are the first input terminal of the down tube driving unit 202 (i.e., connected to the dc input voltage VIN), the second input terminal of the fourth NAND gate 4 is the second input terminal of the down tube driving unit 202 (i.e., connected to the second pulse input signal PWMAX), the output terminal of the fourth NAND gate 4 is connected to the second input terminal of the fifth NAND gate NAND5, the output terminal of the fifth NAND gate 5 is connected to the first input terminal of the sixth NAND gate 6, the second input terminal of the sixth NAND gate 6 is the third input terminal of the down tube driving unit 202 (i.e., connected to the Enable signal Enable), and the output terminal of the sixth NAND gate 6 is the output terminal of the down tube driving unit 202 (i.e., outputting the second pulse output signal PWMOUTX).
In this embodiment, the logic conversion circuit is applied in three levels, and at this time, the upper and lower tube driving units 202 are in an independent working state, the pulse signals output by the upper tube driving unit 201 and the lower tube driving unit 202 are independent from each other, the two driving signals are unlocked, and the output signals can be at a low level. In a three-level application, the upper tube driving unit 201 is an outer tube driving unit, and the lower tube driving unit 202 is an inner tube driving unit. In addition to the second embodiment, the seventh NAND gate NAND7 and the eighth NAND gate NAND8 are connected, so that the two-level logic conversion circuit can be converted into a three-level logic conversion circuit.
In addition, as shown in fig. 5, in the embodiment, the top tube driving unit 201 further includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a tenth resistor R10 and an eleventh resistor R11, and the bottom tube driving unit 202 further includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8 and a ninth resistor R9.
Wherein, the first resistor R1 is connected between the first input terminal of the first NAND gate NAND1 and the first input terminal of the top tube driving unit 201 (i.e. the first end of the first resistor R1 is connected to the first pulse input signal PWMAS, the second end is connected to the first input terminal of the first NAND gate NAND 1), the second resistor R2 is connected between the second input terminal of the first NAND gate NAND1 and the second input terminal of the top tube driving unit 201 (i.e. the first end of the second resistor R2 is connected to the dc input voltage VIN, the second end is connected to the second input terminal of the first NAND gate 1), the third resistor R3 is connected between the output terminal of the second NAND gate 2 and the first input terminal of the third NAND gate 3 (i.e. the first end of the third resistor R3 is connected to the output terminal of the second NAND gate 2, the second end is connected to the first input terminal of the third NAND gate 3), the fourth resistor R6348 is connected between the output terminal of the third NAND gate 39 3 and the output terminal of the top tube driving unit 201 (i.e. the first end of the, the second end is an output end of the upper tube driving unit 201, which outputs a first pulse output signal PWMOUTS), the tenth resistor R10 is connected between the output end of the seventh NAND gate NAND7 and the first input end of the fifth NAND gate NAND5 (i.e., the first end of the tenth resistor R10 is connected to the output end of the seventh NAND gate NAND7, the second end is connected to the first input end of the fifth NAND gate NAND 5), and the eleventh resistor R11 is connected between the output end of the eighth NAND gate NAND8 and the first input end of the third NAND gate NAND3 (i.e., the first end of the eleventh resistor R11 is connected to the output end of the eighth NAND gate NAND8, and the second end is connected to the first input end of the third NAND gate 3. The fifth resistor R5 is connected between the first input terminal of the fourth NAND gate NAND4 and the first input terminal of the down tube driving unit 202 (i.e. the first terminal of the fifth resistor R5 is connected to the dc input voltage VIN, and the second terminal is connected to the first input terminal of the fourth NAND gate NAND 4), the sixth resistor R6 is connected between the second input terminal of the fourth NAND gate NAND4 and the second input terminal of the down tube driving unit 202 (i.e. the first terminal of the sixth resistor R6 is connected to the second pulse input signal PWMAX, and the second terminal is connected to the second input terminal of the fourth NAND gate 4), the seventh resistor R7 is connected between the first input terminal of the fifth NAND gate 5 and the first input terminal of the down tube driving unit 202 (i.e. the first terminal of the seventh resistor R7 is connected to the dc input voltage VIN, and the second terminal is connected to the first input terminal of the fifth NAND gate 5), the eighth resistor R8 is connected between the output terminal of the sixth NAND gate 6 and the output terminal of the down tube driving unit 202 (i.e. the first terminal of the, a second end is an output end of the down tube driving unit 202, and outputs a second pulse output signal PWMOUTX), and a ninth resistor R9 is connected between the second input end of the sixth NAND gate NAND6 and the third input end of the down tube driving unit 202, and between the second input end of the third NAND gate NAND3 and the third input end of the up tube driving unit 201 (i.e., the first end of the ninth resistor R9 is connected to the Enable signal Enable, and the second end is connected to the second input end of the sixth NAND gate NAND6 and the second input end of the sixth NAND gate NAND 6).
Based on the circuit shown in fig. 4, resistors are connected in series at appropriate positions, so that the circuit shown in fig. 5 can play a role in voltage division and current limitation.
The embodiment of the present disclosure provides a signal logic converting circuit 200, which includes a top tube driving unit 201, a first input end of which is connected to a first pulse input signal PWMAS, a second input end of which is connected to a direct current input voltage VIN, and a third input end of which is connected to an Enable signal Enable, for outputting a first pulse output signal PWMOUTS according to the first pulse input signal PWMAS, the direct current input voltage VIN, and the Enable signal Enable to drive an upper side IGBT tube of a converter; and the lower tube driving unit 202, a first input end of which is connected with the direct current input voltage VIN, a second input end of which is connected with the second pulse input signal PWMAX, and a third input end of which is connected with the Enable signal Enable, is used for outputting a second pulse output signal PWMOUTX according to the second pulse input signal PWMAX, the direct current input voltage VIN and the Enable signal Enable, so as to drive the lower side IGBT tube of the converter. The signal logic conversion circuit has high integration level and has a three-level driving signal logic circuit conversion function, and signals output by the two driving units are mutually independent; can be copied to similar application scenes, and has higher economic value.
Example four
On the basis of the first embodiment, the embodiment of the present disclosure provides another specific circuit structure of the signal logic converting circuit 300.
Specifically, as shown in fig. 6, the top tube driving unit 301 includes a ninth NAND gate NAND9, a tenth NAND gate NAND10, an eleventh NAND gate NAND11 and a second capacitor, and the bottom tube driving unit 302 includes a twelfth NAND gate NAND12, a thirteenth NAND gate NAND13 and a fourteenth NAND gate NAND 14.
Wherein, the first input terminal of the ninth NAND gate NAND9 is the first input terminal of the top tube driving unit 301 (i.e. connected to the first pulse input signal PWMAS), the second input terminal of the ninth NAND gate NAND9 is connected to the output terminal of the twelfth NAND gate NAND12, the output terminal of the ninth NAND gate NAND9 is connected to the second input terminal of the tenth NAND gate NAND10, the first input terminal of the tenth NAND gate 10 is the second input terminal of the top tube driving unit 301 (i.e. connected to the dc input voltage VIN), the output terminal of the tenth NAND gate 10 is connected to the first input terminal of the eleventh NAND gate 11, the second input terminal of the eleventh NAND gate 11 is the third input terminal of the top tube driving unit 301 (i.e. connected to the Enable signal Enable), the output terminal of the eleventh NAND gate 11 is the output terminal of the top tube driving unit 301 (i.e. outputting the first pulse output signal PWMOUTS), the first terminal of the second capacitor is connected to the second input terminal, the second end of the second capacitor is grounded.
A first input terminal of the twelfth NAND gate NAND12 is connected to the output terminal of the ninth NAND gate NAND9, a second input terminal of the twelfth NAND gate NAND12 is the second input terminal of the down tube driving unit 302 (i.e., is connected to the second pulse input signal PWMAX), an output terminal of the twelfth NAND gate NAND12 is connected to the second input terminal of the thirteenth NAND gate NAND13, a first input terminal of the thirteenth NAND gate NAND13 is the first input terminal of the down tube driving unit 302 (i.e., is connected to the dc input voltage VIN), an output terminal of the thirteenth NAND gate NAND13 is connected to the first input terminal of the fourteenth NAND gate 14, a second input terminal of the fourteenth NAND gate 14 is the third input terminal of the down tube driving unit 302 (i.e., is connected to the Enable signal Enable), and an output terminal of the fourteenth NAND gate 14 is the output terminal of the down tube driving unit 302 (i.e., outputs the.
In this embodiment, the logic conversion circuit performs two-level application, and at this time, the upper and lower tube driving units 302 are in an interlocked state, the pulse signals output by the upper tube driving unit 301 and the lower tube driving unit 302 are correlated, and the output signals may not be allowed to be at a low level. In the second embodiment, since the second input terminal of the ninth NAND gate NAND9 is connected to the output terminal of the twelfth NAND gate NAND12 and the first input terminal of the twelfth NAND gate NAND12 is connected to the output terminal of the ninth NAND gate NAND9, the second input terminal of the ninth NAND gate NAND9 and the first input terminal of the twelfth NAND gate NAND12 cannot be connected to the dc input voltage VIN, so that the dc signal and the pulse signal input to the corresponding NAND gates are not contradictory. Similarly, in this embodiment, the connection of the corresponding nand gate is changed on the basis of the second embodiment, so that the two-level logic conversion circuit in the unlocked state (independent state) can be converted into the two-level logic conversion circuit in the interlocked state.
In addition, as shown in fig. 7, in the present embodiment, the top tube driving unit 301 further includes a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14 and a fifteenth resistor R15, and the bottom tube driving unit 302 further includes a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19 and a twentieth resistor R20.
Wherein, the twelfth resistor R12 is connected between the first input terminal of the ninth NAND gate NAND9 and the first input terminal of the top tube driving unit 301 (i.e., the first end of the twelfth resistor R12 is connected to the first pulse input signal PWMAS, the second end is connected to the first input terminal of the ninth NAND gate NAND 9), the thirteenth resistor R13 is connected between the second input terminal of the ninth NAND gate NAND9 and the output terminal of the twelfth NAND gate NAND12 (i.e., the first end of the thirteenth resistor R13 is connected to the second input terminal of the ninth NAND gate NAND9, the second end is connected to the output terminal of the twelfth NAND gate 12), the fourteenth resistor R14 is connected between the output terminal of the tenth NAND gate 10 and the first input terminal of the eleventh NAND gate 11 (i.e., the first end of the fourteenth resistor R14 is connected to the output terminal of the tenth NAND gate 10, the second end is connected to the first input terminal of the eleventh NAND gate 11), the fifteenth resistor R15 is connected between the output terminal of the eleventh NAND gate 11 and the output terminal of the top tube driving unit 301 (i. The output end of the eleventh NAND gate NAND11 is connected, the second end is the output end of the upper tube driving unit 301, and the first pulse output signal PWMOUTS) is output.
A sixteenth resistor R16 is connected between the first input terminal of the twelfth NAND gate NAND12 and the output terminal of the ninth NAND gate NAND9 (i.e. the first end of the sixteenth resistor R16 is connected to the output terminal of the ninth NAND gate NAND9, the second end is connected to the first input terminal of the twelfth NAND gate NAND 12), a seventeenth resistor R17 is connected between the second input terminal of the twelfth NAND gate NAND12 and the second input terminal of the down tube driving unit 302 (i.e. the first end of the seventeenth resistor R17 is connected to the second pulse input signal PWMAX, the second end is connected to the second input terminal of the twelfth NAND gate 63nand 84), an eighteenth resistor R18 is connected between the first input terminal of the thirteenth NAND gate 13 and the first input terminal of the down tube driving unit 302 (i.e. the first end of the eighteenth resistor R18 is connected to the dc input voltage VIN, the second end is connected to the first input terminal of the thirteenth NAND gate 13), and a nineteenth resistor R19 is connected between the output terminal of the fourteenth NAND gate 8585 and the output terminal of The second terminal is the output terminal of the down tube driving unit 302 and outputs a second pulse output signal PWMOUTX) connected to the output terminal of the fourteenth NAND gate NAND14, and the twentieth resistor R20 is connected between the second input terminal of the fourteenth NAND gate 14 and the third input terminal of the down tube driving unit 302 and between the second input terminal of the eleventh NAND gate NAND11 and the third input terminal of the up tube driving unit 301 (i.e. the first terminal of the twentieth resistor R20 is connected to the Enable signal Enable, and the second terminal is connected to the second input terminal of the fourteenth NAND gate 14 and the second input terminal of the eleventh NAND gate 11).
Based on the circuit shown in fig. 6, resistors are connected in series at appropriate positions, so that the circuit shown in fig. 7 can perform voltage division and current limiting functions.
The embodiment of the present disclosure provides a signal logic conversion circuit 300, which includes a top tube driving unit 301, a first input end of which is connected to a first pulse input signal PWMAS, a second input end of which is connected to a direct current input voltage VIN, and a third input end of which is connected to an Enable signal Enable, for outputting a first pulse output signal PWMOUTS according to the first pulse input signal PWMAS, the direct current input voltage VIN, and the Enable signal Enable, so as to drive an upper side IGBT tube of a converter; and the lower tube driving unit 302, a first input end of which is connected with the direct current input voltage VIN, a second input end of which is connected with the second pulse input signal PWMAX, and a third input end of which is connected with the Enable signal Enable, and is used for outputting a second pulse output signal PWMOUTX according to the second pulse input signal PWMAX, the direct current input voltage VIN and the Enable signal Enable to drive the lower side IGBT tube of the converter. The signal logic conversion circuit has high integration level, has the conversion function of a two-level driving signal logic circuit, and the signals output by the two driving units are interlocked; can be copied to similar application scenes, and has higher economic value.
The above is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, which may be variously modified and varied by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure. Although the embodiments disclosed in the present disclosure are described above, the embodiments are merely used for understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the disclosure is to be limited only by the appended claims.

Claims (9)

1. A signal logic conversion circuit, comprising:
the upper tube driving unit is connected with a first pulse input signal at a first input end, a direct current input voltage at a second input end and an enable signal at a third input end, and is used for outputting a first pulse output signal according to the first pulse input signal, the direct current input voltage and the enable signal so as to drive an upper IGBT tube of the converter;
and the first input end of the lower tube driving unit is connected with the direct current input voltage, the second input end of the lower tube driving unit is connected with a second pulse input signal, the third input end of the lower tube driving unit is connected with the enable signal, and the lower tube driving unit is used for outputting a second pulse output signal according to the second pulse input signal, the direct current input voltage and the enable signal so as to drive the lower side IGBT tube of the converter.
2. The signal logic conversion circuit of claim 1, wherein the top tube driver unit comprises a first nand gate, a second nand gate, a third nand gate, and a first capacitor;
the first input end of the first nand gate is the first input end of the top tube driving unit, the second input end of the first nand gate and the first input end of the second nand gate are the second input end of the top tube driving unit, the output end of the first nand gate is connected with the second input end of the second nand gate, the output end of the second nand gate is connected with the first input end of the third nand gate, the second input end of the third nand gate is the third input end of the top tube driving unit, the output end of the third nand gate is the output end of the top tube driving unit, the first end of the first capacitor is connected with the second input end of the third nand gate, and the second end of the first capacitor is grounded.
3. The signal logic conversion circuit of claim 2, wherein the top tube driver unit further comprises a first resistor, a second resistor, a third resistor, and a fourth resistor;
the first resistor is connected between the first input end of the first nand gate and the first input end of the top tube driving unit, the second resistor is connected between the second input end of the first nand gate and the second input end of the top tube driving unit, the third resistor is connected between the output end of the second nand gate and the first input end of the third nand gate, and the fourth resistor is connected between the output end of the third nand gate and the output end of the top tube driving unit.
4. The signal logic conversion circuit of claim 2, wherein the down tube driving unit comprises a fourth nand gate, a fifth nand gate, and a sixth nand gate;
the first input ends of the fourth nand gate and the fifth nand gate are the first input ends of the tube-down driving unit, the second input end of the fourth nand gate is the second input end of the tube-down driving unit, the output end of the fourth nand gate is connected with the second input end of the fifth nand gate, the output end of the fifth nand gate is connected with the first input end of the sixth nand gate, the second input end of the sixth nand gate is the third input end of the tube-down driving unit, and the output end of the sixth nand gate is the output end of the tube-down driving unit.
5. The signal logic conversion circuit of claim 4, wherein the lower tube driving unit further comprises a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor;
the fifth resistor is connected between the first input end of the fourth nand gate and the first input end of the lower tube driving unit, the sixth resistor is connected between the second input end of the fourth nand gate and the second input end of the lower tube driving unit, the seventh resistor is connected between the first input end of the fifth nand gate and the first input end of the lower tube driving unit, the eighth resistor is connected between the output end of the sixth nand gate and the output end of the lower tube driving unit, and the ninth resistor is connected between the second input end of the sixth nand gate and the third input end of the lower tube driving unit and between the second input end of the third nand gate and the third input end of the upper tube driving unit.
6. The signal logic conversion circuit of claim 4, wherein the top tube driver unit further comprises a seventh NAND gate and an eighth NAND gate;
the first input end of the seventh nand gate is connected with the output end of the fifth nand gate, the second input end of the seventh nand gate is connected with the first input end of the first nand gate, the output end of the seventh nand gate is connected with the first input end of the fifth nand gate, the first input end of the eighth nand gate is connected with the output end of the seventh nand gate, the second input end of the eighth nand gate is connected with the first input ends of the two nand gates, and the output end of the eighth nand gate is connected with the first input end of the third nand gate, so that the two-level signal logic conversion circuit is switched into a three-level signal logic conversion circuit.
7. The signal logic conversion circuit of claim 6, wherein the top tube driver unit further comprises a tenth resistor and an eleventh resistor;
the twelfth resistor is connected between the output end of the seventh nand gate and the first input end of the fifth nand gate, and the thirteenth resistor is connected between the output end of the eighth nand gate and the first input end of the third nand gate.
8. The signal logic conversion circuit of claim 1, wherein the upper tube driving unit comprises a ninth nand gate, a tenth nand gate, an eleventh nand gate and a second capacitor, and the lower tube driving unit comprises a twelfth nand gate, a thirteenth nand gate and a fourteenth nand gate;
a first input end of the ninth nand gate is a first input end of the top tube driving unit, a second input end of the ninth nand gate is connected to an output end of the twelfth nand gate, an output end of the ninth nand gate is connected to a second input end of the tenth nand gate, the first input end of the tenth nand gate is a second input end of the top tube driving unit, an output end of the tenth nand gate is connected to a first input end of the eleventh nand gate, the second input end of the eleventh nand gate is a third input end of the top tube driving unit, an output end of the eleventh nand gate is an output end of the top tube driving unit, a first end of the second capacitor is connected to a second input end of the eleventh nand gate, and a second end of the second capacitor is grounded;
a first input end of the twelfth nand gate is connected to an output end of the ninth nand gate, a second input end of the twelfth nand gate is a second input end of the lower tube driving unit, an output end of the twelfth nand gate is connected to a second input end of the thirteenth nand gate, the first input end of the thirteenth nand gate is a first input end of the lower tube driving unit, an output end of the thirteenth nand gate is connected to a first input end of the fourteenth nand gate, the second input end of the fourteenth nand gate is a third input end of the lower tube driving unit, and an output end of the fourteenth nand gate is an output end of the lower tube driving unit.
9. The signal logic conversion circuit according to claim 8, wherein the upper tube driving unit further comprises a twelfth resistor, a thirteenth resistor, a fourteenth resistor and a fifteenth resistor, and the lower tube driving unit further comprises a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor and a twentieth resistor;
the twelfth resistor is connected between the first input end of the ninth nand gate and the first input end of the top tube driving unit, the thirteenth resistor is connected between the second input end of the ninth nand gate and the output end of the twelfth nand gate, the fourteenth resistor is connected between the output end of the tenth nand gate and the first input end of the eleventh nand gate, and the fifteenth resistor is connected between the output end of the eleventh nand gate and the output end of the top tube driving unit;
the sixteenth resistor is connected between the first input end of the twelfth nand gate and the output end of the ninth nand gate, the seventeenth resistor is connected between the second input end of the twelfth nand gate and the second input end of the lower tube driving unit, the eighteenth resistor is connected between the first input end of the thirteenth nand gate and the first input end of the lower tube driving unit, the nineteenth resistor is connected between the output end of the fourteenth nand gate and the output end of the lower tube driving unit, and the twentieth resistor is connected between the second input end of the fourteenth nand gate and the third input end of the lower tube driving unit and between the second input end of the eleventh nand gate and the third input end of the upper tube driving unit.
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