CN116455218A - DCDC converter - Google Patents

DCDC converter Download PDF

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Publication number
CN116455218A
CN116455218A CN202310402774.6A CN202310402774A CN116455218A CN 116455218 A CN116455218 A CN 116455218A CN 202310402774 A CN202310402774 A CN 202310402774A CN 116455218 A CN116455218 A CN 116455218A
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CN
China
Prior art keywords
circuit
low
side driving
signal
driving signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310402774.6A
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Chinese (zh)
Inventor
李小涛
郝军哲
王牧晨
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Junying Semiconductor Shanghai Co ltd
Original Assignee
Junying Semiconductor Shanghai Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by Junying Semiconductor Shanghai Co ltd filed Critical Junying Semiconductor Shanghai Co ltd
Priority to CN202310402774.6A priority Critical patent/CN116455218A/en
Publication of CN116455218A publication Critical patent/CN116455218A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)

Abstract

The application relates to a DCDC converter, including first low side drive sub-circuit, second low side drive sub-circuit, first high side drive sub-circuit, second high side drive sub-circuit, first low side power switch tube, second low side power switch tube, first high side power switch tube and second high side power switch tube. When the signal accessed by the low-side driving circuit changes, the first low-side driving signal changes before the second low-side driving signal, and the high Bian Siou circuit accesses the first low-side driving signal which changes first. When the signal accessed by the high-side driving circuit changes, the first high-side driving signal changes before the second high-side driving signal, and the low-side dead zone circuit accesses the first high-side driving signal which changes first. And covering a part of dead time by using the delay time between the first low-side driving signal and the second low-side driving signal and the delay time between the first high-side driving signal and the second high-side driving signal, so as to optimize the dead time and improve the working efficiency.

Description

DCDC converter
Technical Field
The present application relates to the field of electronic circuit technology, and in particular, to a DCDC converter.
Background
The DCDC converter is a voltage converter that converts an input voltage to effectively output a fixed voltage. Its main functions include boosting, reducing and stabilizing voltage, and its application is very extensive.
The main losses of the DCDC converter during normal operation include the conduction losses of the high and low side switching transistors, the switching losses, dead time losses, IC self power losses, gate charge losses, and conduction losses due to the inductor DCR. The dead time loss refers to loss generated by forward voltage and load current of the body diode of the low-side switching tube in the dead time. If the dead time is too large, distortion of the output waveform may be caused, and the dead time loss is too large, reducing the output efficiency. Therefore, optimization of dead time is required to reduce dead time loss.
Disclosure of Invention
Based on this, it is necessary to provide a DCDC converter that can optimize dead time and improve operating efficiency.
In one embodiment, a DCDC converter is provided that includes a high side drive circuit, a low side drive circuit, a high side power switching tube, and a low side power switching tube; the low-side driving circuit comprises a first low-side driving sub-circuit and a second low-side driving sub-circuit, the high-side driving circuit comprises a first high-side driving sub-circuit and a second high-side driving sub-circuit, the low-side power switching tube comprises a first low-side power switching tube and a second low-side power switching tube which are connected in parallel, and the high-side power switching tube comprises a first high-side power switching tube and a second high-side power switching tube which are connected in parallel;
The first low-side driving sub-circuit outputs a first low-side driving signal to drive the first low-side power switching tube, and the second low-side driving sub-circuit outputs a second low-side driving signal to drive the second low-side power switching tube; when the signal accessed by the low-side driving circuit changes, the first low-side driving signal changes before the second low-side driving signal, and the first low-side driving signal is also used for being transmitted to the input end of the high-side dead zone circuit;
the first high-side driving sub-circuit outputs a first high-side driving signal to drive the first high-side power switching tube, and the second high-side driving sub-circuit outputs a second high-side driving signal to drive the second high-side power switching tube; when the signal accessed by the high-side driving circuit changes, the first high-side driving signal changes before the second high-side driving signal, and the first high-side driving signal is also used for being transmitted to the input end of the low-side dead zone circuit.
In one embodiment, the area of the first low-side power switch tube is smaller than the area of the second low-side power switch tube.
In one embodiment, the number of switching tubes included in the first low-side power switching tube is smaller than the number of switching tubes included in the second low-side power switching tube.
In one embodiment, the area of the first low-side power switch tube is smaller than the area of the second low-side power switch tube, and the first low-side driving sub-circuit and the second low-side driving sub-circuit have the same structure.
In one embodiment, the area of the first high-side power switch tube is smaller than the area of the second high-side power switch tube.
In one embodiment, the number of switching tubes included in the first high-side power switching tube is smaller than the number of switching tubes included in the second high-side power switching tube.
In one embodiment, the area of the first high-side power switch tube is smaller than the area of the second high-side power switch tube, and the first high-side driving sub-circuit and the second high-side driving sub-circuit have the same structure.
In one embodiment, the DCDC converter further comprises:
the input end of the high-side dead zone circuit is connected with the output end of the first low-side driving sub-circuit, and the output end of the high-side dead zone circuit is connected with the input end of the high-side driving circuit;
and the input end of the low-side dead zone circuit is connected with the output end of the first high-side driving sub-circuit, and the output end of the low-side dead zone circuit is connected with the input end of the low-side driving circuit.
In one embodiment, the high-side dead zone circuit includes a threshold switch circuit, a first logic circuit and a first level conversion circuit, wherein an input end of the threshold switch circuit is connected with an output end of the first low-side driving sub-circuit, an output end of the threshold switch circuit is connected with an input end of the first logic circuit, an output end of the first logic circuit is connected with the first level conversion circuit, and an output end of the first level conversion circuit is connected with an input end of the high-side driving circuit.
In one embodiment, the low-side dead zone circuit includes a second level conversion circuit, a second logic circuit and a third level conversion circuit, wherein an input end of the second level conversion circuit is connected with an output end of the first high-side driving sub-circuit, an output end of the second level conversion circuit is connected with an input end of the second logic circuit, an output end of the second logic circuit is connected with the third level conversion circuit, and an output end of the third level conversion circuit is connected with an input end of the low-side driving circuit.
In one embodiment, the second logic circuit includes a nor gate and a nor gate, where an input end of the nor gate is connected to the second level conversion circuit, an output end of the nor gate is connected to an input end of the nor gate, and an output end of the nor gate is connected to the third level conversion circuit.
The DCDC converter comprises a high-side driving circuit, a low-side driving circuit, a high-side power switching tube and a low-side power switching tube, wherein the low-side driving circuit comprises a first low-side driving sub-circuit and a second low-side driving sub-circuit, the high-side driving circuit comprises a first high-side driving sub-circuit and a second high-side driving sub-circuit, the low-side power switching tube comprises a first low-side power switching tube and a second low-side power switching tube which are connected in parallel, and the high-side power switching tube comprises a first high-side power switching tube and a second high-side power switching tube which are connected in parallel. The first low-side driving sub-circuit outputs a first low-side driving signal to drive the first low-side power switch tube, and the second low-side driving sub-circuit outputs a second low-side driving signal to drive the second low-side power switch tube. When the signal accessed by the low-side driving circuit changes, the first low-side driving signal changes before the second low-side driving signal, and the first low-side driving signal is also used for being transmitted to the input end of the high-side dead zone circuit. The first high-side driving sub-circuit outputs a first high-side driving signal to drive the first high-side power switch tube, and the second high-side driving sub-circuit outputs a second high-side driving signal to drive the second high-side power switch tube. When the signal accessed by the high-side driving circuit changes, the first high-side driving signal changes before the second high-side driving signal, and the first high-side driving signal is also used for being transmitted to the input end of the low-side dead zone circuit. Therefore, when the signal accessed by the low-side driving circuit changes, the first low-side driving signal changes first, and the second low-side driving signal changes later, and as the high-side dead zone circuit accesses the first low-side driving signal which changes first, part of dead zone time can be covered by delay time between the first low-side driving signal and the second low-side driving signal, and the dead zone time is optimized. Similarly, when the signal accessed by the high-side driving circuit changes, the first high-side driving signal changes first, and the second high-side driving signal changes later, and as the low-side dead zone circuit accesses the first high-side driving signal which changes first, part of dead zone time can be covered by delay time between the first high-side driving signal and the second high-side driving signal, so that the dead zone time is optimized, and the working efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic diagram of a DCDC converter according to an embodiment;
FIG. 2 is a schematic diagram of a high-side dead zone circuit according to an embodiment;
FIG. 3 is a schematic diagram of a low-side dead zone circuit according to an embodiment;
FIG. 4 is a schematic diagram of a high-side driving circuit according to an embodiment;
FIG. 5 is a schematic diagram of a low-side driving circuit according to an embodiment;
FIG. 6 is a schematic diagram of a high side drive circuit split into a first high side drive sub-circuit and a second high side drive sub-circuit according to an embodiment;
FIG. 7 is a schematic diagram of the low side driving circuit split into a first low side driving sub-circuit and a second low side driving sub-circuit according to an embodiment.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that the terms "first," "second," and the like, as used herein, may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the present application. Both the first resistor and the second resistor are resistors, but they are not the same resistor.
It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, units, etc., have electrical or data transfer between them.
It is understood that "at least one" means one or more and "a plurality" means two or more. "at least part of an element" means part or all of the element.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.
As shown in fig. 1, a DCDC converter is provided that includes a low-side drive circuit 210, a high-side drive circuit 220, a high-side power switch 310, and a low-side power switch 320. The low-side driving circuit 210 is not limited to a single structure, and may be, for example, a full-bridge circuit or a half-bridge circuit. The low side drive circuit 210 includes a first low side drive sub-circuit and a second low side drive sub-circuit. The high-side driving circuit 220 may be a full-bridge circuit or a half-bridge circuit. The high-side driving circuit 220 includes a first high-side driving sub-circuit and a second high-side driving sub-circuit, the low-side power switching tube 320 includes a first low-side power switching tube LS1 and a second low-side power switching tube LS2 connected in parallel, and the high-side power switching tube 310 includes a first high-side power switching tube HS1 and a second high-side power switching tube HS2 connected in parallel.
The first low-side driving sub-circuit outputs a first low-side driving signal LG1 to drive the first low-side power switching tube LS1, and the second low-side driving sub-circuit outputs a second low-side driving signal LG2 to drive the second low-side power switching tube LS2. Different low-side power switching tubes are driven by different circuits, so that control disorder can be avoided, and the working performance of the low-side power switching tubes is ensured. When the signal accessed by the low-side driving circuit changes, the first low-side driving signal LG1 changes before the second low-side driving signal LG2, and the first low-side driving signal LG1 is also used for being transmitted to the input end of the high-side dead zone circuit. When the signal accessed by the low-side driving circuit 210 changes, the first low-side driving signal LG1 changes before the second low-side driving signal LG2, which means that when the level of the signal accessed by the low-side driving circuit changes, the level of the first low-side driving signal LG1 output by the first low-side driving sub-circuit changes first, and the level of the second low-side driving signal LG2 output by the second low-side driving sub-circuit changes later. For example, when the signal to be connected to the low side driving circuit is the signal lg_p obtained according to the PWM signal, if the PWM signal turns high to change the level of the signal lg_p, the first low side driving signal LG1 turns low first and the second low side driving signal LG2 turns low later.
The first high-side driving sub-circuit outputs a first high-side driving signal HG1 to drive the first high-side power switching tube HS1, and the second high-side driving sub-circuit outputs a second high-side driving signal HG2 to drive the second high-side power switching tube HS2. When the signal accessed by the high-side driving circuit changes, the first high-side driving signal HG1 changes before the second high-side driving signal HG2, and the first high-side driving signal HG1 is also used for being transmitted to the input end of the low-side dead zone circuit. When the signal accessed by the high-side driving circuit 220 changes, the first high-side driving signal HG1 changes before the second high-side driving signal HG2, which means that when the level of the signal accessed by the high-side driving circuit changes, the first high-side driving signal HG1 output by the first high-side driving sub-circuit changes in level first, and the second high-side driving signal HG2 output by the second high-side driving sub-circuit changes in level later. For example, when the signal accessed by the high-side driving circuit is the signal hg_p obtained according to the PWM signal, if the PWM signal is turned down to change the level of the signal hg_p, the first high-side driving signal HG1 is turned down first, and the second high-side driving signal HG2 is turned down later.
When the signal accessed by the low-side driving circuit 210 changes, since the first low-side driving signal LG1 changes first, the second low-side driving signal LG2 changes later, and the high-side dead zone circuit accesses the first low-side driving signal LG1 that changes first, a part of the dead zone time can be covered by the delay time between the first low-side driving signal LG1 and the second low-side driving signal LG2, so that the dead zone time can be optimized.
Similarly, when the signal accessed by the high-side driving circuit 220 changes, since the first high-side driving signal HG1 changes first, the second high-side driving signal HG2 changes later, and the low-side dead zone circuit accesses the first high-side driving signal HG1 that changes first, a part of dead zone time can be covered by the delay time between the first high-side driving signal HG1 and the second high-side driving signal HG2, so that the dead zone time is optimized, and the working efficiency is improved.
The low-side power switching tube generally refers to a switching tube in a lower position in a bridge arm circuit. If the low-side power switching tube is divided into two parts, the low-side power switching tube comprises a first low-side power switching tube LS1 and a second low-side power switching tube LS2. The first low-side driving signal LG1 is used for driving the first low-side power switching tube LS1, and the second low-side driving signal LG2 is used for driving the second low-side power switching tube LS2. When the signal accessed by the low-side driving circuit changes, the first low-side driving signal LG1 changes before the second low-side driving signal LG2, by that the driving capability of the first low-side driving signal LG1 to the first low-side power switch tube LS1 is larger than the driving capability of the second low-side driving signal LG2 to the second low-side power switch tube LS2.
Further, the implementation of the driving capability of the first low-side driving signal LG1 to the first low-side power switch tube LS1 is not unique to the driving capability of the second low-side driving signal LG2 to the second low-side power switch tube LS 2. For example, the structure of the first low side driving sub-circuit generating the first low side driving signal LG1 is different from the structure of the second low side driving sub-circuit generating the second low side driving signal LG2, for example, the number or connection relation of the switching transistors included in the first low side driving sub-circuit and the second low side driving sub-circuit is different, so that signals with different magnitudes or different duty ratios can be generated, thereby making the driving capability of the first low side driving signal LG1 and the second low side driving signal LG2 different. Alternatively, the low-side power switching transistors driven by the first low-side driving signal LG1 and the second low-side driving signal LG2 may be different, which may also cause the driving capability of the first low-side driving signal LG1 and the second low-side driving signal LG2 to be different. The above or other ways may be selected by those skilled in the art so that the driving capability of the first low-side driving signal LG1 is greater than the driving capability of the second low-side driving signal LG 2. The low-side power switching transistors driven by the first low-side driving signal LG1 and the second low-side driving signal LG2 are different, in some embodiments of the present application, the number of low-side power switching transistors driven by the first low-side driving signal LG1 and the second low-side driving signal LG2 may be different, in other embodiments, other types of differences may also be possible, as long as the driving capability of the first low-side driving signal LG1 is enabled to be greater than the driving capability of the second low-side driving signal LG 2.
The first low-side driving signal LG1 is also transmitted to the input terminal of the high-side dead zone circuit. When the signal accessed by the low side driving circuit 210 changes, the first low side driving signal LG1 changes first and the second low side driving signal LG2 changes later. For example, when the signal to be connected to the low side driving circuit is the signal lg_p obtained according to the PWM signal, if the PWM signal turns high, the level of the signal lg_p is changed, so that the first low side driving signal LG1 outputted by the first low side driving sub-circuit turns low first, and the second low side driving signal LG2 outputted by the second low side driving sub-circuit turns low afterwards. Since the high-side dead zone circuit is connected with the first low-side driving signal LG1 which changes first, a part of dead zone time can be covered by the delay time between the first low-side driving signal LG1 and the second low-side driving signal LG2, and the dead zone time is optimized.
Further, in one embodiment, the area of the first low-side power switch tube LS1 driven by the first low-side driving sub-circuit is smaller than the area of the second low-side power switch tube LS2 driven by the second low-side driving sub-circuit. Because the area of the first low-side power switch tube LS1 is smaller than that of the second low-side power switch tube LS2, the workload of the first low-side driving sub-circuit is smaller than that of the second low-side driving sub-circuit, so that the driving capability of the first low-side driving signal LG1 generated by the first low-side driving sub-circuit to the first low-side power switch tube LS1 is larger than that of the second low-side driving signal LG2 generated by the second low-side driving sub-circuit to the second low-side power switch tube LS 2. When the signals accessed by the first low-side driving sub-circuit and the second low-side driving sub-circuit are the same and the accessed signals change, the first low-side driving signal LG1 generated by the first low-side driving sub-circuit changes first and the second low-side driving signal LG2 generated by the second low-side driving sub-circuit changes later because the work load of the first low-side driving sub-circuit is smaller than that of the second low-side driving sub-circuit.
The implementation that the area of the first low-side power switching tube LS1 is smaller than the area of the second low-side power switching tube LS2 is not exclusive, and may be implemented, for example, by the number of switching tubes included in the first low-side power switching tube LS1 being smaller than the number of the second low-side power switching tubes LS 2. When the number of switching transistors included in the first low-side power switching transistor LS1 is two or more, or when the number of switching transistors included in the second low-side power switching transistor LS2 is two or more, the switching transistors may be connected in parallel. It can be appreciated that, in other embodiments, the area of the first low-side power switch tube LS1 may be smaller than the area of the second low-side power switch tube LS2 in other manners, for example, the types of switch tubes included in the first low-side power switch tube LS1 are different from the types of switch tubes included in the second low-side power switch tube LS2, which will not be described herein.
In an embodiment, the area of the first low-side power switch tube LS1 is smaller than the area of the second low-side power switch tube LS2, and the first low-side driving sub-circuit and the second low-side driving sub-circuit have the same structure. When the first low-side driving sub-circuit includes a switching tube, the same structure of the first low-side driving sub-circuit and the second low-side driving sub-circuit means that the number and the connection relation of the switching tubes in the first low-side driving sub-circuit and the second low-side driving sub-circuit are the same. Because the area of the first low-side power switch tube LS1 connected with the first low-side driving sub-circuit is smaller than that of the second low-side power switch tube LS2 connected with the second low-side driving sub-circuit, even though the structures of the first low-side driving sub-circuit and the second low-side driving sub-circuit are the same, because the workload of the first low-side driving sub-circuit is smaller than that of the second low-side driving sub-circuit, when the signals accessed by the first low-side driving sub-circuit and the second low-side driving sub-circuit change, the first low-side driving signal LG1 output by the first low-side driving sub-circuit with smaller workload changes first, and the second low-side driving signal LG2 output by the second low-side driving sub-circuit with larger workload changes later.
When the structure of the first low-side driving sub-circuit is the same as that of the second low-side driving sub-circuit, the low-side driving circuit 210 can maintain symmetry, and the stability of driving the low-side power switch tube can be maintained. It will be appreciated that in other embodiments, the first low-side driving sub-circuit and the structure may be different from the second low-side driving sub-circuit, for example, the first low-side driving sub-circuit may include a larger size ratio or a larger number ratio of switching transistors than the second low-side driving sub-circuit, such that the driving capability of the first low-side driving signal LG1 to the acting low-side power switching transistor is larger than the driving capability of the second low-side driving signal LG2 to the acting low-side power switching transistor.
High-side power switching tubes generally refer to switching tubes in upper positions in bridge arm circuits. If the high-side power switching tube is divided into two parts, the high-side power switching tube comprises a first high-side power switching tube HS1 and a second high-side power switching tube HS2. The first high-side driving signal HG1 is used for driving the first high-side power switching transistor HS1, and the second high-side driving signal HG2 is used for driving the second high-side power switching transistor HS2. The first high-side driving signal HG1 may be higher than the second high-side driving signal HG2 in driving capability of the first high-side power switch tube HS1 by the first high-side driving signal HG1, so that the first high-side driving signal HG1 is changed before the second high-side driving signal HG2 when the signal connected to the high-side driving circuit is changed.
Further, the implementation of the first high-side driving signal HG1 to the first high-side power switch tube HS1 with a driving capability greater than the driving capability of the second high-side driving signal HG2 to the second high-side power switch tube HS2 is not unique. For example, the first high-side driving sub-circuit generating the first high-side driving signal HG1 has a different structure from the second high-side driving sub-circuit generating the second high-side driving signal HG2, for example, the first high-side driving sub-circuit and the second high-side driving sub-circuit have different numbers or connection relations of switching transistors, so that signals with different magnitudes or different duty ratios can be generated, and thus the driving capabilities of the first high-side driving signal HG1 and the second high-side driving signal HG2 are different. Alternatively, the high-side power switch transistors driven by the first high-side driving signal HG1 and the second high-side driving signal HG2 may be different, which may also cause the driving capability of the first high-side driving signal HG1 and the second high-side driving signal HG2 to be different. The above or other ways may be selected by those skilled in the art so that the driving capability of the first high-side driving signal HG1 is greater than the driving capability of the second high-side driving signal HG 2. The high-side power switching transistors driven by the first high-side driving signal HG1 and the second high-side driving signal HG2 are different, in some embodiments of the present application, the number of high-side power switching transistors driven by the first high-side driving signal HG1 and the second high-side driving signal HG2 may be different, and in other embodiments, other types of differences may also be possible, as long as the driving capability of the first high-side driving signal HG1 is enabled to be greater than the driving capability of the second high-side driving signal HG 2.
The first high-side driving signal HG1 is transmitted to the input of the low-side dead zone circuit. When the signal accessed by the high-side driving circuit 220 changes, the first high-side driving signal HG1 changes first, and the second high-side driving signal HG2 changes later. For example, when the signal accessed by the high-side driving circuit is the signal hg_p obtained according to the PWM signal, if the PWM signal is turned down, the level of the signal hg_p is changed, so that the first high-side driving signal HG1 is turned down first, and the second high-side driving signal HG2 is turned down later. Because the low-side dead zone circuit is connected with the first high-side driving signal HG1 which changes first, part of dead zone time can be covered by the delay time between the first high-side driving signal HG1 and the second high-side driving signal HG2, so that the dead zone time is optimized, and the working efficiency is improved.
Further, in one embodiment, the area of the first high-side power switch transistor HS1 driven by the first high-side driving sub-circuit is smaller than the area of the second high-side power switch transistor HS2 driven by the second high-side driving sub-circuit. Because the area of the first high-side power switch tube HS1 is smaller than that of the second high-side power switch tube HS2, the workload of the first high-side driving sub-circuit is smaller than that of the second high-side driving sub-circuit, so that the driving capability of the first high-side driving signal HG1 generated by the first high-side driving sub-circuit to the first high-side power switch tube HS1 is larger than that of the second high-side driving signal HG2 generated by the second high-side driving sub-circuit to the second high-side power switch tube HS 2. When the signals accessed by the first high-side driving sub-circuit and the second high-side driving sub-circuit are the same and the accessed signals change, the working load of the first high-side driving sub-circuit is smaller than that of the second high-side driving sub-circuit, so that the first high-side driving signal HG1 generated by the first high-side driving sub-circuit changes firstly and the second high-side driving signal HG2 generated by the second high-side driving sub-circuit changes later.
The implementation manner that the area of the first high-side power switching tube HS1 is smaller than that of the second high-side power switching tube HS2 is not exclusive, and may be implemented, for example, by the number of switching tubes included in the first high-side power switching tube HS1 being smaller than that of the second high-side power switching tube HS 2. When the number of switching tubes included in the first high-side power switching tube HS1 is two or more, or when the number of switching tubes included in the second high-side power switching tube HS2 is two or more, the switching tubes may be connected in parallel. It can be appreciated that, in other embodiments, the area of the first high-side power switch tube HS1 may be smaller than the area of the second high-side power switch tube HS2 in other manners, for example, the types of switch tubes included in the first high-side power switch tube HS1 are different from the types of switch tubes included in the second high-side power switch tube HS2, which will not be described herein.
In an embodiment, the area of the first high-side power switch tube HS1 is smaller than the area of the second high-side power switch tube HS2, and the first high-side driving sub-circuit and the second high-side driving sub-circuit have the same structure. When the first high-side driving sub-circuit comprises switching tubes, the same structure of the first high-side driving sub-circuit and the second high-side driving sub-circuit means that the number and the connection relation of the switching tubes in the first high-side driving sub-circuit and the second high-side driving sub-circuit are the same. Because the area of the first high-side power switch tube HS1 connected with the first high-side driving sub-circuit is smaller than the area of the second high-side power switch tube HS2 connected with the second high-side driving sub-circuit, even though the structures of the first high-side driving sub-circuit and the second high-side driving sub-circuit are the same, because the workload of the first high-side driving sub-circuit is smaller than that of the second high-side driving sub-circuit, when the signals accessed by the first high-side driving sub-circuit and the second high-side driving sub-circuit are changed, the first high-side driving signal HG1 output by the first high-side driving sub-circuit with smaller workload is changed first, and the second high-side driving signal HG2 output by the second high-side driving sub-circuit with larger workload is changed later.
When the structure of the first high-side driving sub-circuit is the same as that of the second high-side driving sub-circuit, the high-side driving circuit 220 can maintain symmetry, and the stability of driving the high-side power switch tube can be maintained. It will be appreciated that in other embodiments, the first high-side driving sub-circuit and the structure may be different from the second high-side driving sub-circuit, for example, the first high-side driving sub-circuit may include a larger size ratio or a larger number ratio of switching transistors than the second high-side driving sub-circuit, such that the driving capability of the first high-side driving signal HG1 to the first high-side power switching transistors is larger than the driving capability of the second high-side driving signal HG2 to the second high-side power switching transistors.
In one embodiment, the DCDC converter further comprises a low side dead band circuit and a high side dead band circuit, an input of the high side dead band circuit being connected to an output of the first low side drive sub-circuit, an output of the high side dead band circuit being connected to an input of the high side drive circuit. The input end of the low-side dead zone circuit is connected with the output end of the first high-side driving sub-circuit, and the output end of the low-side dead zone circuit is connected with the input end of the low-side driving circuit.
Specifically, the output terminal of the high-side dead zone circuit may be connected to the input terminal of the high-side driving circuit 220, and outputs the high-side driving pre-signal hg_p to the high-side driving circuit 220, where the high-side driving pre-signal hg_p may be used as the input signal of the high-side driving circuit 220. The input end of the high-side dead zone circuit can be connected with the output end of the first low-side driving sub-circuit, and is connected with the first low-side driving signal LG1 output by the first low-side driving sub-circuit.
After the high-side dead zone circuit is connected to the first low-side driving signal LG1, the first low-side driving signal LG1 is subjected to level processing to obtain a high-side driving pre-signal hg_p, which is output to the high-side driving circuit 220. The level processing may include shaping processing, high-low level conversion, and the like. If the PWM signal turns high, the level of the signal lg_p is changed, so that the first low-side driving signal LG1 turns low first and the second low-side driving signal LG2 turns low later. Since the high-side dead zone circuit is connected with the first low-side driving signal LG1 which changes first, a part of dead zone time can be covered by the delay time between the first low-side driving signal LG1 and the second low-side driving signal LG2, and the dead zone time is optimized.
The output terminal of the low side dead zone circuit is connected to the input terminal of the low side driving circuit 210, and outputs the low side driving pre-signal lg_p to the low side driving circuit 210. The low side driving pre-signal lg_p may be used as an input signal of the low side driving circuit 210. The input end of the low-side dead zone circuit is connected with the output end of the first high-side driving sub-circuit, and is connected with a first high-side driving signal HG1 output by the first high-side driving sub-circuit. After the low-side dead zone circuit is connected to the first high-side driving signal HG1, the low-side driving pre-signal lg_p is obtained after the first high-side driving signal HG1 is subjected to level processing, and the low-side driving pre-signal lg_p is output to the low-side driving circuit 210. If the PWM signal turns down, the level of the signal hg_p changes, and then the first high-side driving signal HG1 turns down first, and the second high-side driving signal HG2 turns down later, and since the low-side dead zone circuit is connected to the first high-side driving signal HG1 that changes first, a part of the dead zone time can be covered by the delay time between the first high-side driving signal HG1 and the second high-side driving signal HG2, so that the dead zone time is optimized, and the working efficiency is improved.
The manner in which signals are processed varies depending on the configuration of the high-side dead zone circuit. In one embodiment, referring to fig. 2, the high-side dead zone circuit includes a threshold switch circuit 410, a first logic circuit 420 and a first level shifter circuit 430, wherein an input end of the threshold switch circuit 410 is connected to an output end of the first low-side driving sub-circuit, an output end of the threshold switch circuit 410 is connected to an input end of the first logic circuit 420, an output end of the first logic circuit 420 is connected to the first level shifter circuit 430, and an output end of the first level shifter circuit 430 is connected to an input end of the high-side driving circuit 220.
The threshold switch circuit 410 is connected to the first low-side driving signal LG1, and can shape the first low-side driving signal LG1 and transmit the first low-side driving signal LG1 to the input end of the first logic circuit 420. The threshold switch circuit 410 outputs a corresponding level signal according to the magnitude relation between the first low-side driving signal LG1 and the preset voltage threshold, and performs a waveform shaping function.
In some embodiments, threshold switching circuit 410 may be a schmitt trigger having two threshold voltages, referred to as a positive threshold voltage and a negative threshold voltage, respectively. When the input voltage in the first low side driving signal LG1 is higher than the forward threshold voltage, the output is high. When the input voltage in the first low side driving signal LG1 is lower than the negative threshold voltage, the output is low, so that the corresponding waveform is output according to the first low side driving signal LG 1.
An input terminal of the first logic circuit 420 is connected to an output terminal of the threshold switch circuit 410, and outputs a waveform output from the threshold switch circuit 410 to the first level shifter circuit 430 after performing logic processing.
In some embodiments, the first logic circuit 420 may be a nor gate, where a first input terminal of the nor gate is connected to an output terminal of the threshold switch circuit 410, and a second input terminal of the nor gate is connected to a pwm_b signal, and an output terminal of the nor gate is connected to an input terminal of the first level shifter circuit 430, where the pwm_b signal is a signal after the PWM signal passes through the nor gate. The first logic circuit 420 outputs a corresponding high-low level signal to the first level shift circuit 430 according to the output signal of the threshold switch circuit 410 and the pwm_b signal.
The first level shift circuit 430 may be a low-to-high level shift circuit for converting a logic low power signal and a ground signal into a logic high power signal BST (bootstrap voltage) and an SW (SWICH) signal, respectively. The signal output from the first level shifter 430 is output to the high-side driving circuit 220 as the high-side driving pre-signal hg_p. It is to be understood that in other embodiments, the high Bian Siou circuit can be of other configurations as long as it is realized by one skilled in the art.
The workflow of the high-side dead zone circuit is approximately as follows: the threshold switch circuit 410 is connected to the first low-side driving signal LG1, and can shape the first low-side driving signal LG1 and transmit the first low-side driving signal LG1 to the input end of the first logic circuit 420. An input terminal of the first logic circuit 420 is connected to an output terminal of the threshold switch circuit 410, and outputs a waveform output from the threshold switch circuit 410 to the first level shifter circuit 430 after performing logic processing. The first level shift circuit 430 converts the logic low power signal and the ground signal into logic high power signals BST and SW signals, respectively. The signal output from the first level shifter 430 is output to the high-side driving circuit 220 as the high-side driving pre-signal hg_p.
In one embodiment, referring to fig. 3, the low-side dead zone circuit includes a second level shifter 510, a second logic 520 and a third level shifter 530, wherein an input terminal of the second level shifter 510 is connected to the first high-side driving sub-circuit, an output terminal of the second level shifter 510 is connected to an input terminal of the second logic 520, an output terminal of the second logic 520 is connected to the third level shifter 530, and an output terminal of the third level shifter 530 is connected to an input terminal of the low-side driving circuit 210.
The workflow of the low-side dead zone circuit is approximately: the input end of the second level shifter 510 is connected to the high-side driving circuit 220, and is connected to the first high-side driving signal HG1 output by the high-side driving circuit 220. The second level shifter 510 level-shifts the first high-side driving signal HG1 and outputs the shifted signal to the second logic 520. The second logic circuit 520 performs logic processing on the accessed signal and transmits the processed signal to the third level conversion circuit 530. The third level conversion circuit 530 may convert the digital power signal and the ground signal into a power signal and a ground signal, respectively, wherein the digital power signal is approximately equal to the power signal. The signal output from the third level shifter 530 is output to the low side driving circuit 210 as the low side driving pre-signal lg_p. It is understood that in other embodiments, the low-side dead band circuit may have other configurations as long as it can be implemented by those skilled in the art.
The second level shifter 510 may be a high-to-low level shifter that converts the logic high power signal BST and the SW signal into a low power signal and a ground signal, respectively.
Further, in the low-side dead zone circuit, the second logic circuit 520 includes an inverter and a nor gate, wherein an input end of the inverter is connected to the second level shifter 510, an output end of the inverter is connected to an input end of the nor gate, and an output end of the nor gate is connected to the third level shifter 530. The signal output by the second level conversion circuit 510 is inverted by the nor gate and then output to the first input end of the nor gate, the second input end of the nor gate is connected to the PWM signal, and the nor gate performs nor processing on the signals connected to the two input ends and then outputs the processed signal to the third level conversion circuit 530. In other embodiments, the second logic circuit 520 may be configured as desired.
When the high-side power switching tube and the low-side power switching tube are divided, the high-side power switching tube can be divided into a first high-side power switching tube and a second high-side power switching tube according to a proportion, and the low-side power switching tube is divided into a first low-side power switching tube and a second low-side power switching tube according to a proportion. The ratio of the number of the first high-side power switch tubes to the number of the second high-side power switch tubes is not unique, and for example, the ratio of the number of the first high-side power switch tubes to the number of the second high-side power switch tubes may be 1:6, and the ratio of the number of the first low-side power switch tubes to the number of the second low-side power switch tubes may also be 1:6.
For a better understanding of the above embodiments, a detailed explanation is provided below in connection with a specific embodiment. In one embodiment, the DCDC converter includes a low side drive circuit 210, a high side drive circuit 220, a high side power switching tube, a low side power switching tube, a high side dead band circuit, and a low side dead band circuit. The low-side driving circuit comprises a first low-side driving sub-circuit and a second low-side driving sub-circuit. The high-side driving circuit 220 includes a first high-side driving sub-circuit and a second high-side driving sub-circuit, the low-side power switching tube includes a first low-side power switching tube LS1 and a second low-side power switching tube LS2 connected in parallel, and the high-side power switching tube includes a first high-side power switching tube HS1 and a second high-side power switching tube HS2 connected in parallel.
Specifically, referring to fig. 2, the high-side dead zone circuit includes a threshold switch circuit 410, a first logic circuit 420 and a first level shifter circuit 430, wherein the threshold switch circuit 410 is a schmitt trigger, and the first logic circuit 420 is a nor gate. The first level shifter 430 is a low-to-high level shifter that converts the logic low power supply signal DVDD and the ground signal DGND into high power supply BST and SW signals, respectively.
Referring to fig. 3, the low-side dead zone circuit includes a second level shifter 510, a second logic 520 and a third level shifter 530, wherein the second logic 520 includes a nor gate and a nor gate. The second level shift circuit 510 is a high-to-low level shift circuit that converts the logic high power supply signals BST (bootstrap voltage) and SW (Switch) into the low power supply signal DVDD and the ground signal DGND, respectively. The third level conversion circuit 530 is also a level conversion circuit that converts the digital power supply signal DVDD and the ground signal DGND into a power supply signal PVDD and a ground signal PGND, respectively, where dvdd≡pvdd.
Fig. 4 and fig. 5 are driving circuits of a high-side power switching tube and a low-side power switching tube in the prior art, respectively, and final-stage signals HG and LG drive the high-side power switching tube and the low-side power switching tube to be turned on and off respectively. This approach may require three to four stages of drive circuitry to drive for a chip with a relatively large power transistor area (e.g., an RDS of 8 mohm).
In the present invention, the dead time includes the time between LG2 turning down (lower pipe off) and HG1 turning up (upper pipe on), and the time between HG2 turning down (upper pipe off) and LG1 turning up (lower pipe on).
The time between LG1 turning down (lower tube turning off) and HG1 turning up (upper tube turning on), that is, the level conversion time of the first level conversion circuit 430, hg_p turning up to HG1 after LG1 turning down, through the schmitt trigger, the two-stage input nor gate, also considers the transmission delay of the dead zone control logic that is common to the multi-stage P-tube and N-tube (such as PM1 and NM1 … … PM7 and NM 7) of the high-side driving circuit 220, and the parasitic resistance and capacitance of the power tube itself.
The time between the turning-down of HG1 (the turn-off of the upper tube) and the turning-up of LG1 (the turn-on of the lower tube), that is, the level transition time of HG1 after the turning-down passes through the second level transition circuit 510, then the transmission delay of the inverter and the nor gate, the level transition time of the third level transition circuit 530, the time between the turning-up of lg_p and the turning-up of LG1, and the transmission delay of the dead zone control logic which is common to the multi-stage P-tube and N-tube (such as PM8 and NM8 … … PM14 and NM 14) of the low-side driving circuit 210, and the parasitic resistance and capacitance of the power tube itself should be considered.
The high-side power switch tube is divided into two parts according to a proportion (for example, 1:6), the small area is the first high-side power switch tube HS1, and the large area is the second high-side power switch tube HS2. The high-side driving circuit 220 is also divided into two parts, including a first high-side driving sub-circuit and a second high-side driving sub-circuit, that is, the output signal HG of the high-side driving circuit 220 is split into two signals, namely, a first high-side driving signal HG1 and a second high-side driving signal HG2 (see fig. 6). The first high-side power switch HS1 is driven by HG1, the second high-side power switch HS2 is driven by HG2, and the driving capability of HG2 to HS2 is slightly weaker than the driving capability of HG1 to HS1 (but is stronger than the driving capability of HG to the whole high-side power switch HS before modification) due to the parasitic existence of the high-side driving circuit 220 and the power transistors. When the PWM is turned down, HG1 is turned down first, HG2 is turned down later, HG1 is turned down as a judgment of turn-off of the upper tube, and HG1 is used to replace the original HG signal to be input to the second level converting circuit 510, so as to cover a part of dead time with a time delay between the turning down of HG1 and the turning down of HG 2.
Because of the transmission delay of the layout wiring and the logic gate, the delay time between the turning-down of HG1 and the turning-down of HG2 is not too long, the delay time generally needs to be shorter than the time from the turning-down of HG1 to the opening of the lower pipe under most working conditions, and the delay time can be a time range which allows fluctuation in a certain range.
Correspondingly, the low-side power switch tube is divided into two parts in proportion (such as 1:6), the small area is the first low-side power switch tube LS1, the large area is the second low-side power switch tube LS2, and the low-side driving circuit 210 is also divided into two parts, including a first low-side driving sub-circuit and a second low-side driving sub-circuit. That is, the output signal LG of the low-side driving circuit 210 is split into a first low-side driving signal LG1 and a second low-side driving signal LG2 (see fig. 7), the first low-side power switching transistor LS1 is driven by LG1, and the second low-side power switching transistor LS2 is driven by LG 2. Because of the parasitic existence of the low-side driving circuit 210 and the power tube, the driving capability of LG2 to LS2 is slightly weaker than that of LG1 to LS1 (but is stronger than that of LG to the whole low-side power switch tube LS before modification). When the PWM turns high, LG1 turns down firstly, LG2 turns down later, LG1 turns down to be used as judgment of lower tube turn-off, LG1 is used for replacing the original LG signal to be input into a Schmitt trigger, and the aim is to cover a part of dead time by using the time of the delay between LG1 turning down and LG2 turning down.
Because of layout wiring and logic gate transmission delay, the time delay between LG1 turning-down and LG2 turning-down should not be too long, and generally, the time delay should be shorter than the time from LG1 turning-down to upper tube opening under most working conditions, and the time delay can be a time range allowing fluctuation in a certain range. Through the scheme, the dead time can be optimized.
In the description of the present specification, reference to the term "some embodiments," "other embodiments," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the present application. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application shall be subject to the appended claims.

Claims (11)

1. The DCDC converter is characterized by comprising a high-side driving circuit, a low-side driving circuit, a high-side power switching tube and a low-side power switching tube; the low-side driving circuit comprises a first low-side driving sub-circuit and a second low-side driving sub-circuit, the high-side driving circuit comprises a first high-side driving sub-circuit and a second high-side driving sub-circuit, the low-side power switching tube comprises a first low-side power switching tube and a second low-side power switching tube which are connected in parallel, and the high-side power switching tube comprises a first high-side power switching tube and a second high-side power switching tube which are connected in parallel;
the first low-side driving sub-circuit outputs a first low-side driving signal to drive the first low-side power switching tube, and the second low-side driving sub-circuit outputs a second low-side driving signal to drive the second low-side power switching tube; when the signal accessed by the low-side driving circuit changes, the first low-side driving signal changes before the second low-side driving signal, and the first low-side driving signal is also used for being transmitted to the input end of the high-side dead zone circuit;
the first high-side driving sub-circuit outputs a first high-side driving signal to drive the first high-side power switching tube, and the second high-side driving sub-circuit outputs a second high-side driving signal to drive the second high-side power switching tube; when the signal accessed by the high-side driving circuit changes, the first high-side driving signal changes before the second high-side driving signal, and the first high-side driving signal is also used for being transmitted to the input end of the low-side dead zone circuit.
2. The DCDC converter of claim 1, wherein the area of the first low-side power switch tube is smaller than the area of the second low-side power switch tube.
3. The DCDC converter of claim 2, wherein the first low-side power switching tube includes a smaller number of switching tubes than the second low-side power switching tube.
4. The DCDC converter of claim 1, wherein the area of the first low-side power switching tube is smaller than the area of the second low-side power switching tube, and wherein the first low-side driving sub-circuit and the second low-side driving sub-circuit are identical in structure.
5. The DCDC converter of claim 1, wherein the area of the first high side power switch tube is smaller than the area of the second high side power switch tube.
6. The DCDC converter of claim 5, wherein the first high side power switch tube includes a smaller number of switch tubes than the second high side power switch tube.
7. The DCDC converter of claim 1, wherein the area of the first high side power switch tube is smaller than the area of the second high side power switch tube, and wherein the first high side drive sub-circuit and the second high side drive sub-circuit are identical in structure.
8. The DCDC converter of claim 1, further comprising:
the input end of the high-side dead zone circuit is connected with the output end of the first low-side driving sub-circuit, and the output end of the high-side dead zone circuit is connected with the input end of the high-side driving circuit;
and the input end of the low-side dead zone circuit is connected with the output end of the first high-side driving sub-circuit, and the output end of the low-side dead zone circuit is connected with the input end of the low-side driving circuit.
9. The DCDC converter of claim 8, wherein the high-side dead band circuit includes a threshold switch circuit, a first logic circuit, and a first level shifter circuit, wherein an input of the threshold switch circuit is connected to an output of the first low-side drive sub-circuit, an output of the threshold switch circuit is connected to an input of the first logic circuit, an output of the first logic circuit is connected to the first level shifter circuit, and an output of the first level shifter circuit is connected to an input of the high-side drive circuit.
10. The DCDC converter of claim 8, wherein the low-side dead band circuit includes a second level shifter circuit, a second logic circuit, and a third level shifter circuit, an input of the second level shifter circuit being connected to an output of the first high-side drive sub-circuit, an output of the second level shifter circuit being connected to an input of the second logic circuit, an output of the second logic circuit being connected to the third level shifter circuit, an output of the third level shifter circuit being connected to an input of the low-side drive circuit.
11. The DCDC converter of claim 10, wherein the second logic circuit includes a nor gate and a nor gate, an input of the nor gate is connected to the second level shifter circuit, an output of the nor gate is connected to an input of the nor gate, and an output of the nor gate is connected to the third level shifter circuit.
CN202310402774.6A 2023-04-14 2023-04-14 DCDC converter Pending CN116455218A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117977963A (en) * 2024-02-05 2024-05-03 浙江中感微电子有限公司 DC-DC converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117977963A (en) * 2024-02-05 2024-05-03 浙江中感微电子有限公司 DC-DC converter

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