CN107689787B - High-voltage side gate driving circuit for half-bridge structure - Google Patents

High-voltage side gate driving circuit for half-bridge structure Download PDF

Info

Publication number
CN107689787B
CN107689787B CN201710675218.0A CN201710675218A CN107689787B CN 107689787 B CN107689787 B CN 107689787B CN 201710675218 A CN201710675218 A CN 201710675218A CN 107689787 B CN107689787 B CN 107689787B
Authority
CN
China
Prior art keywords
inverter
circuit
port
inverter unit
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710675218.0A
Other languages
Chinese (zh)
Other versions
CN107689787A (en
Inventor
祝靖
张允武
陆扬扬
孙伟锋
陆生礼
时龙兴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Southeast University Wuxi Institute Of Integrated Circuit Technology
Southeast University
Original Assignee
Southeast University Wuxi Institute Of Integrated Circuit Technology
Southeast University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Southeast University Wuxi Institute Of Integrated Circuit Technology, Southeast University filed Critical Southeast University Wuxi Institute Of Integrated Circuit Technology
Priority to CN201710675218.0A priority Critical patent/CN107689787B/en
Publication of CN107689787A publication Critical patent/CN107689787A/en
Application granted granted Critical
Publication of CN107689787B publication Critical patent/CN107689787B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0054—Gating switches, e.g. pass gates
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0063—High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load

Abstract

A high-voltage side gate drive circuit for a half-bridge structure is disclosed, wherein a pulse filter circuit comprises two signal paths, the two signal paths are respectively provided with a buffer circuit, an inverter unit and a shaping circuit, the two inverter units are respectively provided with four ports, the first ports of the two inverter units are input ends, the second ports of the two inverter units are respectively output ends, the third ports of the two inverter units are fixed potential ends, and the fourth ports of the two inverter units are floating potential ends; if the absolute value of the voltage difference between the first port and the fourth port is higher than the threshold voltage VTH of the inverter unit, the electric signal of the fourth port can be transmitted to the second port through the first inverter unit or the second inverter unit; if the absolute value of the voltage difference between the first port and the fourth port is not higher than the inverter unit threshold voltage VTH, the electrical signal of the fourth port cannot be transferred to the second port through the first inverter unit or the second inverter unit.

Description

High-voltage side gate driving circuit for half-bridge structure
Technical Field
The invention relates to a high-voltage driving technology, in particular to a high-voltage floating gate driving circuit with high noise immunity and used for a half-bridge structure, and belongs to the technical field of integrated circuits.
Background
The high-voltage side gate driving circuit is an integrated circuit for controlling the on and off of a high-voltage power switch device by using a low-voltage signal, and can be widely applied to the fields of motor driving, resonant power supply and the like because the high-voltage side gate driving circuit can effectively control a bridge-type connected power switch device.
High side gate drive circuits are often used to drive high side switching devices in half bridge configurations, while low side switching devices in half bridge configurations are driven by low side gate drive circuits.The basic topology is shown in FIG. 1, MH、MLThe high-side power switching device and the low-side power switching device are respectively in a half-bridge structure, a half-bridge topology is externally connected with a high-voltage bus voltage and a high-voltage (HV), a half-bridge driving circuit (100) comprises a high-voltage side gate driving circuit (101) and a low-voltage gate driving circuit (102), and an output signal HO of the high-voltage side gate driving circuit (101) drives the high-side power switching device MHThe output signal LO of the low-side gate driver circuit (102) drives the low-side power switch device ML. In order to improve the utilization efficiency of a power supply, the half-bridge driving circuit (100) adopts a single power supply mode, and low-voltage region circuits in the low-voltage side grid driving circuit (102) and the high-voltage side grid driving circuit (101) adopt a low-side fixed power supply VCC for supplying power, wherein the VCC is supplied by a bootstrap diode DBAnd a bootstrap capacitor CBSupplying power to a high-voltage area circuit in a high-voltage side gate drive circuit (101), wherein a power supply voltage VB and a reference ground VS of the high-voltage area circuit in the high-voltage side gate drive circuit (101) are floating voltages, and when an output signal HO of the high-voltage side gate drive circuit (101) is at a high level (VB) and an output LO of a low-voltage side gate drive circuit (102) is at a low level (COM), a high-side power switching device MHConducting, low side power switch device MLThe VS voltage is turned off, and rises, and the VB voltage also rises along with the rise of the VS voltage; conversely, when HO is low and LO is high, MHCutoff, MLOn, the VS and VB voltages drop. In the high-voltage side gate driving circuit (101), in order to reduce power consumption and improve reliability of the circuit, a mode of controlling a high-voltage power switch device by double narrow pulses is often adopted to realize high-voltage level shift, that is, a high-side input signal is converted into two paths of narrow pulses which respectively represent a rising edge and a falling edge of the high-side input signal, so that the conduction time of the high-voltage power switch device is greatly reduced.
As shown in fig. 2a, a high-side gate driving circuit (101) includes a narrow pulse generating circuit (200), a high-voltage level shifting circuit (201), a pulse filtering circuit (202), an RS flip-flop (203), and a gate driving circuit (204). Wherein, the narrow pulse generating circuit (200) respectively converts the rising edge and the falling edge of the high-side input signal HIN into two paths of narrow pulse signals SET and RESET which respectively control the high-voltage level shift circuit (2)01) Two output signals of the high-voltage level shift circuit (201) are connected with two input signals of a pulse filter circuit (202), and the two output signals of the pulse filter circuit (202) are respectively used as a set input end of an RS trigger (203)
Figure BDA0001374105460000023
And a reset input terminal
Figure BDA0001374105460000024
The output end of the RS trigger (203) is connected with the input end of the gate driving circuit (204), and the output signal of the gate driving circuit (204) is HO. The narrow pulse generating circuit (200) is used for converting the high-side input signal HIN into two paths of narrow pulses respectively representing the rising edge and the falling edge of the high-side input signal HIN, and the two paths of pulse signals are used for driving the high-voltage power switching devices LDM1 and LDM 2. The high-voltage level shift circuit (201) comprises high-voltage power switching devices LDM1 and LDM2, and a load resistor (R)L1、RL2) And a Zener diode (Z1, Z2) for converting the pulse signals SET and RESET of the low voltage region circuit into high voltage region circuit signals VDS and VDR, respectively.
As shown in FIG. 2b, since the high-voltage gate driving circuit (101) is powered by a floating power supply, the change of VS voltage generates dV/dt stress and passes through the bootstrap capacitor (C)B) Coupled to the VB terminal of the floating power supply, internal noise is generated in the high-side gate drive circuit (101), which may cause HO state change and MHFalse turn-off or false turn-on. Internal noise during the VS voltage rise, i.e., positive dV/dt stress, is generally more likely to cause MHFalse turn-off or false turn-on.
The conventional solution to the dV/dt noise problem is to use RC filtering, as shown in fig. 3, and the pulse filter circuit (202a) is composed of an inverter, a resistor and a capacitor, and functions to filter the input signals (VDS, VDR) below a certain pulse width, especially the common mode noise signal generated by the dV/dt noise. Although the circuit can reduce the influence of dV/dt noise to a certain extent, the contradiction exists that the dV/dt resistance, the VS negative bias resistance and the channel transmission delay are mutually restricted.
Disclosure of Invention
Aiming at the problem that the dV/dt resistance, the VS negative bias resistance and the channel transmission delay cannot be considered simultaneously in the prior art of the high-voltage side gate driving circuit, the invention provides the high-voltage side gate driving circuit for the half-bridge structure, wherein the adopted pulse filter circuit has high dV/dt noise resistance and VS negative bias resistance, the channel has very small transmission delay, in addition, the circuit structure is small and exquisite, and the layout area is saved.
The technical scheme adopted by the invention is as follows:
a high-voltage side grid drive circuit for a half-bridge structure comprises a narrow pulse generation circuit, a high-voltage level shift circuit, a pulse filter circuit, an RS trigger and a grid drive circuit which are sequentially connected, wherein the narrow pulse generation circuit converts the rising edge and the falling edge of a high-voltage side input signal HIN into two paths of narrow pulse signals SET and RESET respectively and outputs the two paths of narrow pulse signals SET and RESET to the high-voltage level shift circuit, the high-voltage level shift circuit converts the two paths of narrow pulse signals SET and RESET of a low-voltage area circuit into high-voltage area circuit signals VDS and VDR to control two high-voltage power switch devices in the high-voltage level shift circuit respectively, the two paths of output signals of the high-voltage level shift circuit are connected with two input signal ends of the pulse filter circuit, and the two output signals of the pulse filter circuit are connected
Figure BDA0001374105460000021
And a reset input terminal
Figure BDA0001374105460000022
The output end Q of the RS trigger is connected with the input end of the gate driving circuit, and an output signal HO of the gate driving circuit drives the high-voltage side power switching device; the method is characterized in that:
the pulse filter circuit comprises two signal paths, wherein the first path comprises a first buffer circuit, a first inverter unit and a first shaping circuit, the second path comprises a second buffer circuit, a second inverter unit and a second shaping circuit, and the input of the first buffer circuit is connected with the high-voltage area circuit communication circuitThe second buffer circuit is connected with a high-voltage region circuit signal VDR, the first inverter unit and the second inverter unit are respectively provided with four ports which are respectively a first port, a second port, a third port and a fourth port, the first ports of the two inverter units are respectively the input ends of the two inverter units, the second ports of the two inverter units are respectively the output ends of the two inverter units, the third ports of the two inverter units are respectively the fixed potential ends of the two inverter units, and the fourth ports of the two inverter units are respectively the floating potential ends of the two inverter units; the output of the first buffer circuit is connected with the first port of the first inverter unit and the fourth port of the second inverter unit, the output of the second buffer circuit is connected with the first port of the second inverter unit and the fourth port of the first inverter unit, the output of the first inverter unit is connected with the input end of the first shaping circuit, and the output end of the first shaping circuit is connected with the set input end of the RS trigger
Figure BDA0001374105460000031
The output end of the second inverter unit is connected with the input end of a second shaping circuit, and the output end of the second shaping circuit is connected with the reset input end of the RS trigger
Figure BDA0001374105460000032
And the third ports of the first inverter unit and the second inverter unit are connected with a power supply signal or a ground signal, and the internal structures of the first inverter unit and the second inverter unit respectively comprise at least one inverter or an inverter chain consisting of a plurality of inverters.
The first buffer circuit comprises an inverter 500, the input end of the inverter 500 is connected with a high-voltage area circuit signal VDS, the output end of the inverter 500 is connected with a first port of a first inverter unit and a fourth port of a second inverter unit, the first inverter unit comprises a PMOS pipe 502 and an NMOS pipe 503, the grid electrode of the PMOS pipe 502 and the grid electrode of the NMOS pipe 503 are interconnected to be used as the first port of the first inverter unit, the drain electrode of the PMOS pipe 502 and the drain electrode of the NMOS pipe 503 are interconnected to be used as the second port of the first inverter unitThe port is connected with a first shaping circuit, the source electrode of the PMOS tube 502 is used as a third port of the first inverter unit, and the source electrode of the NMOS tube 503 is used as a fourth port of the first inverter unit; the second buffer circuit comprises an inverter 501, the input end of the inverter 501 is connected with a high-voltage region circuit signal VDR, the output of the inverter 501 is connected with a first port of a second inverter unit and a fourth port of the first inverter unit, the second inverter unit comprises a PMOS pipe 504 and an NMOS pipe 505, the grid of the PMOS pipe 504 and the grid of the NMOS pipe 505 are interconnected to serve as a first port of the second inverter unit and are connected with the fourth port of the first inverter unit and the output end of the inverter 501, the drain of the PMOS pipe 504 and the drain of the NMOS pipe 505 are interconnected to serve as a second port of the second inverter unit and are connected with a second shaping circuit, the source of the PMOS pipe 504 serves as a third port of the second inverter unit and is interconnected with the third port of the first inverter unit, and the source of the NMOS pipe 505 serves as a fourth port of the second inverter unit and is connected with the first port of the first inverter unit; the first shaping circuit comprises an inverter 507 and an inverter 509 connected in series, the input of the inverter 507 is connected to the second port of the first inverter unit, and the output of the inverter 509 is connected to the set input of the RS flip-flop
Figure BDA0001374105460000041
The second shaping circuit comprises an inverter 506 and an inverter 508 connected in series, the input of the inverter 506 being connected to the second port of the second inverter cell, the output of the inverter 508 being connected to the reset input of the RS flip-flop
Figure BDA0001374105460000042
The first buffer circuit may also include an inverter 600 and an inverter 602 connected in series, an input terminal of the inverter 600 is connected to the high-voltage region circuit signal VDS, the first inverter unit includes a PMOS transistor 604 and an NMOS transistor 605, a gate of the PMOS transistor 604 and a gate of the NMOS transistor 605 are interconnected to serve as a first port of the first inverter unit, a drain of the PMOS transistor 604 and a drain of the NMOS transistor 605 are interconnected to serve as a second port of the first inverter unit, and connected to the second shaping circuit, a source of the PMOS transistor 604 serves as a third port of the first inverter unit,the source of the NMOS transistor 605 serves as the fourth port of the first inverter unit; the second buffer circuit comprises an inverter 601 and an inverter 603 which are connected in series, the input end of the inverter 601 is connected with a high-voltage region circuit signal VDR, the second inverter unit comprises a PMOS tube 606 and an NMOS tube 607, the grid of the PMOS tube 606 and the grid of the NMOS tube 607 are interconnected to be used as the first port of the second inverter unit and connected with the third port of the first inverter unit and the output end of the inverter 602, the drain of the PMOS tube 606 and the drain of the NMOS tube 607 are interconnected to be used as the second port of the second inverter unit and connected with the first shaping circuit, the source of the PMOS tube 606 is used as the third port of the second inverter unit and connected with the first port of the first inverter unit and the output end of the inverter 603, and the source of the NMOS tube 607 is used as the fourth port of the second inverter unit and interconnected with the fourth port of the first inverter unit; the first shaping circuit comprises an inverter 608, an input of the inverter 608 being connected to the second port of the second inverter unit, an output of the inverter 608 being connected to the set input of the RS flip-flop
Figure BDA0001374105460000043
The second shaping circuit comprises an inverter 609, the input terminal of the inverter 609 is connected to the second port of the first inverter unit, and the output terminal of the inverter 609 is connected to the reset input terminal of the RS flip-flop
Figure BDA0001374105460000044
The narrow pulse generating circuit converts the rising edge and the falling edge of a high-voltage side input signal HIN into two paths of narrow pulse signals SET and RESET respectively, and comprises a single pulse generating circuit which comprises a PMOS tube 801, an NMOS tube 802 and a resistor RGCapacitor CGThe gate of the PMOS tube 801 and the gate of the NMOS tube 802 are interconnected to be used as input ends and connected with one input end of the NOR gate 805 and the falling edge of a high-voltage side input signal HIN, the source of the PMOS tube 801 is connected with a low-voltage side fixed power supply VCC, and the drain of the PMOS tube 801 is connected with a resistor RGOne terminal of (1), resistance RGAnd the other end of the NMOS transistor 802, the drain electrode of the NMOS transistor, and the capacitorCGIs connected to the input terminal of the schmitt trigger 803, the output terminal of the schmitt trigger 803 is connected to the input terminal of the inverter 804, the output terminal of the inverter 804 is connected to the other input terminal of the nor gate 805, the source of the NMOS transistor 802 and the capacitor CGThe other end of the nor gate 805 is connected to a ground signal COM, and the output of the nor gate 805 is a narrow pulse signal RESET; the narrow pulse signal SET generating circuit comprises an inverter 806 and a single pulse generating circuit which has the same structure as the narrow pulse signal RESET generating circuit, wherein the input end of the inverter 806 is connected with the rising edge of the high-voltage side input signal HIN, the output end of the inverter 806 is connected with the input end of the single pulse generating circuit, and the output of the single pulse generating circuit is the narrow pulse signal SET.
The high-voltage level shift circuit is used for converting two paths of narrow pulse signals SET and RESET of the low-voltage area circuit into narrow pulse signals VDS and VDR of the high-voltage area circuit to complete level shift from low voltage to high voltage; the high-voltage power switch device comprises high-voltage power switch devices LDM1 and LDM2 which are LDMOS devices, and a load resistor RL1And RL2Ziner tubes Z1 and Z2; the grid of the high-voltage power switch device LDM1 is connected with a narrow pulse signal SET, the grid of the high-voltage power switch device LDM2 is connected with a narrow pulse signal RESET, and the drain of the high-voltage power switch device LDM1 is connected with a resistor RL1One end of the Zener diode (Z) and the positive end of the Zener diode (Z) 1 as the output end of the high-voltage area circuit signal (VDS) are connected with one input end of the pulse filter circuit, and the drain electrode of the high-voltage power switch device LDM2 is connected with the resistor RL2One end of the Zener diode Z2 and the positive end of the Zener diode Z2 are connected with the other input end of the pulse filter circuit as the output end of the high-voltage area circuit signal VDR, the source electrode of the high-voltage power switch device LDM1 and the source electrode of the high-voltage power switch device LDM2 are both connected with the ground signal COM, and the load resistor RL1And RL2And the other end of the zener diodes Z1 and the negative end of the zener diodes Z2 are connected to a high side floating power supply VB.
The RS trigger has the function of setting the input end
Figure BDA0001374105460000051
And a reset input terminal
Figure BDA0001374105460000052
The two pulse signals are converted into square wave signals and restored to the state of a high-voltage side input signal HIN, the square wave signals comprise an NAND gate 700 and an NAND gate 701, one input end of the NAND gate 700 is used as a reset input end of an RS trigger
Figure BDA0001374105460000053
The other input end of the NAND gate 700 is connected with the output end of the NAND gate 701 and serves as the output end Q of the RS flip-flop, and one input end of the NAND gate 701 serves as the setting input end of the RS flip-flop
Figure BDA0001374105460000054
The other input terminal of the nand gate 701 is connected to the output terminal of the nand gate 700.
The gate driving circuit is used for improving the output driving capability of the high-voltage side gate driving circuit and reducing the charge quantity of the high-voltage side floating power supply VB directly released through a parasitic channel to the greatest extent so as to ensure that the high-voltage side floating power supply VB is maintained at a proper voltage level for a long time; the high-voltage power switch comprises an inverter 702, an inverter 703, a PMOS (P-channel metal oxide semiconductor) tube 704 and an NMOS (N-channel metal oxide semiconductor) tube 705, wherein the input end of the inverter 702 and the input end of the inverter 703 are interconnected and connected with the output end Q of an RS trigger, the output end of the inverter 702 is connected with the grid electrode of the PMOS tube 704, the output end of the inverter 703 is connected with the grid electrode of the NMOS tube 705, the drain electrode of the PMOS tube 704 and the drain electrode of the NMOS tube 705 are interconnected and used as the output end of a grid driving circuit to output a signal HO for driving a high-voltage side power switch device, the source electrode of the PMOS tube 704 is connected with a.
Compared with the prior art, the technical scheme adopted by the invention has the following advantages and remarkable effects:
(1) the invention overcomes the contradiction that the dV/dt noise resistance, the VS negative bias resistance and the channel transmission delay of the high-voltage gate driving circuit are mutually restricted, and greatly improves the dV/dt noise resistance and the VS negative bias resistance of the high-voltage gate driving circuit;
(2) the invention avoids using R (resistance) C (capacitance) filter circuit structure, thereby reducing the time delay of circuit channel and improving the signal reaction speed;
(3) the invention can tolerate a certain process deviation, and the dV/dt noise can not affect the high-side output signal, thereby further improving the dV/dt noise resistance and the reliability of the circuit;
(4) the circuit of the invention has simple structure and small layout area.
Drawings
FIG. 1 is a basic topology of a half-bridge driving circuit driving an external power tube;
FIG. 2a is a block diagram of a high side gate drive circuit;
FIG. 2b is a waveform diagram of a key signal of the high-side gate driving circuit;
FIG. 3 is a block diagram of a prior art RC pulse filter circuit;
FIG. 4 is a block diagram of the novel pulse filter circuit of the present invention;
FIG. 5 is one implementation of the novel pulse filter circuit of the present invention;
FIG. 6 is another implementation of the novel pulse filter circuit of the present invention;
FIG. 7 is an embodiment of a high side gate driver circuit of the present invention;
FIG. 8 is one embodiment of a narrow pulse generation circuit;
FIG. 9 is a waveform illustrating operation of an embodiment of the present invention in the absence of noise interference;
FIG. 10 is a waveform illustrating operation of an embodiment of the present invention when there is dV/dt noise interference and the output HO is high;
FIG. 11 is a waveform illustrating operation of an embodiment of the present invention when there is dV/dt noise interference and the output HO is low.
Detailed Description
The high-voltage side gate driving circuit of the invention has the same structure as that shown in fig. 2a, and comprises a narrow pulse generating circuit 200, a high-voltage level shifting circuit 201, a pulse filtering circuit 202, an RS trigger 203 and a gate driving circuit 204, but the pulse filtering circuit is completely different from the pulse filtering circuit 202 in the prior art, and the narrow pulse generating circuit, the high-voltage level shifting circuit, the RS trigger and the gate driving circuit are matched with the pulse filtering circuit and adopt a better implementation circuit.
As shown in fig. 4, the pulse filter circuit 202c used in the present invention includes two signal paths, the first path includes a first buffer circuit 400, a first inverter unit 402 and a first shaping circuit 404, the second path includes a second buffer circuit 401, a second inverter unit 403 and a second shaping circuit 405, the input of the first buffer circuit 400 is connected to the high-voltage-region circuit signal VDS, the input of the second buffer circuit 401 is connected to the high-voltage-region circuit signal VDR, the first inverter unit 402 and the second inverter unit 403 are respectively provided with four ports, which are respectively a first port, a second port, a third port and a fourth port, the first ports of the two inverter units are respectively input ends of the two inverter units, the second ports of the two inverter units are respectively output ends of the two inverter units, the third ports of the two inverter units are respectively fixed potential ends of the two inverter units, the fourth ports of the two inverter units are respectively floating potential ends of the two inverter units; the output of the first buffer circuit 400 is connected with the first port of the first inverter unit 402 and the fourth port of the second inverter unit 403, the output of the second buffer circuit 401 is connected with the first port of the second inverter unit 403 and the fourth port of the first inverter unit 402, the output of the first inverter unit 402 is connected with the input of the first shaping circuit 404, the output of the first shaping circuit 404 is connected with the set input of the RS flip-flop
Figure BDA0001374105460000071
The output of the second inverter unit 403 is connected to the input of the second shaping circuit 405, and the output of the second shaping circuit 405 is connected to the reset input of the RS flip-flop
Figure BDA0001374105460000072
The third ports of the first inverter unit 402 and the second inverter unit 403 may be connected to a power supply signal or a ground signal, and the internal structures of the first inverter unit 402 and the second inverter unit 403 each include at least one inverter or an inverter chain of a plurality of inverters. First inverter unit 402 (or second inverter unit)403) The functions of (A) are as follows: the output electrical signal of the second port is controlled by the voltage difference between the first port and the fourth port, and if the absolute value of the voltage difference between the first port and the fourth port is higher than the threshold voltage VTH of the inverter unit, the electrical signal of the fourth port can be transmitted to the second port through the first inverter unit 402 (or the second inverter unit 403); if the absolute value of the voltage difference between the first port and the fourth port is not higher than the inverter unit threshold voltage VTH, the electric signal of the fourth port cannot be transferred to the second port through the first inverter unit 402 (or the second inverter unit 403).
Fig. 5 is a circuit of an embodiment of fig. 4, in the pulse filter circuit 202c, the first buffer circuit includes an inverter 500, an input terminal of the inverter 500 is connected to the high-voltage-region circuit signal VDS, the first inverter unit 402 includes a PMOS transistor 502 and an NMOS transistor 503, a gate of the PMOS transistor 502 and a gate of the NMOS transistor 503 are interconnected as a first port of the first inverter unit 402, a drain of the PMOS transistor 502 and a drain of the NMOS transistor 503 are interconnected as a second port of the first inverter unit 402 to be connected to the first shaping circuit, a source of the PMOS transistor 502 is a third port of the first inverter unit 402, and a source of the NMOS transistor 503 is a fourth port of the first inverter unit 402; the second buffer circuit comprises an inverter 501, the input end of the inverter 501 is connected with a high-voltage region circuit signal VDR, the output of the inverter 501 is connected with the first port of the second inverter unit and the fourth port of the first inverter unit, the second inverter unit comprises a PMOS pipe 504 and an NMOS pipe 505, the grid of the PMOS pipe 504 and the grid of the NMOS pipe 505 are interconnected to be used as the first port of the second inverter unit 403 and connected with the fourth port of the first inverter unit 402 and the output end of the inverter 501, the drain of the PMOS pipe 504 and the drain of the NMOS pipe 505 are interconnected to be used as the second port of the second inverter unit 403 and connected with a second shaping circuit, the source of the PMOS pipe 504 is used as the third port of the second inverter unit 403 and interconnected with the third port of the first inverter unit 402, and the source of the NMOS pipe 505 is used as the fourth port of the second inverter unit 403 and connected with the first port of the first inverter unit 402; the first shaping circuit comprises an inverter 507 and an inverter 509 connected in series, the input of the inverter 507 being connected to the second port of the first inverter unit 402, the output of the inverter 509 being connected toSet input end connected with RS trigger
Figure BDA0001374105460000081
The second shaping circuit comprises an inverter 506 and an inverter 508 connected in series, the input of inverter 506 being connected to the second port of the second inverter cell 403, the output of inverter 508 being connected to the reset input of the RS flip-flop
Figure BDA0001374105460000082
Logic power supplies of the inverter 508 and the inverter 509 are connected to a high side floating power supply VB, and logic power supplies of the PMOS transistor 502 and the PMOS transistor 504 are connected to the high side floating power supply VB. The pulse filter circuit 202c functions to filter the VDS and VDR when the VDS and VDR are common mode signals, i.e. the VDS and VDR voltage values are the same,
Figure BDA0001374105460000083
and
Figure BDA0001374105460000084
the output is high and, when VDS is high and VDR is low,
Figure BDA0001374105460000085
at the high level of the voltage, the voltage is high,
Figure BDA0001374105460000086
low, the high side output HO goes low, when VDS is low and VDR is high,
Figure BDA0001374105460000087
at the low level of the voltage, the voltage is low,
Figure BDA0001374105460000088
high, the high side output HO goes high. When the absolute value of the voltage difference between the first port of the first inverter unit 402 and the first port of the second inverter unit 403 is greater than the threshold voltage of the first inverter unit 402 or the second inverter unit 403, the output terminal
Figure BDA00013741054600000810
And
Figure BDA00013741054600000811
the signal will change.
Fig. 6 is another embodiment circuit of fig. 4, in the pulse filter circuit 202c ', a first buffer circuit includes an inverter 600 and an inverter 602 connected in series, an input terminal of the inverter 600 is connected to the high-voltage region circuit signal VDS, the first inverter unit 402' includes a PMOS transistor 604 and an NMOS transistor 605, a gate of the PMOS transistor 604 and a gate of the NMOS transistor 605 are interconnected as a first port of the first inverter unit 402 ', a drain of the PMOS transistor 604 and a drain of the NMOS transistor 605 are interconnected as a second port of the first inverter unit 402' and connected to a second shaping circuit, a source of the PMOS transistor 604 is used as a third port of the first inverter unit 402 ', and a source of the NMOS transistor 605 is used as a fourth port of the first inverter unit 402'; the second buffer circuit comprises an inverter 601 and an inverter 603 which are connected in series, the input end of the inverter 601 is connected with the high-voltage region circuit signal VDR, the second inverter unit 403 'comprises a PMOS tube 606 and an NMOS tube 607, the grid of the PMOS tube 606 and the grid of the NMOS tube 607 are interconnected to be used as the first port of the second inverter unit 403' to be connected with the third port of the first inverter unit 402 'and the output end of the inverter 602, the drain of the PMOS tube 606 and the drain of the NMOS tube 607 are interconnected to be used as the second port of the second inverter unit 403' to be connected with the first shaping circuit, the source of the PMOS tube 606 is used as the third port of the second inverter unit 403 'to be connected with the first port of the first inverter unit 402' and the output end of the inverter 603, and the source of the NMOS tube 607 is used as the fourth port of the second inverter unit 403 'and is interconnected with the fourth port of the first inverter unit 402'; the first shaping circuit comprises an inverter 608, an input of the inverter 608 being connected to the second port of the second inverter unit 403', an output of the inverter 608 being connected to the set input of the RS flip-flop
Figure BDA0001374105460000089
The second shaping circuit comprises an inverter 609, the input of the inverter 609 being connected to the second port of the first inverter unit 402', the output of the inverter 609 being connected to the reset input of the RS flip-flop
Figure BDA0001374105460000094
The pulse filter circuit 202 c' operates in the same manner as in fig. 5. When an absolute value of a voltage difference between the first port of the first inverter unit 402 'and the first port of the second inverter unit 403' is greater than a threshold voltage of the first inverter unit 402 'or the second inverter unit 403', the output terminal
Figure BDA0001374105460000092
And
Figure BDA0001374105460000093
the signal will change.
Fig. 7 is a circuit diagram of an embodiment of the high-voltage floating gate driving circuit for half-bridge structure according to the present invention, which includes a narrow pulse generating circuit 200, a high-voltage level shifting circuit 201, a pulse filtering circuit 202, an RS flip-flop 203, and a gate driving circuit 204. Wherein, the input end of the narrow pulse generating circuit 200 is HIN, the output ends of the narrow pulse generating circuit 200 are SET and RESET, the SET and RESET are used as two input ends of the high voltage level shifting circuit 201, the output end of the high voltage level shifting circuit 201 is VDS and VDR, the VDS and VDR are used as two input ends of the pulse filtering circuit 202c of fig. 5, two output ends of the pulse filtering circuit 202c are respectively connected with the SET input end of the RS flip-flop 203
Figure BDA0001374105460000091
And a reset input terminal
Figure BDA0001374105460000095
The output end Q of the RS flip-flop 203 is connected to the input end of the gate driving circuit 204, and the output end of the gate driving circuit 204 is HO. The power supply of the narrow pulse generating circuit 200 is connected to the low-side fixed power supply VCC and the logic ground signal COM, the power supplies of the pulse filter circuit 202c, the RS flip-flop 203 and the gate driving circuit 204 are connected to the high-side floating power supply VB and the logic ground VS, and the logic ground signal COM and the logic power supply of the high-voltage level shifting circuit 201 are connected to the high-side floating power supply VB.
Fig. 8 is a circuit implementation of narrow pulse generation circuit 200 of fig. 7, which is composed of two paths, one including a single pulse generation circuit 800 and the other including an inverter 806 and a single pulse generation circuit 800. The single pulse generating circuit 800 is composed of a resistor, a capacitor, a Schmidt trigger, an inverter and an OR-NOT gate, wherein the grid of the PMOS tube 801 and one input end of the grid of the NMOS tube 802 and one input end of the OR-NOT gate 805 are connected as the input end of the single pulse generating circuit 800, the drain of the PMOS tube 801 and the resistor RGOne end of the NMOS tube 802 is connected with the drain electrode of the NMOS tube RGAnother terminal of (1), a capacitor CGIs connected with the input end of the schmitt trigger 803, the source of the PMOS transistor 801 is connected with the low-side fixed power supply VCC, the source of the NMOS transistor 802 is connected with the ground signal COM, the output end of the schmitt trigger 803 is connected with the input end of the inverter 804, the output of the inverter 804 is connected with the other input end of the nor gate 805, and the output of the nor gate 805 serves as the output end of the single pulse generating circuit 800. The function of the narrow pulse generating circuit 200 is to convert the high-side input signal HIN into two narrow pulse signals respectively representing the rising edge and the falling edge of the input signal HIN, and the high-voltage power switch in the high-voltage level shift circuit (201) is driven by the two narrow pulse signals.
The embodiment of the high voltage level shifting circuit 201 of fig. 7 includes high voltage power switches (LDM1, LDM2), a load resistor (R)L1、RL2) And Zener diodes (Z1, Z2), wherein the high voltage power switching devices LDM1 and LDM2 are LDMOS devices. The gate of LDM1 is SET signal, the gate of LDM2 is RESET signal, and the drain of LDM1 is connected with resistor RL1And the positive end of the Zener tube Z1, and the drain electrode of the LDM2 is connected with a resistor RL2And the positive terminal of the Zener tube Z2, the source electrodes of the LDM1 and the LDM2 are connected with a ground signal COM and a load resistor (R)L1、RL2) And the negative end of the Zener diodes (Z1, Z2) is connected with a high-side floating power supply VB, the drain electrode of the LDM1 is used as one output end VDS of the high-voltage level shift circuit 201, and the drain electrode of the LDM2 is used as the other output end VDR of the high-voltage level shift circuit 201. The high-voltage level shift circuit 201 is used for respectively converting two paths of narrow pulse signals (SET and RESET) of the low-voltage circuit into narrow pulses of the high-voltage circuitThe burst signals (VDS and VDR) perform low to high voltage level shifting.
The embodiment of the RS flip-flop 203 in FIG. 7 includes two NAND gates (700 and 701), one input signal of the NAND gate 700 is
Figure BDA0001374105460000101
The other input signal of the NAND-gate 700 is connected to the output signal Q of the NAND-gate 701, and one input signal of the NAND-gate 701 is
Figure BDA0001374105460000102
The other input signal of the nand gate 701 is connected to the output of the nand gate 700, and the output signal of the RS flip-flop is Q. The RS flip-flop 203 functions to pulse a signal
Figure BDA0001374105460000103
And
Figure BDA0001374105460000104
and the signal is converted into a square wave signal and is restored to the state of the high-side input signal HIN.
The embodiment of the gate driving circuit 204 in fig. 7 comprises an inverter 702, wherein an input terminal of the inverter 703 is connected to the output terminal Q of the RS flip-flop, an output terminal of the inverter 702 is connected to a gate of a PMOS transistor 704, an output terminal of the inverter 703 is connected to a gate of an NMOS transistor 705, and a drain of the PMOS transistor 704 is connected to a drain of the NMOS transistor 705 and serves as a high-side output signal HO. The gate driving circuit 204 is used to increase the output driving capability of the high-side gate driving circuit to drive the high-side power device MHAnd the charge quantity directly discharged by the high-side floating power supply VB through a parasitic channel is reduced as much as possible so as to ensure that the VB is maintained at a proper voltage level for a long time.
As shown in fig. 9, in the operating waveform of the circuit without dV/dt noise interference, a SET pulse signal is generated at the rising edge of the input signal HIN, the SET signal turns on the high voltage power switch device LDM1, VDS becomes low level, the VDS pulse signal SETs the RS flip-flop (203) after passing through the pulse filter circuit (202c or 202 c'), Q becomes high level, and HO becomes high level; the falling edge of the input signal HIN generates a pulse signal RESET, the RESET signal enables the high-voltage power switch device LDM2 to be opened, the VDR pulse signal RESETs the RS trigger 203 after passing through the novel pulse filter circuit, Q is changed into low level, and HO is changed into low level.
As shown in fig. 10, when the low side input (LIN) is low, the high side input (HIN) changes from low to high, the high side output HO changes to high, the driven power tube MH turns on, the high side floating ground VS voltage rises, the VS voltage changes are coupled to the high side floating power supply VB through the bootstrap capacitor, the parasitic capacitor of the high voltage power switching devices (LDM1 and LDM2) generates displacement current, and the displacement current is generated on the load resistor (R1 and LDM2)L1And RL2) And voltage drop is generated, so that VDS and VDR are in low level relative to VS, and the VDS and VDR are common-mode signals and can be eliminated by the pulse filter circuit without influencing the output state of the high side.
As shown in fig. 11, after the high-side input (HIN) is low and the low-side input (LIN) is changed from high to low, the voltage at VS terminal is increased due to the freewheeling action of the inductive load current through the body diode of the high-side power device, and the high-side floating power supply VB is synchronously changed, so that the load resistance (R) is changedL1And RL2) The voltage drop is generated, so that VDS and VDR are low level relative to VS, and the VDS and VDR are common mode signals and can be eliminated by the pulse filter circuit, and the high-side output state is not influenced.

Claims (8)

1. A high-voltage side grid drive circuit for a half-bridge structure comprises a narrow pulse generation circuit, a high-voltage level shift circuit, a pulse filter circuit, an RS trigger and a grid drive circuit which are sequentially connected, wherein the narrow pulse generation circuit converts the rising edge and the falling edge of a high-voltage side input signal HIN into two paths of narrow pulse signals SET and RESET respectively and outputs the two paths of narrow pulse signals SET and RESET to the high-voltage level shift circuit, the high-voltage level shift circuit converts the two paths of narrow pulse signals SET and RESET of a low-voltage area circuit into high-voltage area circuit signals VDS and VDR to control two high-voltage power switch devices in the high-voltage level shift circuit respectively, the two paths of output signals of the high-voltage level shift circuit are connected with two input signal ends of the pulse filter circuit, and the two outputThe numbers are respectively connected with the set input end of the RS trigger
Figure FDA0002528381400000011
And a reset input terminal
Figure FDA0002528381400000012
The output end Q of the RS trigger is connected with the input end of the gate driving circuit, and an output signal HO of the gate driving circuit drives the high-voltage side power switching device; the method is characterized in that:
the pulse filter circuit comprises two signal paths, wherein the first path comprises a first buffer circuit, a first phase inverter unit and a first shaping circuit, the second path comprises a second buffer circuit, a second phase inverter unit and a second shaping circuit, the input of the first buffer circuit is connected with a high-voltage area circuit signal VDS, the input of the second buffer circuit is connected with a high-voltage area circuit signal VDR, the first phase inverter unit and the second phase inverter unit are respectively provided with four ports which are respectively a first port, the first ports of the two phase inverter units are respectively input ends of the two phase inverter units, the second ports of the two phase inverter units are respectively output ends of the two phase inverter units, the third ports of the two phase inverter units are respectively fixed potential ends of the two phase inverter units, and the fourth ports of the two phase inverter units are respectively floating potential ends of the two phase inverter units; the output of the first buffer circuit is connected with the first port of the first inverter unit and the fourth port of the second inverter unit, the output of the second buffer circuit is connected with the first port of the second inverter unit and the fourth port of the first inverter unit, the output of the first inverter unit is connected with the input end of the first shaping circuit, and the output end of the first shaping circuit is connected with the set input end of the RS trigger
Figure FDA0002528381400000014
The output end of the second inverter unit is connected with the input end of a second shaping circuit, and the output end of the second shaping circuit is connected with the reset input end of the RS trigger
Figure FDA0002528381400000013
2. The high side gate drive circuit for a half bridge configuration of claim 1, wherein: the third ports of the first inverter unit and the second inverter unit are connected with a power supply signal or a ground signal, and the internal structures of the first inverter unit and the second inverter unit respectively comprise at least one inverter or an inverter chain consisting of a plurality of inverters.
3. A high side gate drive circuit for a half bridge configuration according to claim 1 or 2, wherein: the first buffer circuit comprises an inverter 500, the input end of the inverter 500 is connected with a high-voltage area circuit signal VDS, the output of the inverter 500 is connected with a first port of a first inverter unit and a fourth port of a second inverter unit, the first inverter unit comprises a PMOS pipe 502 and an NMOS pipe 503, the grid of the PMOS pipe 502 and the grid of the NMOS pipe 503 are interconnected to be used as the first port of the first inverter unit, the drain of the PMOS pipe 502 and the drain of the NMOS pipe 503 are interconnected to be used as the second port of the first inverter unit and connected with a first shaping circuit, the source of the PMOS pipe 502 is used as the third port of the first inverter unit, and the source of the NMOS pipe 503 is used as the fourth port of the first inverter unit; the second buffer circuit comprises an inverter 501, the input end of the inverter 501 is connected with a high-voltage region circuit signal VDR, the output of the inverter 501 is connected with a first port of a second inverter unit and a fourth port of the first inverter unit, the second inverter unit comprises a PMOS pipe 504 and an NMOS pipe 505, the grid of the PMOS pipe 504 and the grid of the NMOS pipe 505 are interconnected to serve as a first port of the second inverter unit and are connected with the fourth port of the first inverter unit and the output end of the inverter 501, the drain of the PMOS pipe 504 and the drain of the NMOS pipe 505 are interconnected to serve as a second port of the second inverter unit and are connected with a second shaping circuit, the source of the PMOS pipe 504 serves as a third port of the second inverter unit and is interconnected with the third port of the first inverter unit, and the source of the NMOS pipe 505 serves as a fourth port of the second inverter unit and is connected with the first port of the first inverter unit; first shaping circuitThe circuit comprises an inverter 507 and an inverter 509 connected in series, wherein the input end of the inverter 507 is connected with the second port of the first inverter unit, and the output end of the inverter 509 is connected with the set input end of the RS trigger
Figure FDA0002528381400000021
The second shaping circuit comprises an inverter 506 and an inverter 508 connected in series, the input of the inverter 506 being connected to the second port of the second inverter cell, the output of the inverter 508 being connected to the reset input of the RS flip-flop
Figure FDA0002528381400000022
4. A high side gate drive circuit for a half bridge configuration according to claim 1 or 2, wherein: the first buffer circuit comprises an inverter 600 and an inverter 602 which are connected in series, the input end of the inverter 600 is connected with a high-voltage region circuit signal VDS, the first inverter unit comprises a PMOS pipe 604 and an NMOS pipe 605, the grid electrode of the PMOS pipe 604 and the grid electrode of the NMOS pipe 605 are interconnected to be used as a first port of the first inverter unit, the drain electrode of the PMOS pipe 604 and the drain electrode of the NMOS pipe 605 are interconnected to be used as a second port of the first inverter unit and connected with a second shaping circuit, the source electrode of the PMOS pipe 604 is used as a third port of the first inverter unit, and the source electrode of the NMOS inverter 605 is used as a fourth port of the first inverter unit; the second buffer circuit comprises an inverter 601 and an inverter 603 which are connected in series, the input end of the inverter 601 is connected with a high-voltage region circuit signal VDR, the second inverter unit comprises a PMOS tube 606 and an NMOS tube 607, the grid of the PMOS tube 606 and the grid of the NMOS tube 607 are interconnected to be used as the first port of the second inverter unit and connected with the third port of the first inverter unit and the output end of the inverter 602, the drain of the PMOS tube 606 and the drain of the NMOS tube 607 are interconnected to be used as the second port of the second inverter unit and connected with the first shaping circuit, the source of the PMOS tube 606 is used as the third port of the second inverter unit and connected with the first port of the first inverter unit and the output end of the inverter 603, and the source of the NMOS tube 607 is used as the fourth port of the second inverter unit and interconnected with the fourth port of the first inverter unit; first of allThe shaping circuit comprises an inverter 608, an input of the inverter 608 being connected to the second port of the second inverter unit, an output of the inverter 608 being connected to the set input of the RS flip-flop
Figure FDA0002528381400000024
The second shaping circuit comprises an inverter 609, the input terminal of the inverter 609 is connected to the second port of the first inverter unit, and the output terminal of the inverter 609 is connected to the reset input terminal of the RS flip-flop
Figure FDA0002528381400000023
5. A high side gate drive circuit for a half bridge configuration according to claim 1 or 2, wherein: the narrow pulse generating circuit converts the rising edge and the falling edge of a high-voltage side input signal HIN into two paths of narrow pulse signals SET and RESET respectively, and comprises a single pulse generating circuit which comprises a PMOS tube 801, an NMOS tube 802 and a resistor RGCapacitor CGThe gate of the PMOS tube 801 and the gate of the NMOS tube 802 are interconnected to be used as input ends and connected with one input end of the NOR gate 805 and the falling edge of a high-voltage side input signal HIN, the source of the PMOS tube 801 is connected with a low-voltage side fixed power supply VCC, and the drain of the PMOS tube 801 is connected with a resistor RGOne terminal of (1), resistance RGAnd the other end of the NMOS transistor 802, the drain electrode of the NMOS transistor, and the capacitor CGIs connected to the input terminal of the schmitt trigger 803, the output terminal of the schmitt trigger 803 is connected to the input terminal of the inverter 804, the output terminal of the inverter 804 is connected to the other input terminal of the nor gate 805, the source of the NMOS transistor 802 and the capacitor CGThe other end of the nor gate 805 is connected to a ground signal COM, and the output of the nor gate 805 is a narrow pulse signal RESET; the narrow pulse signal SET generating circuit comprises an inverter 806 and a single pulse generating circuit with the same structure as the narrow pulse signal RESET generating circuit, wherein the input end of the inverter 806 is connected with the rising edge of the high-voltage input signal HIN, and the output end of the inverter 806 is connected with the single pulse generating circuitThe input end of the circuit and the output of the single pulse generating circuit are narrow pulse signals SET.
6. A high side gate drive circuit for a half bridge configuration according to claim 1 or 2, wherein: the high-voltage level shift circuit is used for converting two paths of narrow pulse signals SET and RESET of the low-voltage area circuit into narrow pulse signals VDS and VDR of the high-voltage area circuit to complete level shift from low voltage to high voltage; the high-voltage power switch device comprises high-voltage power switch devices LDM1 and LDM2 which are LDMOS devices, and a load resistor RL1And RL2Ziner tubes Z1 and Z2; the grid of the high-voltage power switch device LDM1 is connected with a narrow pulse signal SET, the grid of the high-voltage power switch device LDM2 is connected with a narrow pulse signal RESET, and the drain of the high-voltage power switch device LDM1 is connected with a resistor RL1One end of the Zener diode (Z) and the positive end of the Zener diode (Z) 1 as the output end of the high-voltage area circuit signal (VDS) are connected with one input end of the pulse filter circuit, and the drain electrode of the high-voltage power switch device LDM2 is connected with the resistor RL2One end of the Zener diode Z2 and the positive end of the Zener diode Z2 are connected with the other input end of the pulse filter circuit as the output end of the high-voltage area circuit signal VDR, the source electrode of the high-voltage power switch device LDM1 and the source electrode of the high-voltage power switch device LDM2 are both connected with the ground signal COM, and the load resistor RL1And RL2And the other end of the zener diodes Z1 and the negative end of the zener diodes Z2 are connected to a high side floating power supply VB.
7. A high side gate drive circuit for a half bridge configuration according to claim 1 or 2, wherein: the RS trigger has the function of setting the input end
Figure FDA0002528381400000031
And a reset input terminal
Figure FDA0002528381400000032
The two pulse signals are converted into square wave signals and restored to the state of a high-voltage side input signal HIN, the square wave signals comprise an NAND gate 700 and an NAND gate 701, one input end of the NAND gate 700 is used as a reset input end of an RS trigger
Figure FDA0002528381400000033
The other input end of the NAND gate 700 is connected with the output end of the NAND gate 701 and serves as the output end Q of the RS flip-flop, and one input end of the NAND gate 701 serves as the setting input end of the RS flip-flop
Figure FDA0002528381400000041
The other input terminal of the nand gate 701 is connected to the output terminal of the nand gate 700.
8. A high side gate drive circuit for a half bridge configuration according to claim 1 or 2, wherein: the gate driving circuit is used for improving the output driving capability of the high-voltage side gate driving circuit and reducing the charge quantity of the high-voltage side floating power supply VB directly released through a parasitic channel to the greatest extent so as to ensure that the high-voltage side floating power supply VB is maintained at a proper voltage level for a long time; the high-voltage power switch comprises an inverter 702, an inverter 703, a PMOS (P-channel metal oxide semiconductor) tube 704 and an NMOS (N-channel metal oxide semiconductor) tube 705, wherein the input end of the inverter 702 and the input end of the inverter 703 are interconnected and connected with the output end Q of an RS trigger, the output end of the inverter 702 is connected with the grid electrode of the PMOS tube 704, the output end of the inverter 703 is connected with the grid electrode of the NMOS tube 705, the drain electrode of the PMOS tube 704 and the drain electrode of the NMOS tube 705 are interconnected and used as the output end of a grid driving circuit to output a signal HO for driving a high-voltage side power switch device, the source electrode of the PMOS tube 704 is connected with a.
CN201710675218.0A 2017-08-09 2017-08-09 High-voltage side gate driving circuit for half-bridge structure Active CN107689787B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710675218.0A CN107689787B (en) 2017-08-09 2017-08-09 High-voltage side gate driving circuit for half-bridge structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710675218.0A CN107689787B (en) 2017-08-09 2017-08-09 High-voltage side gate driving circuit for half-bridge structure

Publications (2)

Publication Number Publication Date
CN107689787A CN107689787A (en) 2018-02-13
CN107689787B true CN107689787B (en) 2020-08-25

Family

ID=61152588

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710675218.0A Active CN107689787B (en) 2017-08-09 2017-08-09 High-voltage side gate driving circuit for half-bridge structure

Country Status (1)

Country Link
CN (1) CN107689787B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107612528A (en) * 2017-09-29 2018-01-19 科域科技有限公司 A kind of pulse bandwidth filtering circuit arrangement
WO2019167133A1 (en) * 2018-02-27 2019-09-06 三菱電機株式会社 Communication system and signal repeater
CN108540121B (en) * 2018-04-13 2020-09-29 电子科技大学 Gate drive circuit without static power consumption
CN109728798B (en) * 2018-11-29 2023-08-01 中国科学院微电子研究所 High-voltage side grid driving circuit and integrated circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5436934A (en) * 1992-08-13 1995-07-25 3 Com Corporation Differential high frequency level detector and data restoration circuit including squelch offset and slicing offset
CN102571053A (en) * 2012-01-16 2012-07-11 南京航空航天大学 Control method for alternate current solid power switch and switch device
CN105187047A (en) * 2015-08-13 2015-12-23 电子科技大学 Ultra-high-voltage level shifting circuit for IGBT (Insulated Gate Bipolar Translator) driving chip
CN105827223A (en) * 2016-02-23 2016-08-03 东南大学 Integrated bootstrap high voltage driving chip and technological structure thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5436934A (en) * 1992-08-13 1995-07-25 3 Com Corporation Differential high frequency level detector and data restoration circuit including squelch offset and slicing offset
CN102571053A (en) * 2012-01-16 2012-07-11 南京航空航天大学 Control method for alternate current solid power switch and switch device
CN105187047A (en) * 2015-08-13 2015-12-23 电子科技大学 Ultra-high-voltage level shifting circuit for IGBT (Insulated Gate Bipolar Translator) driving chip
CN105827223A (en) * 2016-02-23 2016-08-03 东南大学 Integrated bootstrap high voltage driving chip and technological structure thereof

Also Published As

Publication number Publication date
CN107689787A (en) 2018-02-13

Similar Documents

Publication Publication Date Title
US10340906B2 (en) Integrated bootstrap high-voltage driver chip and technological structure thereof
CN103141028B (en) Level shift circuit
US10911045B1 (en) Segmented direct gate drive circuit of a depletion mode GaN power device
CN107689787B (en) High-voltage side gate driving circuit for half-bridge structure
US10263607B1 (en) Pulse filtering circuit
JP5825144B2 (en) Semiconductor device and high-side circuit driving method
US8044685B2 (en) Floating driving circuit
US9379699B2 (en) Switch driver with a low-cost cross-conduction-preventing circuit
CN105187047B (en) A kind of extra-high voltage level displacement circuit for IGBT driving chips
CN104731742A (en) Bus driver circuit with improved transition speed
EP3907888B1 (en) A circuit to transfer a signal between different voltage domains and corresponding method to transfer a signal
CN109921779B (en) Half-bridge circuit through protection circuit
CN110601690A (en) Low-working-voltage rapid downlink level shift circuit
JP3900178B2 (en) Level shift circuit
CN116683899A (en) High-reliability high-speed level shift circuit based on gallium nitride technology
US6813169B2 (en) Inverter device capable of reducing through current
CN215835383U (en) Electronic circuit
CN210380809U (en) Low-working-voltage rapid downlink level shift circuit
CN220527920U (en) Motor driving circuit and driving circuit thereof
CN216794844U (en) Large-voltage field effect tube driving circuit with simple structure
CN107579728B (en) Driving circuit of power field effect transistor adopting charge pump
CN117220661A (en) Anti-noise-interference gate driving circuit
CN116169871A (en) High-voltage integrated circuit and intelligent power module
CN116896256A (en) Efficient concept of driving PMOS and NMOS full bridge power stages
CN117749165A (en) High-side level conversion circuit with strong anti-interference function

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant