CN116683899A - High-reliability high-speed level shift circuit based on gallium nitride technology - Google Patents
High-reliability high-speed level shift circuit based on gallium nitride technology Download PDFInfo
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 65
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 65
- 238000005516 engineering process Methods 0.000 title claims description 16
- 238000000034 method Methods 0.000 claims abstract description 16
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- 239000003990 capacitor Substances 0.000 claims description 48
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- 208000013984 distal hereditary motor neuronopathy type 2 Diseases 0.000 claims description 11
- 101150110971 CIN7 gene Proteins 0.000 claims description 10
- 101150110298 INV1 gene Proteins 0.000 claims description 10
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 claims description 10
- 101100286980 Daucus carota INV2 gene Proteins 0.000 claims description 8
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 16
- 230000008054 signal transmission Effects 0.000 description 8
- 230000009471 action Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention provides a high-reliability high-speed level shift circuit based on a gallium nitride process, which comprises a level shift module, a latch module, a voltage bias module, a current mirror module, an acceleration pull-up module, a dVSW/dt resisting module and an output stage module, and can solve the problems of high delay and high power consumption of the traditional gallium nitride level shift circuit.
Description
Technical Field
The present invention relates to power integrated circuits, and more particularly, to a high reliability high speed level shift circuit based on gallium nitride technology.
Background
Gallium nitride materials are acknowledged as third-generation power semiconductor materials, and have excellent physical and chemical characteristics such as larger electron mobility, larger critical electric field strength and smaller heat conductivity, so that the gallium nitride power device has the characteristics of high speed, high reliability and low loss, and can obviously improve the switching speed, the conversion efficiency and the power density of a system when applied to an electric energy conversion system. The current widely used gallium nitride power device driving scheme is discrete driving, namely, a silicon-based driving chip is adopted to drive discrete gallium nitride devices, and the high-frequency advantage of the gallium nitride devices cannot be fully exerted due to the short plate of the working frequency of the silicon-based chip, on the contrary, the parasitic inductance problem exposed by the discrete driving scheme is increasingly remarkable along with the improvement of the switching speed, so that the reliability of the system is greatly reduced. To solve this problem, it is often necessary to introduce multilayer wiring, leadless packaging, and the like, but the PCB and chip packaging costs are inevitably increased. The gallium nitride technology is adopted, and the driving circuit and the power device are integrated on the same die, so that the problems can be fundamentally solved, and the high-frequency application and the reliability of the system are considered.
Because the P-type doping concentration of the gallium nitride material is not high, the P-type heavy doping cannot be realized, and the carrier mobility is low, the N-type gallium nitride field effect transistor and the P-type gallium nitride field effect transistor cannot be matched in the existing commercialized gallium nitride process, and the structure in the traditional CMOS circuit cannot be directly applied to the gallium nitride circuit. Furthermore, the breakdown voltage of the current N-type gallium nitride field effect transistor based on gallium nitride technology is low (about 6V), and the threshold voltage is high (about 2V), which greatly limits the flexibility of circuit design. Nowadays, with the continuous improvement of integration level, a half-bridge driving chip based on a gallium nitride technology is a future development direction, a high-voltage level shift circuit can change a low-level signal into a high-level signal, and the control of the low-voltage signal to the high-voltage circuit is realized, so that the half-bridge driving chip is a key technology for realizing dual-channel driving. However, the above-described short plates of gallium nitride material are more prominent in the design of level shift circuits, and thus the design of level shift circuits based on gallium nitride processes is particularly difficult.
In the practical application of the high-voltage driving chip, the switch of the power tube can introduce dVSW/dt noise into the driving chip, so that logic errors occur in the driving chip, and the problem is more remarkable along with the increase of the switching frequency.
Disclosure of Invention
The invention aims to provide a level shift circuit based on a gallium nitride process integrated circuit, which can overcome the problems of large delay and high power consumption of the traditional gallium nitride level shift circuit. In order to achieve the purpose of the invention, the technical scheme adopted by the invention is as follows: a low-power-consumption high-speed level shift circuit comprises a level conversion module, a latch module, a voltage bias module, a current mirror module, an acceleration pull-up module, a dVSW/dt resisting module and an output stage module.
The voltage bias module is composed of a voltage bias circuit 001, and the voltage bias circuit 001 comprises a current source I0 and an enhanced NMOS tube MN2. The connection relation of the voltage bias circuit 001 is: one end of the current source is connected with the drain electrode of the enhanced NMOS tube MN2, the grid electrode of the enhanced NMOS tube MN3 and the grid electrode of the enhanced NMOS tube MN4, the other end of the current source is connected with the power supply signal VDD of the low-voltage domain power supply rail, and the source electrode of the enhanced NMOS tube MN2 is connected with the ground signal VSS of the low-voltage domain power supply rail.
The current mirror module is composed of a current mirror circuit 002, and the current mirror circuit 002 comprises enhanced NMOS transistors MN 3-MN 4 and capacitors C1-C2. The connection relationship of the current mirror circuit 002 is: the grid electrode of the enhanced NMOS tube MN3 is connected with the drain electrode of the enhanced NMOS tube MN2, the grid electrode of the enhanced NMOS tube MN4 and one end of a current source I0, the drain electrode of the enhanced NMOS tube MN3 is connected with one end of a capacitor C1 and the source electrode of the enhanced NMOS tube MN5, the source electrode of the enhanced NMOS tube MN3 is connected with a ground signal VSS of a low-voltage domain power supply rail, the other end of the capacitor C1 is connected with the ground signal VSS of the low-voltage domain power supply rail, the drain electrode of the enhanced NMOS tube MN4 is connected with one end of the capacitor C2 and the source electrode of the enhanced NMOS tube MN6, the source electrode of the enhanced NMOS tube MN4 is connected with the ground signal VSS of the low-voltage domain power supply rail, and the other end of the capacitor C2 is connected with the ground signal VSS of the low-voltage domain power supply rail.
The low-voltage and high-voltage level shift module is composed of level shift branches 003 and 004, wherein the level shift branch 003 comprises an enhanced NMOS tube MN5, a high-voltage enhanced NMOS tube HMN1, a resistor R3, a diode D3 and a diode D5, and the level shift branch 004 comprises an enhanced NMOS tube MN6, a high-voltage enhanced NMOS tube HMN2, a resistor R4, a diode D4 and a diode D6. The connection relation of the level shift branch 003 is: the grid of enhancement mode NMOS pipe MN5 connects input signal VIN, enhancement mode NMOS pipe MN 5's source electrode connects enhancement mode NMOS pipe MN 3's drain electrode, one end of electric capacity C1, enhancement mode NMOS pipe MN 5's drain electrode connects high-voltage enhancement mode NMOS pipe HMN 1's source, high-voltage enhancement mode NMOS pipe HMN 1's grid connects low-voltage domain power rail's power signal VDD, high-voltage enhancement mode NMOS pipe HMN 1's drain electrode connects one end of resistance R1, enhancement mode NMOS pipe MN 7's grid is connected to the other end of resistance R1, enhancement mode NMOS pipe MN 9's grid, enhancement mode NMOS pipe MN 23's grid, one end of resistance R3, one end of diode D5, high-voltage domain power rail's power signal VBST is connected to the other end of resistance R3, high-voltage domain power rail's power signal VSST is connected to the other end of diode D5, high-voltage domain power rail's ground signal VSW is connected to the other end of diode D3. The connection relation of the level converting branch 004 is as follows: the output end of the inverter INV0 is connected with the grid electrode of the enhanced NMOS tube MN6, the source electrode of the enhanced NMOS tube MN6 is connected with the drain electrode of the enhanced NMOS tube MN4 and one end of the capacitor C2, the drain electrode of the enhanced NMOS tube MN6 is connected with the source electrode of the high-voltage enhanced NMOS tube HMN2, the grid electrode of the high-voltage enhanced NMOS tube HMN2 is connected with the power supply signal VDD of the low-voltage domain power supply rail, the drain electrode of the high-voltage enhanced NMOS tube HMN2 is connected with one end of the resistor R2, the other end of the resistor R2 is connected with the grid electrode of the enhanced NMOS tube MN8, the grid electrode of the enhanced NMOS tube MN10, the grid electrode of the enhanced NMOS tube MN24, one end of the resistor R4, one end of the diode D4 and one end of the diode D6, the other end of the resistor R4 is connected with the power supply signal VBST of the high-voltage domain power supply rail, and the other end of the diode D6 is connected with the ground signal VSW of the high-voltage domain power supply rail.
The accelerating pull-up module is composed of accelerating pull-up circuits 005 and 006, the accelerating pull-up circuit 005 comprises an enhanced NMOS tube MN7, an enhanced NMOS tube MN9, an enhanced NMOS tube MN11, an enhanced NMOS tube MN13, an enhanced NMOS tube MN15, an enhanced NMOS tube MN17, a resistor R5, a capacitor C3 and a diode D1, and the accelerating pull-up circuit 006 comprises an enhanced NMOS tube MN8, an enhanced NMOS tube MN10, an enhanced NMOS tube MN12, an enhanced NMOS tube MN14, an enhanced NMOS tube MN16, an enhanced NMOS tube MN18, a resistor R6, a capacitor C4 and a diode D2. The connection relation of the acceleration pull-up circuit 005 is: the grid electrode of the enhanced NMOS tube MN7 is connected with the grid electrode of the enhanced NMOS tube MN23, one end of a resistor R3, one end of a diode D5 and one end of a resistor R1, the source electrode of the enhanced NMOS tube MN7 is connected with a ground signal VSW of a high-voltage domain power supply rail, the drain electrode of the enhanced NMOS tube MN7 is connected with the drain electrode of the enhanced NMOS tube MN11, the grid electrode of the enhanced NMOS tube MN15, the grid electrode of the enhanced NMOS tube MN17 and one end of a resistor R5, the other end of the resistor R5 is connected with one end of a diode D1 and one end of a capacitor C3, the other end of the diode D1 is connected with a power supply signal VBST of the high-voltage domain power supply rail, the source electrode of the enhanced NMOS tube MN11 is connected with the ground signal VSW of the high-voltage domain power supply rail, the grid electrode of the enhanced NMOS tube MN11 is connected with the grid electrode of the enhanced NMOS tube MN13, the grid electrode of the enhanced NMOS tube MN12, the grid electrode of the enhanced NMOS tube MN14, one end of a resistor R9 and one end of a resistor R10, the source electrode of the enhanced NMOS tube MN9 is connected with a ground signal VSW of a high-voltage domain power supply rail, the drain electrode of the enhanced NMOS tube MN9 is connected with the source electrode of the enhanced NMOS tube MN15, the drain electrode of the enhanced NMOS tube MN13, the other end of a capacitor C3 and the grid electrode of the enhanced NMOS tube MN19, the drain electrode of the enhanced NMOS tube MN15 is connected with a power supply signal VBST of the high-voltage domain power supply rail, the source electrode of the enhanced NMOS tube MN17 is connected with the grid electrode of the enhanced NMOS tube MN21, the drain electrode of the enhanced NMOS tube MN22, one end of the resistor R8, the drain electrode of the enhanced NMOS tube MN20 and the input end of the inverter INV 1. The connection relationship of the acceleration pull-up circuit 006 is: the grid electrode of the enhanced NMOS tube MN8 is connected with the grid electrode of the enhanced NMOS tube MN24, one end of a resistor R4, one end of a diode D6 and one end of a resistor R2, the source electrode of the enhanced NMOS tube MN8 is connected with a ground signal VSW of a high-voltage domain power supply rail, the drain electrode of the enhanced NMOS tube MN8 is connected with the drain electrode of the enhanced NMOS tube MN12, the grid electrode of the enhanced NMOS tube MN16, the grid electrode of the enhanced NMOS tube MN18 and one end of a resistor R6, the other end of the resistor R6 is connected with one end of a diode D2 and one end of a capacitor C4, the other end of the diode D2 is connected with a power supply signal VBST of the high-voltage domain power supply rail, the source electrode of the enhanced NMOS tube MN12 is connected with the ground signal VSW of the high-voltage domain power supply rail, the grid of the enhanced NMOS tube MN12 is connected with the grid of the enhanced NMOS tube MN14, the grid of the enhanced NMOS tube MN11, the grid of the enhanced NMOS tube MN13, one end of a resistor R9 and one end of a resistor R10, the source of the enhanced NMOS tube MN10 is connected with a ground signal VSW of a high-voltage domain power supply rail, the drain of the enhanced NMOS tube MN10 is connected with the source of the enhanced NMOS tube MN16, the drain of the enhanced NMOS tube MN14, the other end of a capacitor C4 and the grid of the enhanced NMOS tube MN20, the drain of the enhanced NMOS tube MN16 is connected with a power supply signal VBST of the high-voltage domain power supply rail, the drain of the enhanced NMOS tube MN18 is connected with the grid of the enhanced NMOS tube MN22, the drain of the enhanced NMOS tube MN21, one end of the resistor R7 and the drain of the enhanced NMOS tube MN 19.
The latch module is composed of an auxiliary latch circuit 007, and comprises an enhanced NMOS tube MN19, an enhanced NMOS tube MN20, an enhanced NMOS tube MN21, an enhanced NMOS tube MN22, a resistor R7 and a resistor R8. The connection relation is as follows: the grid electrode of the enhanced NMOS tube MN19 is connected with the drain electrode of the enhanced NMOS tube MN9, the source electrode of the enhanced NMOS tube MN15, the drain electrode of the enhanced NMOS tube MN13 and the other end of the capacitor C3, the grid electrode of the enhanced NMOS tube MN20 is connected with the drain electrode of the enhanced NMOS tube MN10, the source electrode of the enhanced NMOS tube MN16, the drain electrode of the enhanced NMOS tube MN14 and the other end of the capacitor C4, the source electrode of the enhanced NMOS tube MN19 is connected with a ground signal VSW of a high-voltage domain power supply rail, the source electrode of the enhanced NMOS tube MN20 is connected with the ground signal VSW of the high-voltage domain power supply rail, the drain electrode of the enhanced NMOS tube MN19 is connected with the drain electrode of the enhanced NMOS tube MN21, the grid electrode of the enhanced NMOS tube MN22, one end of the resistor R7 and the source electrode of the enhanced NMOS tube MN18, the drain electrode of the enhanced NMOS tube MN20 is connected with the drain electrode of the enhanced NMOS tube MN22, one end of the grid electrode of the enhanced NMOS tube MN21, one end of the resistor R8, the source electrode of the enhanced NMOS tube MN17 and the input end of the inverter INV1, the source electrode of the enhanced NMOS tube 21 is connected with the ground signal VSW of the high-voltage domain power supply rail, the source of the source electrode of the enhanced NMOS tube is connected with the high-voltage domain power supply rail VSW, and the other end of the high-voltage domain power supply rail is connected with the high-voltage domain power supply signal VSW, and the high-voltage domain power supply rail, and the high-voltage domain power supply signal VSR 8.
The anti-dVSW/dt module is composed of an anti-dVSW/dt circuit 008 and comprises an enhanced NMOS tube MN23, an enhanced NMOS tube MN24, a resistor R9 and a resistor R10. The connection relation is as follows: the grid of the enhanced NMOS tube MN23 is connected with the grid of the enhanced NMOS tube MN7, the grid of the enhanced NMOS tube MN9, one end of a resistor R1, one end of a resistor R3, one end of a diode D3 and one end of a diode D5, the grid of the enhanced NMOS tube MN24 is connected with the grid of the enhanced NMOS tube MN8, the grid of the enhanced NMOS tube MN10, one end of a resistor R2, one end of a resistor R4, one end of a diode D4 and one end of a diode D6, the source of the enhanced NMOS tube MN23 is connected with a ground signal VSW of a high-voltage domain power supply rail, the source of the enhanced NMOS tube MN24 is connected with the ground signal VSW of the high-voltage domain power supply rail, the drain of the enhanced NMOS tube MN24 is connected with one end of a resistor R10, the other end of the resistor R10 is connected with the resistor R9, the grid of the enhanced NMOS tube MN11, the grid of the enhanced NMOS tube MN13, the grid of the enhanced NMOS tube MN12 and the grid of the enhanced NMOS tube MN14, and the other end of the resistor R9 is connected with the ground signal VSW of the high-voltage domain power supply rail.
The output module is composed of an output circuit 009, and includes an inverter INV1 and an inverter INV2. The connection relation is as follows: the input end of the inverter INV1 is connected with the source electrode of the enhanced NMOS tube MN17, the grid electrode of the enhanced NMOS tube MN21, the drain electrode of the enhanced NMOS tube MN22, one end of a resistor R8 and the drain electrode of the enhanced NMOS tube MN20, the output end of the inverter INV1 is connected with the input end of the inverter INV2, and the output end of the inverter INV2 is connected with the output signal VOUT.
Preferably: the enhanced NMOS transistors MN2 to MN24 are enhanced gallium nitride field effect transistors, and the high-voltage enhanced NMOS transistors HMN1 to HMN2 are high-voltage enhanced gallium nitride field effect transistors.
Preferably: the resistors R1-R10 are resistors based on gallium nitride technology, depletion type or enhancement type gallium nitride field effect transistors in a diode connection mode, depletion type or enhancement type gallium nitride field effect transistors biased by fixed voltage of a grid electrode, or resistors made of other materials under the gallium nitride technology, including metal film resistors and polysilicon resistors;
the diodes D1-D6 are depletion type or enhancement type gallium nitride field effect transistors in a diode connection mode, on-chip integrated diode devices or externally connected diode devices;
the inverters INV 0-INV 2 are resistance inverters or totem-pole type double-N output inverters based on gallium nitride technology;
the current source I0 is a current source formed by a depletion type gallium nitride field effect transistor and a depletion type or enhancement type gallium nitride field effect transistor with a grid electrode biased by a fixed voltage.
Compared with the prior art, the invention has the following advantages and remarkable effects:
(1) The delay of signal transmission can be effectively reduced. When the input signal VIN is low level, the upper end of the capacitor C1 is about zero potential, and when the VIN is high level, the voltage at the two ends of the capacitor C1 cannot be suddenly changed, the potential at the upper end of the capacitor C1 will be maintained at zero potential in a short time, and compared with the condition without the capacitor C1, the MN5 will obtain a larger gate-source voltage, so that the current capability of the MN5 is enhanced, the potential at the X point can be pulled down rapidly, and the delay of signal transmission is reduced. When the potential at the point X is turned from high to low, the potential at the point S is turned from low to high, the conduction of the NMOS tube MN17 in the pull-up circuit 005 is accelerated, an additional pull-up current path is provided for the point B, the potential at the point B is quickly turned, and the delay of signal transmission is reduced. And vice versa when the input signal VIN changes from high to low.
(2) The power consumption of the circuit during operation can be effectively reduced. The voltage bias circuit 001 and the current mirror circuit 002 act as tail current sources to provide relatively constant current to the level-shifting branches 003 and 004, greatly limiting power consumption. When the potential at the X point is turned from low to high, the potential at the S point is turned from high to low, MN17 is turned off, and the additional pull-up current path of B is closed, so that the power consumption is saved under the condition of ensuring the faster turning speed. The traditional level shift circuit based on gallium nitride technology comprises structures such as a pulse generating circuit, a digital filter circuit and the like, and a large number of logic gates are used.
(3) Can effectively improve the capability of resisting dVSW/dt. At the instant when the dVSW/dt comes, the X point and the Y point are simultaneously low level, the anti-dVSW/dt circuit 008 pulls the C point to high level, and the S point and the R point at two input ends of the latch circuit are set to low level and are maintained in the latch state, so that the output signal is not interfered by dVSW/dt noise.
Drawings
FIG. 1 is a schematic diagram of an exemplary application of the present invention in a half-bridge driving circuit based on a gallium nitride process;
FIG. 2 is a block diagram of a conventional level shift circuit and a block diagram of an internal pulse generating circuit thereof;
FIG. 3 is a diagram showing the waveforms of the conventional level shift circuit;
FIG. 4 is a diagram of waveforms of operation of a conventional level shifting circuit under the influence of dVSW/dt noise;
FIG. 5 is a block diagram of a high-reliability high-speed level shift circuit according to the present invention;
FIG. 6 is a diagram showing the waveforms of the high-reliability high-speed level shift circuit according to the present invention;
FIG. 7 is a diagram showing the waveforms of the operation of the highly reliable high-speed level shift circuit according to the present invention under the influence of dVSW/dt noise.
Detailed Description
The invention will now be further described with reference to the drawings and specific examples, which are given for illustration only and are not intended to limit the scope of the invention.
Fig. 1 is a schematic diagram of a typical application of the present invention in a half-bridge driving circuit based on gallium nitride technology, in which a high-reliability high-speed level shift circuit is used instead of the existing level shift circuit, and the rest is the same as the prior art. The half-bridge structure is a common structure in a power supply system, and is generally formed by connecting two gallium nitride power tubes in series, namely a high-side gallium nitride power tube and a low-side gallium nitride power tube, wherein the bus voltage of the high-side gallium nitride power tube T1 is VBUS, and a VS is arranged between the source electrode of the high-side gallium nitride power tube T1 and the drain electrode of the low-side gallium nitride power tube, so that the load of a subsequent circuit is connected. The core of the half-bridge driving circuit is a level shift circuit. Since VS is a floating potential, to realize normal driving of the high-side gan power transistor T1, a level shift circuit must be relied on to convert the signal of the low-voltage domain power rail VCC-GND into the high-voltage domain power rail VBST-VSW, so as to drive the high-side gan power transistor. The input HIN signal and the input LIN signal are respectively passed through a high-side input logic circuit and a low-side input logic circuit, the high-side signal is converted into a high-voltage domain signal by a level shift circuit, and then the high-side gallium nitride power tube T1 is driven by a high-side output driving circuit; the low-side signal drives the low-side gallium nitride power tube T2 through the delay matching circuit and the low-side output driving circuit. In the half-bridge driving circuit, the high-voltage basin area usually adopts a bootstrap power supply mode, and a diode D1 and a capacitor C1 form a floating power supply VB to supply power to the high-voltage basin area circuit.
Fig. 2 (a) is a block diagram of a conventional level shift circuit, which includes a pulse generating circuit 001, a level shift circuit 002, a digital filter circuit 003, a latch circuit 004, and a buffer stage circuit 005. After the input signal VIN passes through the pulse generating circuit 001, two pulse signals are generated at the SET point and the RESET point, and fig. 2 (b) is a block diagram of the pulse generating circuit 001. The two pulses enter the level conversion branch 002 and then are converted into the high-voltage domain power supply rail VBST-VSW, and are output from the X point and the Y point respectively. The diodes D1 and D2 function to clamp the X and Y potentials so that they are not much below VSW. The signal is transmitted to the latch circuit 004 after the dVSW/dt noise is filtered out in the digital filter circuit 003. The latch circuit 004 is generally composed of an RS trigger, and two NAND gates form positive feedback, so that the anti-interference capability of the circuit is enhanced. The signal is finally shaped by the buffer stage 005 to obtain the output signal VOUT. The circuit introduces a digital filter circuit 003, has stronger dVSW/dt resistance, but uses a large number of logic gates, and increases the power consumption and delay of the circuit. The circuit introduces the pulse generating circuit 001, reduces the on time of the level conversion branch 002, reduces the power consumption to a certain extent, but the pulse generating circuit 001 itself is also composed of a large number of logic gates, and increases a part of the power consumption.
Fig. 3 is a diagram showing an operation waveform of a conventional level shift circuit, in which an input signal VIN passes through a pulse generating circuit 001, a positive pulse is generated at a SET point and a RESET point, and the positive pulse respectively pull the potentials at an X point and a Y point to a low level after entering a level shift circuit 002 at a rising edge and a falling edge of the input signal VIN. When no dVSW/dt noise exists, the signals at the X point and the Y point can normally pass through the digital filter circuit 003. FIG. 4 is a diagram showing the waveforms of operation of a conventional level shift circuit under the influence of dVSW/dt noise, when dVSW/dt noise is present, the X-point and Y-point potentials are pulled to low level simultaneously, the X1-point and Y1-point are pulled to low level simultaneously, the Z-point potential is pulled to high level simultaneously, the R 'point and S' point are pulled to high level simultaneously, and the state of the RS latch is maintained, so that the signal transmission is not interfered by the dVSW/dt noise. Without the digital filter circuit 003, the latch circuit 004 would enter an unstable state and the output signal VOUT would not be determinable. Fig. 5 is a specific circuit diagram of a fully integrated gallium nitride low-power consumption high-speed level shift circuit according to the present invention, which is used for converting signals in a low-voltage domain into high-voltage domain, and includes a voltage bias circuit 001 and a current mirror circuit 002, level conversion branches 003 and 004, an acceleration pull-up circuit 005 and 006, a latch circuit 007, a dpsw/dt resisting circuit 008, and an output circuit 009. The low voltage domain power rail is a ground signal VSS-power signal VDD, and the high voltage domain power rail is a ground signal VSW-power signal VBST.
The level shift circuit provided by the invention reserves a level shift branch in the traditional level shift circuit, and adds a voltage bias circuit 001, a current mirror circuit 002, acceleration pull-up circuits 005 and 006 and a dVSW/dt resisting circuit 008.
The voltage bias circuit 001 and the current mirror circuit 002 together form a tail current source, which comprises a current source I0, enhanced NMOS transistors MN 2-MN 4, and capacitors C1-C2. After the current generated by the current source I0 flows through the enhanced NMOS MN2 configured by diode, a relatively constant voltage bias is generated at the gate thereof, and then a relatively constant current is provided to the level shift branches 003 and 004 after passing through the current mirror formed by the enhanced NMOS MN3 to MN 4. The capacitors C1 and C2 are respectively connected across the two ends of the source drain of the MN3 and the source drain of the MN 4. When the input signal VIN is low level, the upper end of the capacitor C1 is about zero potential, and when the VIN is high level, the voltage at the two ends of the capacitor C1 cannot be suddenly changed, the potential at the upper end of the capacitor C1 will be maintained at zero potential in a short time, and compared with the condition without the capacitor C1, the MN5 will obtain a larger gate-source voltage, so that the current capability of the MN5 is enhanced, the potential of the point can be pulled down rapidly, and the delay of signal transmission is reduced. After the X point potential is completely pulled down to a low level, C1 charging is completed, and the gate-source voltage and current capability of MN5 returns to a normal level. And vice versa when the input signal VIN changes from high to low. The addition of the capacitors C1 and C2 reduces the signal transmission delay and the power consumption as much as possible.
The level shift branches 003 and 004 are completely symmetrical and comprise enhanced NMOS transistors MN5 and MN6, high-voltage enhanced NMOS transistors HMN1 and HMN2, diodes D3 to D6 and resistors R3 and R4. The working principles of the level-shifting branches 003 and 004 are identical, and the working principles of the level-shifting branches 003 are as follows: when the input signal VIN is input to the gate of MN5, MN5 is turned on, and the potential at the X point changes from the high level to the low level. The resistance value of the resistor R3 is designed so that the voltage drop on the resistor R3 is about VBST-VSW when the branch is conducted, the high level at the X point is VBST, and the low level is VSW, and the purpose of converting signals of the low-voltage domain power supply rail to the high-voltage domain power supply rail is achieved. The purpose of the high voltage device HMN1 is to protect other devices on the branch from high voltage breakdown. During the power tube switching instant or dVSW/dt, the diode D3 has the function of clamping the potential at the X point so that it is not much lower than VSW; the diode D5 functions to clamp the potential at point X so that it is not much higher than VBST. The resistor R1 is used as a damping resistor to restrain oscillation generated by the noise of the switch instant dVSW/dt.
The accelerating pull-up circuits 005 and 006 are completely symmetrical, including enhancement NMOS transistors MN 7-MN 18, diodes D1-D2, resistors R5-R6, and capacitors C3-C4. The operation principle of the accelerating pull-up circuits 005 and 006 is identical, and the operation principle of the accelerating pull-up circuit 005 is as follows: when the X point is at a high level, MN7 and MN9 are conducted, the potential at the lower end of a capacitor C3 is zero, a diode D1 is conducted, VBST charges the capacitor C3 through the diode D1, the potential at the upper end of the capacitor C3 is VDD-VD (VD is the forward conducting voltage of the diode D1), and the voltage difference between the two ends is VDD-VD; when the X point becomes low level, MN7, MN9 turn off, the electric potential of upper end of the electric capacity C3 and electric potential of lower end of the resistance R5 are approximately equal, about VDD, make MN15 turn on, electric potential of lower end of electric capacity C3 becomes VDD, because the electric potential of both ends of electric capacity can not break suddenly, so electric potential of upper end of electric capacity C3 is raised to 2VDD-VD (about equal to 2 VDD), diode D1 is cut off. The circuit adopts a double N-type transistor output scheme, and introduces a bootstrap capacitor C3, on one hand, the scheme ensures that the gate-source voltage of the upper tube MN15 is zero when the upper tube and the lower tube are simultaneously conducted, and the problem that the output low level is higher than the ground potential due to the fact that the upper tube and the lower tube are simultaneously conducted is solved; on the other hand, by utilizing the characteristic that the voltages at the two ends of the capacitor cannot be suddenly changed, the gate-source voltage of the upper tube MN15 is ensured to be larger than the threshold voltage when the high level is output, the level loss problem caused by incomplete conduction of the upper tube is avoided, and the reliability of the circuit is improved.
The latch circuit 007 includes enhanced NMOS transistors MN19 through MN22, and resistors R7 through R8. The working principle is as follows: when the X point is changed from a high level to a low level, the MN19 is turned on, the S point is changed from a low level to a high level, the A point is changed to a low level, the MN22 is turned off, the VBST pulls the B point potential to the high level, the MN21 is turned on, the A point potential is further pulled to the low level, and the state is locked; in the process, the MN17 is in a conducting state, and the VBST charges the point B through two branches of the MN17 and the R8, so that the potential overturning speed of the point B is greatly improved. When the X point is changed from the low level to the high level, the S point is changed from the high level to the low level, the MN17 is turned off, the additional pull-up current path of the B is closed, and the power consumption is saved under the condition of ensuring the faster turnover speed.
The anti-dVSW/dt circuit 008 includes enhanced NMOS transistors MN 23-MN 24, and resistors R9-R10. The working principle is as follows: if the anti-dsw/dt circuit 007 is not introduced, when the high side channel is changed from the off state to the on state, VSW will rapidly rise and generate a forward dsw/dt noise, during this short period, the potentials at the X and Y points will drop to low level at the same time, the potentials at the S and R points will be pulled to high level at the same time, and when the dsw/dt noise is over, the latch circuit 007 will enter an unstable state, causing unexpected logic errors; after the anti-dVSW/dt circuit 007 is introduced, after the potentials at the X and Y points drop to a low level, the MN23 and the MN24 are cut off, the potential at the C point becomes a high level, the MN 11-MN 14 are conducted, and the potentials at the two input ends of the latch circuit 007 are pulled to a low level, so that the current output state is saved and the interference of dVSW/dt noise is avoided.
The output circuit 009 includes inverters INV1 to INV2. The purpose of which is to shape filter the output signal and to enhance its driving capability.
Fig. 6 is a waveform diagram illustrating the operation of the high-reliability high-speed level shift circuit according to the present invention. When the input signal VIN changes from low to high, the NMOS MN5 is turned on quickly, and the X point is pulled to low quickly. The inverted signal VIN' of the input signal VIN changes from high level to low level, so that MN6 is turned off rapidly, and the pull-up speed at the Y point is lower than the pull-down speed at the X point because the current capability of the resistor is far lower than that of the MOS transistor. Under the action of the bootstrap capacitor C3, the gate voltage range of the MN15 and the MN17 is increased from 0-VDD to 0-2 VDD, when the X point signal enters the acceleration pull-up circuit 005, the MN17 is conducted, the S point potential is pulled to a high level, the NMOS tube MN19 is started, and the A point potential is pulled to a low level rapidly. Meanwhile, the Y point potential is gradually pulled to a high level, the R point potential is changed to a low level under the action of the acceleration pull-up circuit 006, and the B point potential is rapidly pulled to a high level under the action of two charging paths, namely R8 and MN17, so that the delay of signal transmission is reduced. And vice versa when the input signal VIN changes from high to low.
FIG. 7 is a diagram showing the waveforms of the operation of the highly reliable high-speed level shift circuit according to the present invention under the influence of dVSW/dt noise. When dVSW/dt noise exists, the potentials of the X point and the Y point are simultaneously pulled to a low level, so that the MN23 pipe and the MN24 pipe are turned off, the C point is pulled to a high level, the MOS pipes MN 11-14 are turned on, the S point and the R point are simultaneously pulled to a low level, and the state of the latch circuit 008 is kept, so that the dVSW/dt noise interference is avoided during signal transmission. Under the clamping action of the diodes D3-D6, the potentials of the X point and the Y point are limited between-VD and VDD+VD (VD is the voltage drop when the diodes are conducted), and the devices are protected from being damaged by dVSW/dt noise.
Claims (10)
1. A high-reliability high-speed level shift circuit based on gallium nitride technology comprises a voltage bias module, a current mirror module, a level conversion module, an acceleration pull-up module, a latch module, a dVSW/dt resisting module and an output stage module; the method is characterized in that: the voltage bias module comprises a voltage bias circuit 001, the current mirror module comprises a current mirror circuit 002, the level conversion module comprises level conversion branches 003 and 004, the accelerating pull-up module comprises accelerating pull-up circuits 005 and 006, the latch module comprises a latch circuit 007, the anti-dVSW/dt module comprises an anti-dVSW/dt circuit 008, and the output stage module comprises an output stage circuit 009; the input signal VIN and the signal VIN' passing through the inverter INV0 are respectively connected to the input ends of the level converting branches 003 and 004; the output ends of the level conversion branches 003 and 004 are respectively an X point and a Y point, and are respectively connected with the input ends of the acceleration pull-up circuits 005 and 006; the output ends of the acceleration pull-up circuits 005 and 006 are respectively connected to two input ends S and R of the latch circuit 007; the two output ends A and B of the latch circuit 007 are respectively connected with the sources of the auxiliary pull-up tubes of the acceleration pull-up circuits 006 and 005, so that an additional charging path is provided for the A and B points, and the signal turning speed of the A and B points is accelerated; an output terminal B of the latch circuit 007 is connected to an input terminal of the output stage circuit 009, and an output signal VOUT is obtained through the two inverters INV1 and INV2; the voltage bias circuit 001 provides a bias voltage, and after being copied by the MN3 and the MN4 in the current mirror circuit 002, the voltage bias circuit respectively supplies power to the level conversion branches 003 and 004; the X point and Y point of the output ends of the level conversion branches 003 and 004 are connected with the input end of the anti-dVSW/dt circuit 008, and the C point of the output end of the anti-dVSW/dt circuit 008 is connected with the grid electrode of the control tube in the accelerating pull-up circuits 005 and 006 and is used for temporarily pulling down the output signals S and R of the accelerating pull-up circuits 005 and 006 to a low level when dVSW/dt noise occurs.
2. The gallium nitride process-based high-reliability high-speed level shift circuit according to claim 1, wherein: the voltage bias circuit 001 comprises a current source I0 and an enhanced NMOS tube MN2; the connection relation of the voltage bias circuit 001 is: one end of the current source is connected with the drain electrode of the enhanced NMOS tube MN2, the grid electrode of the enhanced NMOS tube MN3 and the grid electrode of the enhanced NMOS tube MN4, the other end of the current source is connected with the power supply signal VDD of the low-voltage domain power supply rail, and the source electrode of the enhanced NMOS tube MN2 is connected with the ground signal VSS of the low-voltage domain power supply rail.
3. The gallium nitride process-based high-reliability high-speed level shift circuit according to claim 2, wherein: the current mirror circuit 002 comprises enhanced NMOS transistors MN 3-MN 4, and capacitors C1-C2; the connection relationship of the current mirror circuit 002 is: the grid electrode of the enhanced NMOS tube MN3 is connected with the drain electrode of the enhanced NMOS tube MN2, the grid electrode of the enhanced NMOS tube MN4 and one end of a current source I0, the drain electrode of the enhanced NMOS tube MN3 is connected with one end of a capacitor C1 and the source electrode of the enhanced NMOS tube MN5, the source electrode of the enhanced NMOS tube MN3 is connected with a ground signal VSS of a low-voltage domain power supply rail, the other end of the capacitor C1 is connected with the ground signal VSS of the low-voltage domain power supply rail, the drain electrode of the enhanced NMOS tube MN4 is connected with one end of the capacitor C2 and the source electrode of the enhanced NMOS tube MN6, the source electrode of the enhanced NMOS tube MN4 is connected with the ground signal VSS of the low-voltage domain power supply rail, and the other end of the capacitor C2 is connected with the ground signal VSS of the low-voltage domain power supply rail.
4. A high reliability high speed level shift circuit based on gallium nitride process according to claim 3, wherein: the level shift branch 003 comprises an enhanced NMOS MN5, a high voltage enhanced NMOS HMN1, a resistor R3, a diode D3, and a diode D5, and the level shift branch 004 comprises an enhanced NMOS MN6, a high voltage enhanced NMOS HMN2, a resistor R4, a diode D4, and a diode D6; the connection relation of the level shift branch 003 is: the grid electrode of the enhanced NMOS tube MN5 is connected with the input signal VIN, the source electrode of the enhanced NMOS tube MN5 is connected with the drain electrode of the enhanced NMOS tube MN3 and one end of a capacitor C1, the drain electrode of the enhanced NMOS tube MN5 is connected with the source electrode of the high-voltage enhanced NMOS tube HMN1, the grid electrode of the high-voltage enhanced NMOS tube HMN1 is connected with the power supply signal VDD of the low-voltage domain power supply rail, the drain electrode of the high-voltage enhanced NMOS tube HMN1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with the grid electrode of the enhanced NMOS tube MN7, the grid electrode of the enhanced NMOS tube MN9, the grid electrode of the enhanced NMOS tube MN23, one end of a resistor R3, one end of a diode D3 and one end of a diode D5, the other end of the resistor R3 is connected with the power supply signal VBST of the high-voltage domain power supply rail, and the other end of the diode D5 is connected with the ground signal VSW of the high-voltage domain power supply rail; the connection relation of the level converting branch 004 is as follows: the output end of the inverter INV0 is connected with the grid electrode of the enhanced NMOS tube MN6, the source electrode of the enhanced NMOS tube MN6 is connected with the drain electrode of the enhanced NMOS tube MN4 and one end of the capacitor C2, the drain electrode of the enhanced NMOS tube MN6 is connected with the source electrode of the high-voltage enhanced NMOS tube HMN2, the grid electrode of the high-voltage enhanced NMOS tube HMN2 is connected with the power supply signal VDD of the low-voltage domain power supply rail, the drain electrode of the high-voltage enhanced NMOS tube HMN2 is connected with one end of the resistor R2, the other end of the resistor R2 is connected with the grid electrode of the enhanced NMOS tube MN8, the grid electrode of the enhanced NMOS tube MN10, the grid electrode of the enhanced NMOS tube MN24, one end of the resistor R4, one end of the diode D4 and one end of the diode D6, the other end of the resistor R4 is connected with the power supply signal VBST of the high-voltage domain power supply rail, and the other end of the diode D6 is connected with the ground signal VSW of the high-voltage domain power supply rail.
5. The gallium nitride process-based high-reliability high-speed level shift circuit according to claim 4, wherein: the accelerating pull-up circuit 005 comprises an enhanced NMOS tube MN7, an enhanced NMOS tube MN9, an enhanced NMOS tube MN11, an enhanced NMOS tube MN13, an enhanced NMOS tube MN15, an enhanced NMOS tube MN17, a resistor R5, a capacitor C3 and a diode D1, and the accelerating pull-up circuit 006 comprises an enhanced NMOS tube MN8, an enhanced NMOS tube MN10, an enhanced NMOS tube MN12, an enhanced NMOS tube MN14, an enhanced NMOS tube MN16, an enhanced NMOS tube MN18, a resistor R6, a capacitor C4 and a diode D2; the connection relation of the acceleration pull-up circuit 005 is: the grid electrode of the enhanced NMOS tube MN7 is connected with the grid electrode of the enhanced NMOS tube MN23, the grid electrode of the enhanced NMOS tube MN9, one end of a resistor R3, one end of a diode D5 and one end of a resistor R1, the source electrode of the enhanced NMOS tube MN7 is connected with a ground signal VSW of a high-voltage domain power rail, the drain electrode of the enhanced NMOS tube MN7 is connected with the drain electrode of the enhanced NMOS tube MN11, the grid electrode of the enhanced NMOS tube MN15, the grid electrode of the enhanced NMOS tube MN17 and one end of the resistor R5, the other end of the resistor R5 is connected with one end of a diode D1 and one end of a capacitor C3, the other end of the diode D1 is connected with a power signal VBST of the high-voltage domain power rail, the source electrode of the enhanced NMOS tube 11 is connected with the ground signal VSW of the high-voltage domain power rail, the grid electrode of the enhanced NMOS tube MN11 is connected with the grid electrode of the enhanced NMOS tube MN13, the grid electrode of the enhanced NMOS tube MN12, the grid electrode of the enhanced NMOS tube MN14, one end of a resistor R9 and one end of a resistor R10, the source electrode of the enhanced NMOS tube MN9 is connected with a ground signal VSW of a high-voltage domain power supply rail, the drain electrode of the enhanced NMOS tube MN9 is connected with the source electrode of the enhanced NMOS tube MN15, the drain electrode of the enhanced NMOS tube MN13, the other end of a capacitor C3 and the grid electrode of the enhanced NMOS tube MN19, the drain electrode of the enhanced NMOS tube MN15 is connected with a power supply signal VBST of the high-voltage domain power supply rail, the source electrode of the enhanced NMOS tube MN17 is connected with the grid electrode of the enhanced NMOS tube MN21, the drain electrode of the enhanced NMOS tube MN22, one end of the resistor R8, the drain electrode of the enhanced NMOS tube MN20 and the input end of the inverter INV 1; the connection relationship of the acceleration pull-up circuit 006 is: the grid electrode of the enhanced NMOS tube MN8 is connected with the grid electrode of the enhanced NMOS tube MN24, the grid electrode of the enhanced NMOS tube MN10, one end of a resistor R4, one end of a diode D6 and one end of a resistor R2, the source electrode of the enhanced NMOS tube MN8 is connected with a ground signal VSW of a high-voltage domain power rail, the drain electrode of the enhanced NMOS tube MN8 is connected with the drain electrode of the enhanced NMOS tube MN12, the grid electrode of the enhanced NMOS tube MN16, the grid electrode of the enhanced NMOS tube MN18 and one end of the resistor R6, the other end of the resistor R6 is connected with one end of a diode D2 and one end of a capacitor C4, the other end of the diode D2 is connected with a power signal VBST of the high-voltage domain power rail, the source electrode of the enhanced NMOS tube 12 is connected with the ground signal VSW of the high-voltage domain power rail, the grid of the enhanced NMOS tube MN12 is connected with the grid of the enhanced NMOS tube MN14, the grid of the enhanced NMOS tube MN11, the grid of the enhanced NMOS tube MN13, one end of a resistor R9 and one end of a resistor R10, the source of the enhanced NMOS tube MN10 is connected with a ground signal VSW of a high-voltage domain power supply rail, the drain of the enhanced NMOS tube MN10 is connected with the source of the enhanced NMOS tube MN16, the drain of the enhanced NMOS tube MN14, the other end of a capacitor C4 and the grid of the enhanced NMOS tube MN20, the drain of the enhanced NMOS tube MN16 is connected with a power supply signal VBST of the high-voltage domain power supply rail, the drain of the enhanced NMOS tube MN18 is connected with the grid of the enhanced NMOS tube MN22, the drain of the enhanced NMOS tube MN21, one end of the resistor R7 and the drain of the enhanced NMOS tube MN 19.
6. The gallium nitride process-based high-reliability high-speed level shift circuit according to claim 5, wherein: the auxiliary latch circuit 007 comprises an enhanced NMOS tube MN19, an enhanced NMOS tube MN20, an enhanced NMOS tube MN21, an enhanced NMOS tube MN22, a resistor R7 and a resistor R8; the connection relation is as follows: the grid electrode of the enhanced NMOS tube MN19 is connected with the drain electrode of the enhanced NMOS tube MN9, the source electrode of the enhanced NMOS tube MN15, the drain electrode of the enhanced NMOS tube MN13 and the other end of the capacitor C3, the grid electrode of the enhanced NMOS tube MN20 is connected with the drain electrode of the enhanced NMOS tube MN10, the source electrode of the enhanced NMOS tube MN16, the drain electrode of the enhanced NMOS tube MN14 and the other end of the capacitor C4, the source electrode of the enhanced NMOS tube MN19 is connected with a ground signal VSW of a high-voltage domain power supply rail, the source electrode of the enhanced NMOS tube MN20 is connected with the ground signal VSW of the high-voltage domain power supply rail, the drain electrode of the enhanced NMOS tube MN19 is connected with the drain electrode of the enhanced NMOS tube MN21, the grid electrode of the enhanced NMOS tube MN22, one end of the resistor R7 and the source electrode of the enhanced NMOS tube MN18, the drain electrode of the enhanced NMOS tube MN20 is connected with the drain electrode of the enhanced NMOS tube MN22, one end of the grid electrode of the enhanced NMOS tube MN21, one end of the resistor R8, the source electrode of the enhanced NMOS tube MN17 and the input end of the inverter INV1, the source electrode of the enhanced NMOS tube 21 is connected with the ground signal VSW of the high-voltage domain power supply rail, the source of the source electrode of the enhanced NMOS tube is connected with the high-voltage domain power supply rail VSW, and the other end of the high-voltage domain power supply rail is connected with the high-voltage domain power supply signal VSW, and the high-voltage domain power supply rail, and the high-voltage domain power supply signal VSR 8.
7. The gallium nitride process-based high-reliability high-speed level shift circuit according to claim 6, wherein: the anti-dVSW/dt circuit 008 comprises an enhanced NMOS tube MN23, an enhanced NMOS tube MN24, a resistor R9 and a resistor R10; the connection relation is as follows: the grid of the enhanced NMOS tube MN23 is connected with the grid of the enhanced NMOS tube MN7, the grid of the enhanced NMOS tube MN9, one end of a resistor R1, one end of a resistor R3, one end of a diode D3 and one end of a diode D5, the grid of the enhanced NMOS tube MN24 is connected with the grid of the enhanced NMOS tube MN8, the grid of the enhanced NMOS tube MN10, one end of a resistor R2, one end of a resistor R4 and one end of a diode D4, one end of a diode D6, the source of the enhanced NMOS tube MN23 is connected with a ground signal VSW of a high-voltage domain power supply rail, the source of the enhanced NMOS tube MN24 is connected with the ground signal VSW of the high-voltage domain power supply rail, the drain of the enhanced NMOS tube MN24 is connected with one end of a resistor R10, the other end of the resistor R10 is connected with the resistor R9, the grid of the enhanced NMOS tube MN11, the grid of the enhanced NMOS tube MN13, the grid of the enhanced NMOS tube MN12 and the grid of the enhanced NMOS tube MN14, and the other end of the resistor R9 is connected with the ground signal VSW of the high-voltage domain power supply rail.
8. The gallium nitride process-based high-reliability high-speed level shift circuit according to claim 7, wherein: the output circuit 009 includes an inverter INV1, an inverter INV2; the connection relation is as follows: the input end of the inverter INV1 is connected with the source electrode of the enhanced NMOS tube MN17, the grid electrode of the enhanced NMOS tube MN21, the drain electrode of the enhanced NMOS tube MN22, one end of a resistor R8 and the drain electrode of the enhanced NMOS tube MN20, the output end of the inverter INV1 is connected with the input end of the inverter INV2, and the output end of the inverter INV2 is connected with the output signal VOUT.
9. The gallium nitride process-based high-reliability high-speed level shift circuit according to claim 8, wherein: the enhanced NMOS transistors MN2 to MN24 are enhanced gallium nitride field effect transistors, and the high-voltage enhanced NMOS transistors HMN1 to HMN2 are high-voltage enhanced gallium nitride field effect transistors.
10. The gallium nitride process-based high-reliability high-speed level shift circuit according to claim 7, wherein: the resistors R1-R10 are resistors based on gallium nitride technology, depletion type or enhancement type gallium nitride field effect transistors in a diode connection mode, depletion type or enhancement type gallium nitride field effect transistors biased by fixed voltage of a grid electrode, or resistors made of other materials under the gallium nitride technology, including metal film resistors and polysilicon resistors;
the diodes D1-D6 are depletion type or enhancement type gallium nitride field effect transistors in a diode connection mode, on-chip integrated diode devices or externally connected diode devices;
the inverters INV 0-INV 2 are resistance inverters or totem-pole type double-N output inverters based on gallium nitride technology;
the current source I0 is a current source formed by a depletion type gallium nitride field effect transistor and a depletion type or enhancement type gallium nitride field effect transistor with a grid electrode biased by a fixed voltage.
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| CN117254797A (en) * | 2023-09-11 | 2023-12-19 | 芯北电子科技(南京)有限公司 | Level shift circuit for quick response of wide working voltage amplitude of DC-DC drive |
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| CN117254797A (en) * | 2023-09-11 | 2023-12-19 | 芯北电子科技(南京)有限公司 | Level shift circuit for quick response of wide working voltage amplitude of DC-DC drive |
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