CN220527920U - Motor driving circuit and driving circuit thereof - Google Patents

Abstract

The application discloses motor drive circuit and drive circuit thereof, drive circuit includes: the first adjusting unit comprises a first transistor and a second transistor, the first transistor is connected between the signal output end and the power supply ground end and is controlled to be conducted based on an input signal to enable the signal output end to be communicated with the power supply ground end, and the second transistor is connected between the signal output end and the power supply end and is controlled to be conducted based on the input signal to enable the signal output end to be communicated with the power supply end; the second adjusting unit comprises a third transistor which is connected between the signal output end and the power supply ground end, and when the voltage of the signal output end is lower than a preset threshold value, the first transistor and the third transistor are controlled to be conducted so as to enable the signal output end to be communicated with the power supply ground end. According to the driving circuit provided by the disclosure, on the premise of meeting the requirement of the system on off impedance, the optimization of the off rate can be realized, so that the voltage impact stress of the transistor at the off time is reduced, and the reliability of the system is further improved.

Description

Motor driving circuit and driving circuit thereof

Technical Field

The utility model relates to the technical field of motor driving, in particular to a motor driving circuit and a driving circuit thereof.

Background

The IPM (Intelligent Power Module ) is a novel high-power electronic device, has the advantages of high current density, low saturation voltage, high voltage resistance and the like, and is widely applied to various application fields such as frequency conversion speed regulation of an electric control system. An IPM module for motor driving includes at least two-phase half-bridge driving circuits. A grid driving chip is needed in each phase of half-bridge driving circuit to drive the power tube in one phase of half-bridge, so that an input signal is converted into an output signal for driving the motor to operate.

Since the gate driving chip in the IPM is applied to an environment of high withstand voltage, high current, and high power. Therefore, when the grid driving chip controls to turn off the power tube, higher voltage stress impact can be generated, and the reliability of the power tube is extremely high. Thereby affecting the reliability of the intelligent power module.

Disclosure of Invention

In view of the above problems, an object of the present utility model is to provide a motor driving circuit and a driving circuit thereof, which control the power tube to be turned off by two-stage driving, so as to reduce the voltage stress impact of the system on the power tube at the time of turning off the driving circuit, and enhance the reliability of the motor driving circuit.

According to an aspect of the present utility model, there is provided a driving circuit including:

the first adjusting unit is connected with the signal input end to receive an input signal, and comprises a first transistor and a second transistor, wherein the first transistor is connected between the signal output end and the power supply ground end and is controlled to be conducted based on the input signal so as to communicate the signal output end with the power supply ground end, and the second transistor is connected between the signal output end and the power supply end and is controlled to be conducted based on the input signal so as to communicate the signal output end with the power supply end; and

the second adjusting unit receives an input signal and is connected with the signal output end, the second adjusting unit comprises a third transistor, the third transistor is connected between the signal output end and the power supply ground end, when the voltage of the signal output end is lower than a preset threshold value, the first adjusting unit controls the first transistor to be conducted so as to enable the signal output end to be communicated with the power supply ground end, and the second adjusting unit controls the third transistor to be conducted so as to enable the signal output end to be communicated with the power supply ground end.

Optionally, the off-impedance of the first transistor is greater than the off-impedance of the third transistor.

Optionally, the first adjusting unit further includes:

And the input end of the NOT gate receives an input signal, the output signal of the NOT gate is output to the control end of the second transistor and the control end of the first transistor, and the second transistor and the first transistor are alternately conducted based on the input signal.

Optionally, the second transistor and the first transistor are PMOS transistors and NMOS transistors.

Optionally, the second transistor and the first transistor are an NMOS transistor and a PMOS transistor.

Optionally, the first adjusting unit further includes:

and the first buffer is connected between the signal input end and the input end of the NOT gate.

Optionally, the first adjusting unit further includes:

and the second buffer is connected between the output end of the NOT gate and the control end of the second transistor.

Optionally, the first adjusting unit further includes:

and a third buffer connected between the output terminal of the NOT gate and the control terminal of the first transistor.

Optionally, the second adjusting unit includes:

the input end of the Schmitt trigger is connected with the signal output end;

and the R input end of the RS trigger is connected with the signal input end, the S input end of the RS trigger is connected with the output end of the Schmitt trigger, and the control end of the third transistor receives the output signal of the RS trigger.

Optionally, the output end of the schmitt trigger generates level inversion when the voltage of the signal output end is lower than the preset threshold value, and the output end of the RS trigger generates level inversion based on the output end of the schmitt trigger to control the third transistor to be turned on.

Optionally, the preset threshold is a flip-flop voltage threshold of the schmitt trigger.

Optionally, the second adjusting unit further includes:

and a fourth buffer connected between the output terminal of the RS flip-flop and the control terminal of the third transistor.

Optionally, the driving circuit is a high-side driving circuit, and the high-side driving circuit includes: a high-side input signal end, a high-side output signal end, a high-side power supply end and a high-side power supply ground end,

the signal input end is used as a high-side signal input end, the signal output end is used as a high-side signal output end, the power supply end is used as a high-side power supply end, and the power supply ground end is used as a high-side power supply ground end; the high-side driving circuit is connected between the high-side input signal end and the high-side output signal end; the preset threshold is a first threshold.

Optionally, the driving circuit is a low-side driving circuit, and the low-side driving circuit includes: a low-side signal input terminal, a low-side signal output terminal, a low-side power supply terminal, and a low-side power supply ground terminal,

The signal input end is used as a low-side signal input end, the signal output end is used as a low-side signal output end, the power supply end is used as a low-side power supply end, and the power supply ground end is used as a low-side power supply ground end; the low-side driving circuit is connected between the low-side input signal end and the low-side output signal end; the preset threshold is a second threshold.

According to another aspect of the present utility model, there is provided a motor driving circuit including:

the first end of the first high-side transistor and the first end of the second high-side transistor are connected with a high-side power supply end;

a first low-side transistor, a first end of the first low-side transistor being connected to a second end of the first high-side transistor, the first end of the first low-side transistor being connected to a first high-side power ground, and the first end of the first low-side transistor being connected to the motor, the second end of the first low-side transistor being connected to a low-side power ground;

a second low-side transistor, a first end of the second low-side transistor being connected to a second end of the second high-side transistor, a first end of the second low-side transistor being connected to a second high-side power ground, and a first end of the second low-side transistor being connected to the motor, a second end of the second low-side transistor being connected to a low-side power ground;

The grid driving circuit comprises a high-side driving circuit and a low-side driving circuit, the high-side driving circuit is the driving circuit, the low-side driving circuit is the driving circuit, wherein the control end of a first high-side transistor is connected with the high-side signal output end of the first grid driving circuit, the control end of a first low-side transistor is connected with the low-side signal output end of the first grid driving circuit, the control end of a second high-side transistor is connected with the high-side signal output end of the second grid driving circuit, and the control end of the second low-side transistor is connected with the low-side signal output end of the second grid driving circuit; and

the first diode is connected between the high-side power supply end and the low-side power supply end of the first grid driving circuit;

and the second diode is connected between the high-side power supply end and the low-side power supply end of the second grid driving circuit.

The utility model provides a motor driving circuit, a grid driving circuit and a driving circuit thereof, wherein when a pull-down signal output end (a high-side signal output end or a low-side signal output end) is used for enabling a power tube (a high-side transistor or a low-side transistor) in a corresponding phase half-bridge driving circuit to be in an off state, the pull-down signal output end is divided into two pull-down stages. The power tube corresponding to the first pull-down stage has large current, so that the turn-off rate of the power tube can be effectively reduced and the voltage stress of the power tube can be reduced only by pulling down the signal output end by the first adjusting unit. When the voltage at the signal output end is lower than a first threshold (for example, the starting voltage of a high-side transistor), the current of the power tube is smaller at the moment, the second pull-down stage is carried out, the first adjusting unit and the second adjusting unit are adopted to pull down the signal output end at the same time, the power tube can be rapidly closed, and the requirement of the system on the driving turn-off impedance is met.

Drawings

The above and other objects, features and advantages of the present utility model will become more apparent from the following description of embodiments of the present utility model with reference to the accompanying drawings, in which:

FIG. 1 shows a schematic diagram of a motor drive circuit;

FIG. 2 shows a schematic diagram of a high-side drive circuit in a motor drive circuit;

fig. 3 shows a schematic diagram of a driving circuit according to an embodiment of the present utility model;

fig. 4 shows a schematic diagram of a structure of a gate driving circuit provided according to an embodiment of the present utility model;

fig. 5 shows a circuit schematic of a gate driving circuit provided according to an embodiment of the present utility model;

fig. 6 shows a waveform schematic diagram of a high-side driving circuit in a gate driving circuit according to an embodiment of the present utility model.

Detailed Description

Various embodiments of the present utility model will be described in more detail below with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For clarity, the various features of the drawings are not drawn to scale.

Fig. 1 shows a schematic diagram of a motor drive circuit. Fig. 2 shows a schematic diagram of a high-side driving circuit in a motor driving circuit.

As shown in fig. 1, the intelligent power module is used for driving the motor M, and the intelligent power module includes, for example, a two-phase half-bridge driving circuit. The one-phase half-bridge driving circuit comprises a gate driving circuit 110, a high-side transistor M1, a low-side transistor M2, a diode D1, a capacitor C0 and a capacitor C1, wherein the diode D1, the capacitor C0 and the capacitor C1 are arranged on the periphery of the gate driving circuit 110, and the other-phase half-bridge driving circuit comprises a gate driving circuit 110, a high-side transistor M3, a low-side transistor M4, and a diode D2, the capacitor C2 and the capacitor C3, which are arranged on the periphery of the gate driving circuit 110. Further, the gate driving circuit 110 of one side shown in fig. 1 supplies driving signals to the high-side transistor M1 and the low-side transistor M2, and thereby drives the corresponding phases of the motor M via the high-side transistor M1 and the low-side transistor M2. Fig. 1 shows that the gate driving circuit 110 of the other side provides driving signals to the high-side transistor M3 and the low-side transistor M4, thereby driving the corresponding phases of the motor M via the high-side transistor M3 and the low-side transistor M4. Further, when the high-side transistor M1 and the low-side transistor M4 are turned on, the motor M rotates forward. When the high-side transistor M3 and the low-side transistor M2 are turned on, the motor M is inverted. The inductance Lp1, the inductance Lp2, and the inductance Lp3 are parasitic inductances on the peripheral circuit wiring of the gate driving circuit 110 in the one-phase half-bridge driving circuit. The inductance Lp4, the inductance Lp5, and the inductance Lp6 are parasitic inductances on the peripheral circuit wiring of the gate driving circuit 110 in the other-phase half-bridge driving circuit.

The gate driving circuit 110 includes a plurality of pins, and pin names and descriptions are shown in the following table.

TABLE 1 Pin names of Gate drive circuits in Intelligent Power modules and descriptions thereof

Pin name	Pin specification
		HIN	High-side signal input terminal
LIN	Low side signal input terminal
		VCC	Low side power supply terminal
GND	Low side power supply ground terminal
		LO	Low side signal output terminal
VS	High-side power supply ground terminal
		HO	High-side signal output terminal
VB	High-side power supply terminal

The control terminal of the high-side transistor M1 is connected to the high-side signal output terminal HO of the gate driving circuit 110 to receive the high-side driving signal, and the control terminal of the low-side transistor M2 is connected to the low-side signal output terminal LO of the gate driving circuit 110 to receive the low-side driving signal. A capacitor C0 is externally connected between the high-side power supply terminal VB and the high-side power supply ground terminal VS of the gate driving circuit 110. A diode D1 is externally connected between the low-side power supply terminal VCC and the high-side power supply terminal VB of the gate driving circuit 110, wherein an anode of the diode D1 is connected to the low-side power supply terminal VCC, and a cathode of the diode D1 is connected to the high-side power supply terminal VB. The gate driving circuit 110 has a capacitor C1 connected between the low side power supply terminal VCC and the low side power supply ground terminal GND and is grounded. The high-side signal input HIN and the low-side signal input LIN of the gate drive circuit 110 receive control signals provided by a microcontroller, for example.

The control terminal of the high-side transistor M3 is connected to the high-side signal output terminal HO of the gate driving circuit 110 to receive the high-side driving signal, and the control terminal of the low-side transistor M4 is connected to the low-side signal output terminal LO of the gate driving circuit 110 to receive the low-side driving signal. A capacitor C3 is externally connected between the high-side power supply terminal VB and the high-side power supply ground terminal VS of the gate driving circuit 110. A diode D2 is externally connected between the low-side power supply terminal VCC and the high-side power supply terminal VB of the gate driving circuit 110, wherein an anode of the diode D2 is connected to the low-side power supply terminal VCC, and a cathode of the diode D2 is connected to the high-side power supply terminal VB. The gate driving circuit 110 has a capacitor C2 connected between the low side power supply terminal VCC and the low side power supply ground terminal GND and is grounded. The high-side signal input HIN and the low-side signal input LIN of the gate drive circuit 110 receive control signals provided by a microcontroller, for example.

Taking the illustrated lower half-bridge driving circuit as an example, when the high-side transistor M1 is turned off, a voltage pulse is generated between the node M1d and the node M1s due to the parasitic inductances (Lp 1, lp2, lp 3), so that the voltage V is applied to both ends of the high-side transistor M1 _p Higher voltage surges, which is detrimental to high voltage motor drive reliability. Similarly, taking the upper half-bridge driving circuit as an example, when the high-side transistor M3 is turned off, a voltage pulse is generated between the node M3d and the node M3s due to parasitic inductances (Lp 4, lp5, lp 6), so that the voltage V is applied to both ends of the high-side transistor M3 _p Higher voltage surges, which is detrimental to high voltage motor drive reliability.

Illustratively, the drain terminal voltage of the high-side transistor M1Wherein L is _p2 An inductance value of the inductance Lp2, I ₀ To flow a current through the first high-side power ground VS1 of the intelligent power module along the high-side power supply VP of the intelligent power module. Source terminal voltage of high-side transistor M1 +.> Wherein L is _p3 The inductance value of the inductance Lp3, V _S1 Is the voltage of the first high-side power ground VS1 of the intelligent power module. The voltage of the first high-side power ground VS1 with the high-side transistor M1 turned off +.>Wherein L is _p1 An inductance value of the inductance Lp1, I ₁ Is the current flowing through the first high-side power ground VS1 of the smart power module along the ground GND of the smart power module. To sum up, drain-source voltage difference of high-side transistor M1> When the high-side transistor M1 is turned off, the low-side transistor M2 is turned on, and the current I0 decreases and the current I1 increases from the parasitic inductance Lp6 to the low-side transistor M4 to the low-side transistor M2 to the parasitic inductance Lp 1. And then (I)>Voltage V corresponding to drain-source terminal of high-side transistor M1 _M1ds Specific bus voltage V _p Much larger.

Similarly, the drain voltage of the high-side transistor M3Wherein L is _p4 An inductance value of the inductance Lp4, I ₂ To flow a current along the high-side power supply terminal VP of the intelligent power module through the second high-side power supply ground terminal VS2 of the intelligent power module. Source terminal voltage of high-side transistor M3 +.> Wherein L is _p5 The inductance value of the inductance Lp5 is V _S2 Is the voltage of the second high-side power ground VS2 of the intelligent power module. The voltage of the second high-side power ground VS2 with the high-side transistor M3 turned off +.>Wherein L is _p6 An inductance value of the inductance Lp6, I ₃ Is the current flowing through the second high-side power ground VS2 of the smart power module along the ground GND of the smart power module. To sum up, drain-source voltage difference of high-side transistor M3>When the high-side transistor M3 is turned off, the low-side transistor M4 is turned on, and the current I2 decreases and the current I3 increases from the parasitic inductance Lp1 to the low-side transistor M2 to the low-side transistor M4 to the parasitic inductance Lp 6. And then (I)>Voltage V of drain-source terminal of corresponding high-side transistor M3 _M3ds Specific bus voltage V _p Much larger.

Taking the lower half-bridge driving circuit shown in fig. 1 as an example, when the low-side transistor M2 is turned off, a voltage pulse is generated between the node M2d and the node M2s due to parasitic inductances (Lp 1, lp2, lp 3), resulting in that the two ends of the low-side transistor M2 bear a bus voltage V _p Higher voltage surges, which is detrimental to high voltage motor drive reliability. Similarly, taking the upper half-bridge driving circuit shown in fig. 1 as an example, when the low-side transistor M4 is turned off, due to parasitic inductances (Lp 4, lp5, lp 6), a voltage pulse is generated between the node M4d and the node M4s, so that the two ends of the low-side transistor M4 receive the specific bus voltage V _p Higher voltage surges, which is detrimental to high voltage motor drive reliability.

Illustratively, the drain terminal voltage of the low-side transistor M2Wherein L is _p1 An inductance value of the inductance Lp1, I ₁ To get intelligentThe ground GND of the power module is capable of flowing through the current of the first high-side power supply ground VS1 of the intelligent power module. The voltage of the first high-side power ground VS1 with the low-side transistor M2 turned offWherein L is _p2 An inductance value L of the inductance Lp2 _p3 An inductance value of the inductance Lp3, I ₀ To flow a current through the first high-side power ground VS1 of the intelligent power module along the high-side power supply VP of the intelligent power module. To sum up, drain-source voltage difference of low-side transistor M2>When the low-side transistor M2 is turned off, the high-side transistor M1 is turned on. The freewheeling path is from parasitic inductance Lp5 to high-side transistor M3 to parasitic inductance Lp4 to parasitic inductance Lp2 to high-side transistor M1 to parasitic inductance Lp3, and current I0 gradually increases and current I1 gradually decreases. And then (I) >Drain-source voltage V of corresponding low-side transistor M2 _M2ds Specific bus voltage V _p Much larger. Also, there is a risk of overpressure shock.

Similarly, the drain voltage of the low-side transistor M4Wherein L is _p3 An inductance value of the inductance Lp3, I ₃ Is the current flowing through the second high-side power ground VS2 of the smart power module along the ground GND of the smart power module. The voltage of the second high-side power ground VS2 with the low-side transistor M4 turned offWherein L is _p4 An inductance value L of the inductance Lp4 _p5 An inductance value of the inductance Lp5, I ₂ To flow a current along the high-side power supply terminal VP of the intelligent power module through the second high-side power supply ground terminal VS2 of the intelligent power module. To sum up, the low sideDrain-source voltage difference of transistor M4>When the low-side transistor M4 is turned off, the high-side transistor M3 is turned on. The freewheeling path is from parasitic inductance Lp3 to high-side transistor M1 to parasitic inductance Lp2 to parasitic inductance Lp4 to high-side transistor M3 to parasitic inductance Lp5, and current I2 gradually increases and current I3 gradually decreases. And then (I)>Drain-source voltage V of corresponding low-side transistor M4 _M4ds Specific bus voltage V _p Much larger. Also, there is a risk of overpressure shock.

As shown in fig. 2, one of the high-side driving circuits 111 of the gate driving circuit 110 is connected between the high-side signal input terminal HIN, the high-side signal output terminal HO, the high-side power supply terminal VB, and the high-side power supply ground terminal VS of the gate driving circuit 110. The high-side driving circuit 111 includes an NOT gate NOT1, an NOT gate NOT2, an NOT gate NOT3, an NOT gate NOT4, an NOT gate NOT5, a pull-up pipe MP1, and a pull-down pipe MN1. When the high-side signal input terminal HIN is at a high level, the pull-up tube MP1 is turned on, the pull-down tube MN1 is turned off, and the voltage at the high-side signal output terminal HO is pulled up, so that the high-side signal output terminal HO outputs a control signal to control the turn-on of the M1. When the high-side signal input terminal HIN is at a low level, the pull-up tube MP1 is turned off, and the pull-down tube MN1 is turned on, so that the voltage at the high-side signal output terminal HO is pulled down, and the control signal control M1 is outputted by the high-side signal output terminal HO to be turned off.

The high-side driving circuit 111 pulls down the high-side signal output terminal HO with a transistor MN1 (NMOS transistor) connected between the high-side signal output terminal HO and the high-side power supply ground terminal VS, thereby directly turning off the high-side transistor (for example, NMOS transistor) connected thereto. Since the impedance of the high-side transistor in the off state is small, this causes the high-side transistor M1 to be turned off too quickly at the moment when the high-side signal output terminal HO is pulled down by the high-side driving circuit 111 of the gate driving circuit 110, resulting inToo large, enterThe voltage stress impact born by the high-side transistor M1 is larger, and the voltage stress is easy to exceed the voltage-resistant range of the high-side transistor M1, so that the high-side transistor M1 is damaged or broken down, and further, the high-side transistor reliability is more required.

Fig. 3 shows a schematic diagram of a driving circuit according to an embodiment of the present utility model.

As shown IN fig. 3, the driving circuit 311 is connected between the signal input terminal IN, the signal output terminal OUT, the power supply terminal V1, and the power supply ground terminal V2. The driving circuit 311 includes a first adjustment unit 3111 and a second adjustment unit 3112.

The first adjustment unit 3111 is connected to the signal input terminal IN, receives an input signal, and controls the signal output terminal OUT to communicate with the power supply terminal V1 or with the power supply ground terminal V2 based on the input signal. The first adjustment unit 3111 includes a first transistor MN2 and a second transistor MP1, the first transistor MN2 being connected between the signal output terminal OUT and the power supply ground terminal V2 and being controlled to be turned on based on an input signal to communicate the signal output terminal OUT with the power supply ground terminal V2. The second transistor MP1 is connected between the signal output terminal OUT and the power supply terminal V1 and is controlled to be turned on based on an input signal to communicate the signal output terminal OUT with the power supply terminal V1.

The second adjustment unit 3112 receives an input signal and is connected to the signal output terminal OUT. The second adjustment unit 3112 includes a third transistor MN3, the third transistor MN3 is connected between the signal output terminal OUT and the power supply ground terminal V2, when the voltage of the signal output terminal OUT is lower than a preset threshold, the first adjustment unit 3111 controls the first transistor MN2 to be turned on to communicate the signal output terminal OUT with the power supply ground terminal V1, and the second adjustment unit 3112 controls the third transistor MN3 to be turned on to communicate the signal output terminal OUT with the power supply ground terminal V2.

Wherein, the off-impedance of the first transistor MN2 is greater than the off-impedance of the third transistor MN 3. That is, the driving circuit 311 of the present embodiment is divided into two pull-down stages when pulling down the signal output terminal OUT. The first pull-down stage only uses the first adjusting unit 3111 to pull down the signal output OUT, and the driving turn-off current provided by the first adjusting unit 3111 is smaller at this time, so that the turn-off rate can be effectively reduced. When the voltage at the signal output terminal OUT is lower than the first threshold value, a second pull-down stage is entered, and the signal output terminal OUT is pulled down simultaneously by adopting the first adjustment unit 3111 and the second adjustment unit 3112, and at this time, the driving turn-off current provided by the first adjustment unit 3111 and the second adjustment unit 3112 is larger, so that the correspondingly connected power tube can be turned off quickly, and the requirement of the system on the driving turn-off impedance is met.

The first adjustment unit 3111 includes an NOT gate NOT0, a second transistor MP1, and a first transistor MN2. The input of the NOT gate NOT0 is connected to the signal input IN and receives the input signal. The second transistor MP1 is connected between the power supply terminal V1 and the signal output terminal OUT, and the control terminal of the second transistor MP1 is connected with the output terminal of the nand gate NOT 0. The first transistor MN2 is connected between the signal output terminal OUT and the power supply ground terminal V2, and the control terminal of the first transistor MN2 is connected to the output terminal of the nand gate NOT0, wherein the second transistor MP1 and the first transistor MN2 are alternately turned on based on the input signal. Further, a first terminal of the second transistor MP1 is connected to the power supply terminal V1, and a second terminal of the second transistor MP1 is connected to the signal output terminal OUT. The first terminal of the first transistor MN2 is connected to the power supply ground terminal V2, and the second terminal of the first transistor MN2 is connected to the signal output terminal OUT. The second transistor MP1 and the first transistor MN2 are PMOS transistors and NMOS transistors. In an alternative embodiment, the second transistor MP1 and the first transistor MN2 are NMOS transistors and PMOS transistors.

IN other embodiments, the first adjusting unit 3111 further includes a first buffer U1 connected between the signal input IN and the input of the NOT gate NOT 0. The first adjustment unit 3111 further includes a second buffer U2 connected between the output of the NOT gate NOT0 and the control terminal of the second transistor MP 1. The first adjusting unit 2111 further includes a third buffer U3 connected between the output terminal of the NOT gate NOT0 and the control terminal of the first transistor MN2. The first adjustment unit 3111 includes one, two, or three of the first buffer U1, the second buffer U2, and the third buffer U3.

The second adjustment unit 3112 includes, for example, a schmitt trigger J0, an RS trigger RS1, and a third transistor MN3. The input terminal of the schmitt trigger J0 is connected to the signal output terminal OUT. The R input end of the RS trigger RS1 is connected with the signal input end IN, and the S input end of the RS trigger RS1 is connected with the output end of the Schmitt trigger J0. The third transistor MN3 is connected between the signal output terminal OUT and the power supply ground terminal V2, and a control terminal of the third transistor MN3 is connected to the output terminal Q of the RS flip-flop RS 1. The output terminal of the schmitt trigger J0 performs level inversion when the voltage of the signal output terminal OUT is lower than a preset threshold value. The preset threshold is the flip-flop voltage threshold of the schmitt trigger J0. The output terminal of the RS flip-flop RS1 is level-flipped based on the output terminal of the schmitt trigger J0 to control the third transistor MN3 to be turned on. Further, a first terminal of the third transistor MN3 is connected to the power supply ground terminal V2, and a second terminal of the third transistor MN3 is connected to the signal output terminal OUT.

In other embodiments, the second adjusting unit 3112 further includes a fourth buffer U4 connected between the output Q of the RS flip-flop RS1 and the control terminal of the third transistor MN3. The above-mentioned buffer plays the effect of signal enhancement.

The first transistor MN2 and the third transistor MN3 in the present embodiment are connected in parallel between the signal output terminal OUT and the power ground terminal V2, where the parallel impedance of the first transistor MN2 and the third transistor MN3 is equal to the impedance of the transistor MN1 in fig. 2, so as to meet the requirement of the system on the driving turn-off impedance. Further, the pull-down capability of the first transistor MN2 is smaller than that of the third transistor MN3, so that the turn-off rate can be optimized under the condition that the requirement of the system driving turn-off impedance is met, the voltage impact stress at the turn-off moment of the correspondingly connected power transistor is further reduced, and the reliability of the driving system is improved. Since the pull-down capability is lower as the off resistance is larger, the resistance of the first transistor MN2 is larger than that of the third transistor MN 3.

Further, the driving circuit may be a high-side driving circuit or a low-side driving circuit among gate driving circuits for driving the motor. Correspondingly, when the driving circuit is used as a low-side driving circuit, the signal input end IN is a low-side signal input end LIN, the signal output end OUT is a low-side signal output end LO, the power supply end V1 is a low-side power supply end VCC, the power supply ground end V2 is a low-side power supply ground end GND, and the preset threshold is a second threshold. Correspondingly, when the driving circuit is used as a high-side driving circuit, the signal input end IN is a high-side signal input end HIN, the signal output end OUT is a high-side signal output end HO, the power supply end V1 is a high-side power supply end VB, the power supply ground end V2 is a high-side power supply ground end VS, and the preset threshold is a first threshold.

Fig. 4 shows a schematic diagram of a structure of a gate driving circuit according to an embodiment of the present utility model. Fig. 5 shows a circuit schematic of a gate driving circuit according to an embodiment of the present utility model. Fig. 6 shows a waveform schematic diagram of a high-side driving circuit in a gate driving circuit according to an embodiment of the present utility model.

The present disclosure provides a gate driving circuit 210, so as to optimize the turn-off rate on the premise of meeting the requirement of the turn-off impedance of the system, thereby reducing the voltage impact stress of the high-side transistor and the low-side transistor at the turn-off time and further improving the reliability of the system.

As shown in fig. 4, the gate driving circuit 210 provided in this embodiment includes a high-side input signal terminal HIN, a high-side output signal terminal HO, a high-side power supply terminal VB, a high-side power supply ground terminal VS, a low-side signal input terminal LIN, a low-side signal output terminal LO, a low-side power supply terminal VCC, a low-side power supply ground terminal GND, a high-side driving circuit 211, and a low-side driving circuit 212. The high-side driving circuit 211 is connected between the high-side input signal terminal HIN and the high-side output signal terminal HO, and the low-side driving circuit 212 is connected between the low-side input signal terminal LIN and the low-side output signal terminal LO.

The gate driving circuit 210 is an integrated circuit or an integrated chip, for example.

Further, fig. 5 is incorporated. The high-side driving circuit 211 is connected among a high-side signal input terminal HIN, a high-side signal output terminal HO, a high-side power supply terminal VB, and a high-side power supply ground terminal VS of the gate driving circuit 210. The high-side driving circuit 211 includes a first adjusting unit 2111 and a second adjusting unit 2112. The first adjusting unit 2111 is connected to the high-side signal input terminal HIN, receives the high-side input signal, and controls the high-side signal output terminal HO to communicate with the high-side power supply terminal VB or to communicate with the high-side power supply ground terminal VS based on the high-side input signal. The second adjusting unit 2112 is connected to the high-side signal input HIN and the high-side signal output HO, and the second adjusting unit 2112 controls the high-side signal output HO to communicate with the high-side power supply ground VS when the high-side signal output HO is controlled to communicate with the high-side power supply ground VS based on the first adjusting unit 2111 and the voltage is lower than the first threshold. Wherein, the off-resistance of the first transistor MN2 connected between the high-side signal output terminal HO and the high-side power supply ground terminal VS in the first adjusting unit 2111 is larger than the off-resistance of the third transistor MN3 connected between the high-side signal output terminal HO and the high-side power supply ground terminal VS in the second adjusting unit 2112. That is, the high-side driving circuit 211 of the present embodiment divides the pull-down stage into two pull-down stages when pulling down the high-side signal output terminal HO to turn off the high-side transistor in the corresponding half-bridge driving circuit. The current of the high-side transistor corresponding to the first pull-down stage is large, so that only the first adjusting unit 2111 is used for pulling down the high-side signal output terminal HO, and at this time, the driving turn-off current provided by the first adjusting unit 2111 is smaller, so that the turn-off rate of the high-side transistor can be effectively reduced, and the voltage stress of the high-side transistor can be reduced. When the voltage at the high-side signal output terminal HO is lower than a first threshold (for example, the on voltage of the high-side transistor), the current of the high-side transistor is smaller at this time, and the high-side signal output terminal HO is pulled down simultaneously by adopting the first adjusting unit 2111 and the second adjusting unit 2112, and at this time, the driving off current provided by the first adjusting unit 2111 and the second adjusting unit 2112 is larger, so that the high-side transistor can be turned off quickly, and the requirement of the system on the driving off impedance is met.

Illustratively, the first adjusting unit 2111 includes an NOT gate NOT0, a second transistor MP1, and a first transistor MN2. The input terminal of the NOT gate NOT0 is connected to the high-side signal input terminal HIN and receives the high-side input signal. The second transistor MP1 is connected between the high-side power supply terminal VB and the high-side signal output terminal HO, and the control terminal of the second transistor MP1 is connected to the output terminal of the nand gate NOT 0. The first transistor MN2 is connected between the high-side signal output terminal HO and the high-side power supply ground terminal VS, and the control terminal of the first transistor MN2 is connected to the output terminal of the nand gate NOT0, where the second transistor MP1 and the first transistor MN2 are alternately turned on based on the high-side input signal. Further, a first terminal of the second transistor MP1 is connected to the high-side power supply terminal VB, and a second terminal of the second transistor MP1 is connected to the high-side signal output terminal HO. The first terminal of the first transistor MN2 is connected to the high-side power supply ground terminal VS, and the second terminal of the first transistor MN2 is connected to the high-side signal output terminal HO. The second transistor MP1 and the first transistor MN2 are PMOS transistors and NMOS transistors. In an alternative embodiment, the second transistor MP1 and the first transistor MN2 are NMOS transistors and PMOS transistors.

In other embodiments, the first adjusting unit 2111 further includes a first buffer U1 connected between the high-side signal input HIN and the input of the NOT gate NOT 0. The first adjusting unit 2111 further includes a second buffer U2 connected between the output terminal of the NOT gate NOT0 and the control terminal of the second transistor MP 1. The first adjusting unit 2111 further includes a third buffer U3 connected between the output terminal of the NOT gate NOT0 and the control terminal of the first transistor MN2. The first adjustment unit 2111 includes one, two, or three of the first buffer U1, the second buffer U2, and the third buffer U3.

The second adjustment unit 2112 includes, for example, a schmitt trigger J0, an RS trigger RS1, and a third transistor MN3. The input terminal of the schmitt trigger J0 is connected to the high-side signal output terminal HO. The R input end of the RS trigger RS1 is connected with the high-side signal input end HIN, and the S input end of the RS trigger RS1 is connected with the output end of the Schmitt trigger J0. The third transistor MN3 is connected between the high-side signal output terminal HO and the high-side power supply ground terminal VS, and the control terminal of the third transistor MN3 is connected to the output terminal Q of the RS flip-flop RS 1. The output terminal of the schmitt trigger J0 is turned over when the voltage of the high-side signal output terminal HO is lower than the first threshold. The first threshold is the flip-flop voltage threshold of the schmitt trigger J0. The output terminal of the RS flip-flop RS1 is level-flipped based on the output terminal of the schmitt trigger J0 to control the third transistor MN3 to be turned on. Further, a first terminal of the third transistor MN3 is connected to the high-side power supply ground terminal VS, and a second terminal of the third transistor MN3 is connected to the high-side signal output terminal HO.

In other embodiments, the second adjusting unit 2112 further includes a seventh buffer U4 connected between the output terminal Q of the RS flip-flop RS1 and the control terminal of the third transistor MN3. The above-mentioned buffer plays the effect of signal enhancement.

The first transistor MN2 and the third transistor MN3 in the present embodiment are connected in parallel between the high-side signal output terminal HO and the high-side power supply ground terminal VS, where the parallel impedance of the first transistor MN2 and the third transistor MN3 is equal to the impedance of the transistor MN1 in fig. 2, so as to meet the requirement of the system on the driving turn-off impedance. Further, the pull-down capability of the first transistor MN2 is smaller than that of the third transistor MN3, so that the turn-off rate can be optimized under the condition that the requirement of the system driving turn-off impedance is met, the voltage impact stress at the turn-off moment of the high-side transistor is further reduced, and the reliability of the driving system is improved. Since the pull-down capability is lower as the off resistance is larger, the resistance of the first transistor MN2 is larger than that of the third transistor MN 3.

The low-side driving circuit 212 is connected between the low-side signal input terminal LIN, the low-side signal output terminal LO, the low-side power supply terminal VCC, and the low-side power supply ground terminal GND of the gate driving circuit 210. The low-side driving circuit 212 includes a third adjusting unit 2121 and a fourth adjusting unit 2122. The third adjusting unit 2121 is connected to the low-side signal input terminal LIN, receives the low-side input signal, and controls the low-side signal output terminal LO to communicate with the low-side power supply terminal VCC or with the low-side power supply ground terminal GND based on the low-side input signal. The fourth adjusting unit 2122 is connected to the low-side signal input terminal LIN and the low-side signal output terminal LO, and the fourth adjusting unit 2122 controls the low-side signal output terminal LO to communicate with the low-side power supply ground GND when the low-side signal output terminal LO is controlled to communicate with the low-side power supply ground VCC based on the third adjusting unit 2121 and the voltage is lower than the second threshold. Wherein, the off impedance of the fourth transistor MN21 connected between the low-side signal output terminal LO and the low-side power supply ground GND in the third adjusting unit 2121 is larger than the off impedance of the sixth transistor MN31 connected between the low-side signal output terminal LO and the low-side power supply ground GND in the fourth adjusting unit 2122. That is, the low-side driving circuit 212 of the present embodiment is divided into two pull-down stages when the low-side signal output terminal LO is pulled down to turn off the low-side transistors in the corresponding half-bridge driving circuits. The current of the low-side transistor corresponding to the first pull-down stage is large, so that only the third adjusting unit 2121 is used for pulling down the low-side signal output terminal LO, and at this time, the driving turn-off current provided by the third adjusting unit 2121 is smaller, so that the turn-off rate of the low-side transistor can be effectively reduced, and the voltage stress of the low-side transistor can be reduced. When the voltage at the low-side signal output terminal LO is lower than a second threshold (for example, the on voltage of the low-side transistor), the current of the low-side transistor is smaller at this time, and the low-side signal output terminal LO is pulled down simultaneously by adopting the third adjusting unit 2121 and the fourth adjusting unit 2122, and at this time, the driving off current provided by the third adjusting unit 2121 and the fourth adjusting unit 2122 is larger, so that the low-side transistor can be turned off quickly, and the requirement of the system on the driving off impedance is met.

The third adjustment unit 2121 includes, illustratively, a NOT gate NOT1, a fifth transistor MP11, and a fourth transistor MN21. The input of the NOT-gate NOT1 is connected to the low-side signal input LIN and receives the low-side input signal. The fifth transistor MP11 is connected between the low-side power supply terminal VCC and the low-side signal output terminal LO, and the control terminal of the fifth transistor MP11 is connected to the output terminal of the nand gate NOT 1. The fourth transistor MN21 is connected between the low-side signal output terminal LO and the low-side power supply ground terminal GND, and the control terminal of the fourth transistor MN21 is connected to the output terminal of the nand gate NOT1, wherein the fifth transistor MP11 and the fourth transistor MN21 are alternately turned on based on the low-side input signal. Further, a first terminal of the fifth transistor MP11 is connected to the low-side power supply terminal VCC, and a second terminal of the fifth transistor MP11 is connected to the low-side signal output terminal LO. The first terminal of the fourth transistor MN21 is connected to the low-side power supply ground GND, and the second terminal of the fourth transistor MN21 is connected to the low-side signal output LO. The fifth transistor MP11 and the fourth transistor MN21 are PMOS transistors and NMOS transistors. In an alternative embodiment, the fifth transistor MP11 and the fourth transistor MN21 are an NMOS transistor and a PMOS transistor.

In other embodiments, the third adjusting unit 2121 further includes a fourth buffer U11 connected between the low-side signal input terminal LIN and the input terminal of the NOT gate NOT 1. The third adjusting unit 2121 further includes a fifth buffer U21 connected between the output terminal of the NOT gate NOT1 and the control terminal of the fifth transistor MP 11. The third adjusting unit 2121 further includes a sixth buffer U31 connected between the output terminal of the NOT gate NOT1 and the control terminal of the fourth transistor MN 21. The third adjustment unit 2121 includes one, two, or three of the fourth buffer U11, the fifth buffer U21, and the sixth buffer U31.

The fourth adjustment unit 2122 includes, for example, a schmitt trigger J1, an RS trigger RS2, and a sixth transistor MN31. The input of the schmitt trigger J1 is connected to the low-side signal output LO. The R input end of the RS trigger RS2 is connected with the low-side signal input end LIN, and the S input end of the RS trigger RS2 is connected with the output end of the Schmitt trigger J1. The sixth transistor MN31 is connected between the low-side signal output terminal LO and the low-side power supply ground terminal GND, and the control terminal of the sixth transistor MN31 is connected to the output terminal Q of the RS flip-flop RS 2. Wherein the output terminal of the schmitt trigger J1 is turned over in level when the voltage of the low-side signal output terminal LO is lower than the second threshold value. The second threshold is the flip-flop voltage threshold of the schmitt trigger J1. The output terminal of the RS flip-flop RS2 is turned over in level based on the output terminal of the schmitt trigger J1 to control the sixth transistor MN31 to be turned on. Further, a first terminal of the sixth transistor MN31 is connected to the low-side power supply ground GND, and a second terminal of the sixth transistor MN31 is connected to the low-side signal output LO.

In other embodiments, the second adjusting unit 2122 further includes an eighth buffer U41 connected between the output terminal Q of the RS flip-flop RS2 and the control terminal of the sixth transistor MN 31. The above-mentioned buffer plays the effect of signal enhancement.

The fourth transistor MN21 and the sixth transistor MN31 in the present embodiment are connected in parallel between the low-side signal output terminal LO and the low-side power ground terminal GND, where the parallel impedance of the fourth transistor MN21 and the sixth transistor MN31 is equal to the impedance of the transistor MN1 in fig. 2, so as to meet the requirement of the system on the driving turn-off impedance. Further, the pull-down capability of the fourth transistor MN21 is smaller than that of the sixth transistor MN31, so that the turn-off rate can be optimized under the condition that the requirement of the system driving turn-off impedance is met, the voltage impact stress at the turn-off moment of the low-side transistor is further reduced, and the reliability of the driving system is improved. Since the pull-down capability is lower as the off resistance is larger, the resistance of the fourth transistor MN21 is larger than that of the sixth transistor MN 31.

Referring to fig. 6, a waveform diagram of the high-side driving circuit 211 is shown. It will be appreciated that the waveform of the low-side drive circuit 212 is similar to the waveform of the high-side drive circuit 211. When the high-side signal input terminal HIN changes from high level to low level, the output terminal of the NOT gate NOT0 in the first adjusting unit outputs high level, and correspondingly, the levels of the control terminal mp1_g of the second transistor MP1 and the control terminal mn2_g of the first transistor MN2 change to high level, the second transistor MP1 is turned off, and the first transistor MN2 is turned on. Since the high-side signal output terminal HO is at the high level in the previous state, the output terminal of the schmitt trigger J0 is kept at the low level, and the level of the output terminal Q of the RS trigger is kept at the low level in the previous state, and accordingly the third transistor MN3 is turned off. At this time, the high-side driving circuit is in the first pull-down stage, and the turn-off impedance of the first transistor MN2 is according to the turn-off rate The method is characterized in that an optimal design is made, so that the drain-source overshoot voltage of the high-side transistor connected with the first pull-down stage is not too large.

In the first pull-down stage, the voltage of the high-side signal output terminal HO gradually decreases, and when the voltage is lower than the first threshold (also the flip-threshold of the schmitt trigger J0), the output level of the schmitt trigger J0 becomes high, and correspondingly the RS trigger is set, the voltage of the output terminal Q of the RS trigger becomes high, so that the third transistor MN3 is also turned on, and the high-side driving circuit enters the second pull-down stage. In the second pull-down stage, since the first transistor MN2 and the third transistor MN3 are turned on at the same time, the turn-off impedance is further reduced, so that the voltage of the high-side signal output terminal HO is rapidly reduced, and the system turn-off impedance requirement is satisfied.

It should be noted that, the high-side driving circuit and the low-side driving circuit in the gate driving circuit provided in the application all adopt the driving circuits described above. Or one of the two adopts the driving circuit and the other adopts any circuit structure in the prior art.

The driving circuit (high-side driving circuit and/or low-side driving circuit) provided by the embodiment can optimize the turn-off rate on the premise of meeting the requirement of the turn-off impedance of the system, so that the voltage impact stress of the power tube at the turn-off moment is reduced, and the reliability of the system is further improved. The control mode and the circuit have universality.

The present disclosure also provides a motor driving circuit including at least one phase half-bridge driving circuit to drive a motor. Each phase of half-bridge driving circuit comprises the grid driving circuit, a high-side transistor, a low-side transistor and a diode, so that the optimization of the turn-off rate can be realized on the premise of meeting the turn-off impedance requirement of the system, the voltage impact stress of the high-side transistor at the turn-off moment is reduced, and the reliability of the system is further improved. Further, the high-side transistor is turned off, and the drain-source voltage difference value of the high-side transistor is increased due to the follow current path of current in the circuit; and/or the low-side transistor is turned off, and the freewheeling path of the current in the circuit causes the drain-source voltage difference of the low-side transistor to increase.

The control end of the transistor is, for example, a gate of the MOS transistor, the first end of the transistor is, for example, a source of the MOS transistor, and the second end of the transistor is, for example, a drain of the MOS transistor.

Embodiments in accordance with the present utility model, as described above, are not intended to be exhaustive or to limit the utility model to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the utility model and the practical application, to thereby enable others skilled in the art to best utilize the utility model and various modifications as are suited to the particular use contemplated. The utility model is limited only by the claims and the full scope and equivalents thereof.

Claims (15)

1. A driving circuit, characterized by comprising:

the first adjusting unit is connected with the signal input end to receive an input signal, and comprises a first transistor and a second transistor, wherein the first transistor is connected between the signal output end and the power supply ground end and is controlled to be conducted based on the input signal so as to communicate the signal output end with the power supply ground end, and the second transistor is connected between the signal output end and the power supply end and is controlled to be conducted based on the input signal so as to communicate the signal output end with the power supply end; and

the second adjusting unit receives an input signal and is connected with the signal output end, the second adjusting unit comprises a third transistor, the third transistor is connected between the signal output end and the power supply ground end, when the voltage of the signal output end is lower than a preset threshold value, the first adjusting unit controls the first transistor to be conducted so as to enable the signal output end to be communicated with the power supply ground end, and the second adjusting unit controls the third transistor to be conducted so as to enable the signal output end to be communicated with the power supply ground end.

2. The driver circuit of claim 1, wherein the off-resistance of the first transistor is greater than the off-resistance of the third transistor.

3. The drive circuit according to claim 1 or 2, wherein the first adjustment unit further comprises:

and the input end of the NOT gate receives an input signal, the output signal of the NOT gate is output to the control end of the second transistor and the control end of the first transistor, and the second transistor and the first transistor are alternately conducted based on the input signal.

4. The driver circuit of claim 3, wherein the second transistor and the first transistor are PMOS transistors and NMOS transistors.

5. The driver circuit of claim 3, wherein the second transistor and the first transistor are an NMOS transistor and a PMOS transistor.

6. A driving circuit according to claim 3, wherein the first adjusting unit further comprises:

and the first buffer is connected between the signal input end and the input end of the NOT gate.

7. A driving circuit according to claim 3, wherein the first adjusting unit further comprises:

and the second buffer is connected between the output end of the NOT gate and the control end of the second transistor.

8. A driving circuit according to claim 3, wherein the first adjusting unit further comprises:

And a third buffer connected between the output terminal of the NOT gate and the control terminal of the first transistor.

9. The drive circuit according to claim 1 or 2, wherein the second adjustment unit includes:

the input end of the Schmitt trigger is connected with the signal output end;

and the R input end of the RS trigger is connected with the signal input end, the S input end of the RS trigger is connected with the output end of the Schmitt trigger, and the control end of the third transistor receives the output signal of the RS trigger.

10. The drive circuit of claim 9, wherein the output of the schmitt trigger is turned over in level when the voltage of the signal output is lower than the preset threshold, and the output of the RS trigger is turned over in level based on the output of the schmitt trigger to control the third transistor to be turned on.

11. The drive circuit of claim 10, wherein the predetermined threshold is a flip-flop voltage threshold of the schmitt trigger.

12. The drive circuit according to claim 9, wherein the second adjusting unit further comprises:

And a fourth buffer connected between the output terminal of the RS flip-flop and the control terminal of the third transistor.

13. The drive circuit of claim 1, wherein the drive circuit is a high-side drive circuit comprising: a high-side input signal end, a high-side output signal end, a high-side power supply end and a high-side power supply ground end,

the signal input end is used as a high-side signal input end, the signal output end is used as a high-side signal output end, the power supply end is used as a high-side power supply end, and the power supply ground end is used as a high-side power supply ground end; the high-side driving circuit is connected between the high-side input signal end and the high-side output signal end; the preset threshold is a first threshold.

14. The drive circuit of claim 1, wherein the drive circuit is a low-side drive circuit comprising: a low-side signal input terminal, a low-side signal output terminal, a low-side power supply terminal, and a low-side power supply ground terminal,

the signal input end is used as a low-side signal input end, the signal output end is used as a low-side signal output end, the power supply end is used as a low-side power supply end, and the power supply ground end is used as a low-side power supply ground end; the low-side driving circuit is connected between the low-side input signal end and the low-side output signal end; the preset threshold is a second threshold.

15. A motor drive circuit, characterized by comprising:

the first end of the first high-side transistor and the first end of the second high-side transistor are connected with a high-side power supply end;

a first low-side transistor, a first end of the first low-side transistor being connected to a second end of the first high-side transistor, the first end of the first low-side transistor being connected to a first high-side power ground, and the first end of the first low-side transistor being connected to the motor, the second end of the first low-side transistor being connected to a low-side power ground;

a second low-side transistor, a first end of the second low-side transistor being connected to a second end of the second high-side transistor, a first end of the second low-side transistor being connected to a second high-side power ground, and a first end of the second low-side transistor being connected to the motor, a second end of the second low-side transistor being connected to a low-side power ground;

a gate drive circuit comprising a high side drive circuit and a low side drive circuit, the high side drive circuit being the drive circuit of any one of claims 1-13, the low side drive circuit being the drive circuit of any one of claims 1-12, 14, wherein a control terminal of a first high side transistor is connected to a high side signal output terminal of the first gate drive circuit, a control terminal of a first low side transistor is connected to a low side signal output terminal of the first gate drive circuit, a control terminal of a second high side transistor is connected to a high side signal output terminal of the second gate drive circuit, and a control terminal of the second low side transistor is connected to a low side signal output terminal of the second gate drive circuit; and

The first diode is connected between the high-side power supply end and the low-side power supply end of the first grid driving circuit;

and the second diode is connected between the high-side power supply end and the low-side power supply end of the second grid driving circuit.