JP2003273714A - Load drive circuit and semiconductor device having load drive circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely prevent an arm of a totem pole circuit from being short- circuited without increasing the number of components and the size of the circuit. <P>SOLUTION: A main terminal of a MOSFET (P4) is connected between the gate of a MOSFET (N2) arranged on the upper arm side of the totem pole circuit (10) and an output (Vout) of the circuit (10) and the gate of the MOSFET (P4) is connected to the gate of the MOSFET (N2) through the gate resistor (R3) of the MOSFET (P4). The MOSFET (P4) is turned on when the potential of the output (Vout) is changed from high potential to low potential by a MOSFET (N1) arranged on the lower arm side of the circuit (10). <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a totem pole type load drive circuit composed of two insulated gate devices and a semiconductor device having the load drive circuit.

[0002]

2. Description of the Related Art A totem pole type load drive circuit (hereinafter referred to as a totem pole circuit) constructed by connecting two insulated gate devices in series is applied to a power converter for driving an electric motor or a drive circuit for a display. Has been done. The insulated gate device has a higher breakdown voltage, and by adopting a high breakdown voltage insulated gate device in the totem pole circuit, the applicable range of current and voltage handled by the totem pole circuit is expanded.

Further, due to advances in semiconductor isolation technology, a totem pole circuit composed of a high breakdown voltage insulated gate device and a peripheral circuit such as a drive circuit, a control circuit, and a protection circuit of the high breakdown voltage insulated gate device are the same. A power IC integrated on a semiconductor substrate is used. FIG. 4 is a diagram showing a conventional example of a totem pole circuit and its peripheral circuits.

In FIG. 4, reference numeral 10 is a circuit in which two n-channel MOSFETs (N1, N2) are connected in series as shown in the drawing, and is connected to a high-voltage DC power supply (VH), and N1,
It is a totem pole circuit that outputs (Vout) the connection point of N2. A load (for example, a light emitting element of a plasma display panel, which is a capacitive load) is connected to the output (Vout).

Reference numeral 21 is a drive circuit for driving a MOSFET (N2) connected to the upper arm side (high voltage side), 30
Is a low voltage DC power source (VL) as a power source
Low-voltage control signal (S for controlling ET (N1, N2)
1, S2), 41 is the control circuit 3
The control signal output from 0
It is a level shift circuit for converting to a voltage level necessary for driving T (N2).

A control signal (S
1, S2) are signals based on the lowest potential (Vss) in the circuit. Therefore, the MOSF connected to the side of the upper arm that operates based on the potential of the output (Vout)
ET (N2) cannot be directly driven by the output of the control signal 30. Therefore, the control signal (S2) is once input to the level shift circuit 41, converted into a signal with the potential of the output (Vout) as a reference by the level shift circuit, and then the signal is input to the drive circuit 21 to input the MOSFET.
Driving (N2).

The drive circuit 21 and the level shift circuit 41 can have various configurations other than those shown in the drawings, and other examples will be described later. When the circuit of FIG. 4 is used for driving an electric motor or a display, a voltage of several tens of volts or more is applied to the high voltage DC power supply (VH). For example, when used in a driving circuit of a plasma display panel, a voltage of 100 V or more is applied and a current of 200 mA or more flows.

For this reason, the MOSFETs (N1, N2) employ a device having a high withstand voltage and a large current drive capability capable of sufficiently driving the voltage and current, and the level shift circuit 4
A high breakdown voltage device is also used for the elements constituting the device 1. As shown in FIG. 4, a totem pole circuit using an n-channel type device is driven by a current per unit device area on a semiconductor substrate as compared with a push-pull circuit using a p-channel type device and an n-channel type device. Since it has a large capacity, it is suitable for driving a load that requires a large current.

Next, the operation of the circuit shown in FIG. 4 will be described. The control circuit 30 sets the output (Vout) to the H level (VH) or the L level (Vss) based on the control signal (S) input to the input terminal (Vin) from the signal processing circuit of the preceding stage (not shown). MOSFET (N1, N2)
For alternately turning on and off, that is, MOSFET
(N1) is turned off or on to turn on the MOSFET (N2)
Complementary control signals (S1, S2) are output at a low voltage for turning on and off. Vss is the lowest potential commonly connected to each circuit as shown.

In the example of FIG. 4, when the control signal (S2) is at the H level, the n-channel type MOSFET (N3) constituting the level shift circuit 41 is turned on, and the current IN3 flows through the resistor R2 to drive it. The p-channel MOSFET (P1) forming the circuit 21 is turned on. MOSFET (P
When 1) is turned on, the MOSFET (N2) is turned on and the voltage of the output (Vout) becomes VH. At this time, the control signal (S1) is at L level and the MOSFET (N1) is off.

In FIG. 4, a resistor (R1) constituting the drive circuit 21 is for obtaining a desired gate voltage by the current supplied by the MOSFET (P1), and a Zener diode (ZD) is a MOSFET (ZD). N
This is for suppressing the increase in the gate-source voltage of 2). On the contrary, the control signal (S2) becomes L level, the MOSFET (N2) is turned off, and the control signal (S1) becomes H level.
The MOSFET (N1) is turned on and the voltage of the output (Vout) becomes Vss.

Here, MOSFETs forming a series circuit
When (N1, N2) are simultaneously turned on, the DC power supply is short-circuited by the MOSFETs (N1, N2) (arm short circuit). When an arm short circuit occurs, not only the power consumption of the totem pole circuit is increased, but also the devices and loads forming the totem pole circuit may be destroyed.

Therefore, the control circuit 30 controls the control signal (S
The control signal (S2) changes from the L level to the H level a predetermined time after 1) changes from the H level to the L level, and vice versa.
The control signal (S1) is changed so that the control signal (S1) changes from the L level to the H level after a predetermined period of time after the level changes to the level.
A time difference (dead time) is provided between 1) and (S2) on / off.

This dead time depends on the MOSFET (N
1, N2) switching characteristics and load driving characteristics (output (Vout) output characteristics).

[0015]

In the circuit of FIG. 4,
MOSFET that constitutes the upper arm despite the dead time provided between the control signals (S1, S2)
MOS that constitutes the lower arm after (N2) is turned off once
There is a problem that the MOSFET (N2) is turned on again due to the voltage fluctuation of the output (Vout) terminal when the FET (N1) is turned on, and an arm short circuit occurs.

This phenomenon will be described by taking a case where a capacitive load is connected to the output (Vout) as an example. First MOSFET
(N2) turns off, and after dead time T elapses, MOSFE
When T (N1) is turned on, the output (Vout) voltage is VH
Abruptly changes from Vss to Vss. When the voltage of the output (Vout) sharply drops from VH, the MOSFET
Current IR2 via the drain-gate capacitance of (P1)
Flows.

IR2 flows as shown by an arrow in FIG. 4 to cause a voltage drop in the resistor R2, and this voltage drop causes a MOS drop.
The FET (P1) is driven and the current IP1 flows. The current IP1 flows through the resistor R1 and the MOSFET (N1). At this time, the resistor R1 causes the MOSFET to flow.
A voltage is applied to the gate of (N2), and this voltage is
When the threshold voltage of FET (N2) is exceeded, MOSFET
(N2) is turned on and the current IN2 flows.

At this time, since the MOSFET (N1) has already been turned on, the current IN2 changes to the MOSFET (N1).
1) to Vss, and a short circuit (arm short circuit) occurs between the DC power supplies. In this way, when an arm short circuit occurs in which the devices of the upper and lower arms are simultaneously turned on, not only the power consumption of the load drive circuit increases, but also the devices constituting the upper and lower arms or the load may be destroyed.

In the circuit shown in FIG. 4, the causes of arm short circuit are mainly the following two points. (1) A p-channel MOSFET is adopted to drive the device of the upper arm, and the p-channel MOS is used.
In order to drive the FET, a resistor R2 is provided between the gate of the p-channel MOSFET and the power supply. (2) The reference potential of the upper arm device (MOSFET (N2)) is the output (Vout), and the source potential fluctuates significantly.

Regarding the above (1), arm short circuit can be prevented by reducing the resistance value of R2, but the current of the MOSFET (N3) constituting the level shift circuit becomes large and the power consumption in the level shift circuit is increased. There is a problem that is increased. As a circuit that does not use the resistor R2, there is a level shift circuit shown in FIG. FIG. 5 is a diagram showing another level shift circuit (42).
ET (P2, N4) series circuit and MOSFET (P
3, N5) series circuits, and the connection point of the device in each series circuit is connected to the gate of the p-channel MOSFET.

Since such a circuit is well known, a detailed description thereof will be omitted, but complementary control signals (S1, S2) are input to the gates of the n-channel MOSFETs (N4, N5) and the voltage level of the control signal is set to the upper arm. The voltage is shifted to a voltage level sufficient to drive the device and output from the connection point of the series circuit. In FIG. 5, MOSFETs (P2, N4)
The connection point (A) is connected to the gate of the MOSFET (P1) to drive the MOSFET (P1).

Alternatively, the connection point (B) of the MOSFETs (P3, N5) may be connected to the gate of the MOSFET (N2) and the MOSFET (P1) may be omitted. In this case, the p-channel insulated gate device of the drive circuit also serves as the p-channel insulated gate device of the level shift circuit. Even when the level shift circuit shown in FIG. 5 is used, MOS corresponds to the resistor R2 in FIG.
MOSFETs (P2, P3) that drive the FET (P1)
ON resistance of the MOSFET (P2,
It is necessary to reduce the on resistance of P3). However, since the MOSFETs (P2, P3) are p-type devices, the device size increases in order to have a lower on-resistance than the n-type devices due to the difference in carrier mobility.

If the on-resistance of the MOSFETs (P2, P3) is lowered, the current flowing through the two series circuits becomes large, and the power consumption of the level shift circuit (42) also becomes large. The above (2) is unavoidable in the totem pole circuit in which the reference potential of the upper arm device is Vout, and is particularly likely to occur when the lower arm device changes from off to on.

A number of circuits for preventing arm short circuits have been proposed so far, and FIG.
As described in Japanese Patent Publication No. 00-307406, M
N-channel type MOSFE in front of OSFET (N1)
A buffer circuit 50 as a delay circuit is inserted with T (N6). The common control signal (S1) is input to the MOSFETs (N1, N6), but the MOSFET (N1) is turned on by the buffer circuit 50 by the MOSF.
It is later than the turning on of ET (N6). That is, MOSFE
When T (N6) is turned on first, the MOSFET (N
The gate voltage of 2) approaches Vss, and the MOSFET (N
The effect when 1) is turned on is avoided.

Therefore, by optimizing the delay time of the buffer circuit 50 and the current driving capability of the MOSFET (N6), arm short circuit due to malfunction of the MOSFET (N2) can be avoided. However, in the circuit shown in FIG. 6, the MOSFETs (N1, N2) forming the totem pole circuit
Besides, since the MOSFET (N6) and the buffer circuit 50 are required, the number of parts increases. In addition, MOSFET
Since the power supply voltage is applied to (N6) through the MOSFET (P1), when a high voltage is applied to the power supply voltage, the MOSFET (N6) must also be configured with a high breakdown voltage device, and current drive is required. You must also have the ability. When the load drive circuit is configured as a monolithic IC, the increase in chip size due to the addition of the MOSFET (N6) cannot be ignored and causes a cost increase.

FIG. 7 shows the MOSFET (N1,
This circuit also serves as N6). Even if the MOSFET (P1) malfunctions due to a sudden change in the potential of the output (Vout), the MOSFET (N1) is already in the on state at that time, and a negative voltage is generated between the gate and source of the MOSFET (N2). MOSFET (N2)
Is completely turned off and no arm short circuit occurs.

However, in the circuit shown in FIG. 7, since the diode ZD exists between the output (Vout) and the MOSFET (N1), the diode ZD also has a MOSF.
A current driving capability equivalent to that of ET (N1) is required. In order to increase the current drive capacity of the diode ZD, the device size is increased and the junction capacitance is increased. Since the diode ZD is also connected to the gate of the MOSFET (N2), the MOSFET seen from the MOSFET (P1)
There is a problem that the input capacitance of (N2) increases and the rise time of the MOSFET (N2) is delayed. That is,
Since the characteristics of the totem pole circuit are influenced by the characteristics of the diode ZD, it is not suitable for a load drive circuit that drives a large current load.

As described above, in the conventional load drive circuit, there is a problem that an arm short circuit in which the devices of the upper and lower arms of the totem pole circuit are simultaneously turned on easily occurs, and the circuit is also used in the circuit for preventing the arm short circuit. There has been a problem that the parts and circuit size increase, and eventually the cost of the IC chip increases. SUMMARY OF THE INVENTION An object of the present invention is to provide a load drive circuit capable of reliably preventing arm short circuit without increasing the number of parts and the circuit size in view of the above problems.

[0029]

In order to achieve the above object, two n-channel type insulated gate devices are connected in series, the gate of the n-channel type insulated gate device on the upper arm side and a high-potential side main terminal. And a first p-channel insulated gate device for driving the n-channel insulated gate device, and a load connected to the connection point of the series connection is connected to the two n-channel insulated gate devices. In a load driving circuit that is alternately turned on and off to drive, a main terminal of a second p-channel insulated gate device is connected between the gate of the n-channel insulated gate device on the upper arm side and the connection point. Connecting the gate to the gate of the high-potential side n-channel insulated gate device through the gate resistance of the second p-channel insulated gate device. That.

The second p-channel insulated gate device may be turned on when the potential of the connection point changes from a high potential to a low potential by turning on the n-channel insulated gate device on the lower arm side. In the case where the load drive circuit, the level shift circuit, the control circuit, etc. are integrated on one chip as a monolithic IC, the second
The p-channel type insulated gate device may be formed in the vicinity of the gate terminal of the upper arm side high breakdown voltage insulated gate device or in the vicinity of the corner portion of the high breakdown voltage insulated gate device.

At this time, the second p-channel type insulated gate device may be formed in a high breakdown voltage device forming region in which the high breakdown voltage insulated gate device is formed.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a first embodiment. The same components as those in FIG. 4 are designated by the same reference numerals and detailed description thereof will be omitted. In FIG. 1, 2
Reference numeral 0 is a drive circuit for driving the MOSFET (N2) connected to the upper arm side. Driving circuit 2 shown in FIG.
1, a low breakdown voltage p-channel MO for preventing malfunctions
The SFET (P4) and its gate resistance (R3) are connected. Source of MOSFET (P4) is MOSFET
It is connected to the gate of (N2) and its drain is the output (Vou
t). The gate of the MOSFET (P4) is the source of the MOSFET (P4), that is, the MOS, via the gate resistance (R3) of the MOSFET (P4).
It is connected to the gate of the FET (N2). MOSFE
T (P4) is preferably connected near the gate terminal of MOSFET (N2).

The on-resistance of the MOSFET (P1) is set high (for example, several kΩ) in order to suppress power consumption, whereas the MOSFETs (N1, N2) have a high current drive capability and their on-resistance. Is low. In addition, MOSFE
T (P4) is a low withstand voltage element, and is set to an on-resistance value (for example, several 100Ω) sufficiently lower than the resistance R1 (for example, several kΩ) connected in parallel.

Reference numeral 40 denotes a level shift circuit, which may adopt the structure of the level shift circuit 41 shown in FIG.
The configuration shown in FIG. 5 may be used. MO the connection point (B) in FIG.
Connected to the gate of SFET (N2), MOSFET (P
When 1) is omitted, the p-channel type insulated gate device of the drive circuit also serves as the p-channel type insulated gate device of the level shift circuit. Therefore, the MOSFET (P4) for malfunction prevention is the level shift circuit-MOSFE.
It may be connected between T (N2).

Next, the operation will be described. Control circuit 30
When the control signal (S2) output from outputs H level,
The voltage level of the signal is converted by the level shift circuit 40 and the MOSFET (P1) is turned on. MOSFET
When (P1) is turned on, the current IP1 flows and the resistance R1
Generates a voltage, which is applied to the gate of the MOSFET (N2) to turn on the MOSFET (N2).

When the MOSFET (P1) is turned on and the current IP1 flows, the MOSFET (P4) passes through the drain-gate capacitance and load of the MOSFET (P4).
A current also flows through the gate resistance R3 of (P4). The voltage drop generated here momentarily turns on the MOSFET (P4), and VH → MOSFET (P1) → MOSFET
A current route of (P4) → Vout is formed,
At this time, the MOSFET (N1) is off, and M
Since the ON resistance of the OSFET (P1) is high, almost no current flows through this route. In addition, this current route is a transient one, and is almost the same at the same time.
T (N2) turns on, and VH → MOSFET (N2)
→ Vout current route is established.

On the contrary, when the control signal (S1) becomes H level after a predetermined period has elapsed since the control signal (S2) becomes L level, the MOSFET (N1) is turned on. At this time Vout
Since the potential of the terminal rapidly changes from VH to Vss, as described above, a current flows through the drain-gate capacitance of the MOSFET (P1), so that the MOSFET (P
1) is turned on and a current IP1 is generated.

This current IP1 flows through the resistor R3, which is the gate resistance of the MOSFET (P4), and the drain-gate capacitance of the MOSFET (P4), causing a voltage drop and turning on the MOSFET (P4). Is VH → MOSFET (P1) → MOSFET (P
4) → Flows through the route of MOSFET (N1). Vou
The current flowing due to the abrupt change of the potential of t is MOSFE
It depends on the drain-gate capacitance of T (P1), and this current is M which has an ON resistance lower than the resistance R1.
MOSF by flowing into OSFET (P4)
No voltage is generated at the gate of ET (N2)
(N2) does not accidentally turn on and an arm short circuit does not occur.

At this time, VH → MOSFET (P1)
The route of → MOSFET (P4) → MOSFET (N1) is to short-circuit between VH and Vss, but since the on-resistance of MOSFET (P1) is large as described above,
No current flows as in the case of an arm short circuit in which the MOSFETs (N1, N2) are turned on at the same time, and problems such as increase in power consumption and element destruction do not occur.

FIG. 2 is a diagram showing a second embodiment, in which an anti-parallel circuit of an IGBT (N20) and a diode (D2) and an anti-parallel circuit of an IGBT (N10) and a diode (D1) are provided. Connect them in series as shown in the figure, and
Vss) to form a totem pole circuit 11. The diodes (D1, D2) are IGBTs.
It is a reverse conducting diode of (N10, N20). The connection point of the series circuit is the output (Vout).

The source of the MOSFET (P4) is an IGBT
MOSFET (P4) connected to the gate of (N20)
Is connected to the source of the MOSFET (P4) via the gate resistance of the MOSFET (P4), and the
The drain of ET (P4) is connected to the output (Vout). Next, the operation will be described. When the control signal (S2) output from the control circuit 30 becomes H level, the signal level is converted by the level shift circuit 40 and the MOS
The FET (P1) is turned on. When the MOSFET (P1) is turned on, a current IP1 flows, a voltage is generated by the resistor R1, and this is applied to the gate of the IGBT (N20) to turn on the IGBT (N20).

By the way, when the MOSFET (P1) is turned on and the current IP1 flows, the MOSFET (P4) passes through the drain-gate capacitance and load of the MOSFET (P4).
A current also flows through the gate resistance R3 of (P4). The voltage drop generated here momentarily turns on the MOSFET (P4), and VH → MOSFET (P1) → MOSFET
A current route of (P4) → Vout is formed,
At this time, the IGBT (N10) is off, and the MO
Due to the high on-resistance of the SFET (P1), almost no current flows through this route. Further, this current route is a transient one, and is almost the same as the IGBT (N
20) is turned on, and VH → IGBT (N20) → Vo
A current route ut is established.

On the contrary, when the control signal (S2) becomes L level and the control signal (S1) becomes H level after a lapse of a predetermined period, the IGBT (N10) is turned on. At this time, the potential of the Vout terminal changes abruptly from VH to Vss. Therefore, as described above, a current flows through the drain-gate capacitance of the MOSFET (P1), so that the MOSFET (P
1) is turned on and a current IP1 is generated.

This current IP1 flows through the resistor R3, which is the gate resistance of the MOSFET (P4), and the drain-gate capacitance of the MOSFET (P4), causing a voltage drop and turning on the MOSFET (P4). Is VH → MOSFET (P1) → MOSFET (P
4) Flows along the route of → IGBT (N10). Vout
The current that flows due to a sudden change in the potential of the MOSFET
It depends on the drain-gate capacitance of (P1), and this current is an MO having an ON resistance lower than the resistance R1.
By flowing into SFET (P4)
No voltage is generated at the gate of T (N2) and the IGBT (N2)
0) is not accidentally turned on and an arm short circuit does not occur.

At this time, VH → MOSFET (P1)
The route of → MOSFET (P4) → IGBT (N10) is to short-circuit between VH and Vss, but since the on-resistance of MOSFET (P1) is large as described above, I
No current flows as in the case of arm short circuit in which the GBTs (N10, N20) are turned on at the same time, and problems such as increase in power consumption and element destruction do not occur.

Next, a load drive circuit, a level shift circuit,
A case where a control circuit and the like are integrated on one chip as a monolithic IC will be described. FIG. 3 is a conceptual diagram of a monolithic IC according to the third embodiment. In FIG. 3A, 100 is an IC chip, 200 is a low breakdown voltage device formation region in which a control circuit and the like are formed, and 300 is a high breakdown voltage device formation region in which a high breakdown voltage device is formed. The low breakdown voltage device formation region 200 and the high breakdown voltage device formation region 300 are isolated from each other.

The high breakdown voltage device 310 is formed in the high breakdown voltage device formation region 300.
In the case of having a plurality of output stages such as the above, the high breakdown voltage device formation region 300 is further divided into a plurality of element formation regions, and one or a plurality of high breakdown voltage devices 310 are formed in the element formation region. In FIG. 3A, 311 to 313 are element formation regions formed in the high breakdown voltage device formation region 300. For example, when the circuits shown in FIGS. 1 and 2 are integrated on one chip, devices forming a totem pole circuit are provided in the element forming regions 311, 313, and a driving circuit and a level shift circuit are provided in the element forming region 312. It may be formed.

A known isolation method can be applied to the isolation of the low breakdown voltage device formation region and the high breakdown voltage device formation region, or the isolation method of the high breakdown voltage devices in the high breakdown voltage device formation region. A method of forming a groove reaching the oxide film and separating the element region on the SOI substrate in which the two semiconductor substrates are bonded together via the element substrate is advantageous in suppressing the element area.

In FIG. 3A, p for preventing malfunction of the n-channel type insulated gate device which constitutes the upper arm.
The channel-type insulated gate device 320 is a low breakdown voltage device. MOSFET described in the first and second embodiments
(P4) corresponds to this, and its gate resistance (R3) is formed, for example, as a polysilicon resistance 330. As described above, the malfunction of the element forming the upper arm is a phenomenon that occurs transiently with the abrupt voltage change of the output (Vout), and the drain-gate capacitance of the insulated gate element acts. . p-channel insulated gate device 32
The 0 (MOSFET (P4)) and the polysilicon resistor 330 (resistor (R3)) are connected to the gate of the n-channel insulated gate device of the upper arm to prevent malfunction, so that the n-channel insulated gate device of the upper arm is connected. The gate is formed near the terminal and connected.

Although the p-channel insulated gate device (MOSFET (P4)) is a low breakdown voltage device,
It is formed in the high breakdown voltage device formation region. In FIG. 3 (a),
Although the elements formed in each region, the terminals thereof, the terminals, and the wiring between the elements are omitted, the p-channel insulated gate device 320 for preventing malfunction and the polysilicon resistor 330 are driven in the high breakdown voltage device formation region 300. It is arranged between the element formation region 312 where the circuit is formed and the element formation region 313 where the n-channel insulated gate device of the upper arm is formed,
The malfunction preventing p-channel insulated gate device 320 and the polysilicon resistor 330 are connected to the upper arm in the vicinity of the gate terminal of the n-channel insulated gate device.

When the n-channel insulated gate device of the upper arm is formed in the element formation region 311, a p-channel insulated gate device 320 and a polysilicon resistor 330 are formed.
May be formed not only between the element formation region 311 and the element formation region 312 in which the drive circuit is formed, but also in a region A surrounded by a dotted line in FIG. If the p-channel insulated gate device 320 for preventing malfunction and the polysilicon resistor 330 cannot be formed in the high breakdown voltage device formation region 300,
Low breakdown voltage device formation area 200 and high breakdown voltage device formation area 3
You may form in the area between 00 and.

Further, as in the area B surrounded by the dotted line in FIG. 3B, it may be arranged outside the element formation areas 311, 313 or in the vicinity of the gate wiring 340. Since the malfunction prevention p-channel insulated gate device 320 is a low breakdown voltage device, if it is simultaneously formed by another low breakdown voltage device forming process such as a control circuit formed in the low breakdown voltage device forming region, a manufacturing process should be added. Instead, it can be formed in the high breakdown voltage device formation region.

Further, as shown in FIG. 3B, a malfunction preventing p-channel type insulated gate device 320 and a polysilicon resistor 330 are formed in the same element forming region as the upper arm n-channel type insulated gate device. Good. At this time, if a region (well) for forming the p-channel type insulated gate device is required, if the well is formed at the same time when the n-type region used for the n-channel type insulated gate device is formed, no additional process is required. It is unnecessary.

As shown in FIG. 3B, when the high breakdown voltage n-channel insulated gate device has a shape with rounded corners or a shape with the corners dropped, or In the case of having a curved portion, a device is formed in the high breakdown voltage device formation region 300 in the corner portion or curved portion of the high breakdown voltage n-channel insulated gate device, particularly in a region where the high breakdown voltage n-channel insulated gate device is adjacent. A region (C to E surrounded by a dotted line) which is not covered occurs.

It is advisable to form a low breakdown voltage p-channel insulated gate device 320 and a polysilicon resistor 330 for preventing malfunction in this region. That is, if it is formed in such a region, it will be formed in the vicinity of the high breakdown voltage n-channel type insulated gate device, and it should be formed and connected in a place near the gate terminal of the high breakdown voltage n-channel type insulated gate device. You can

The element area of the low breakdown voltage p-channel insulated gate device is extremely smaller than that of the high breakdown voltage n-channel insulated gate device, and can be formed, for example, in an area of about 1/100. The locations where the low breakdown voltage p-channel insulated gate device 320 and the polysilicon resistor 330 for preventing malfunction are formed are not limited to the above examples, and they can be formed in the empty space between the high breakdown voltage n-channel insulated gate devices. Therefore, there is no increase in the element formation region due to the formation of the low breakdown voltage p-channel insulated gate device for preventing malfunction.

Since the polysilicon resistor 330 has a smaller device area than the low breakdown voltage p-channel insulated gate device 320 and has a high degree of freedom in device layout, the low breakdown voltage p-channel insulated gate device 320 for malfunction prevention is provided.
Can be formed in the vicinity of the gate. Further, not only a polysilicon resistor but also a diffused resistor can be used.

Up to now, the structure in which the same type of insulated gate devices are connected in series to form the totem pole circuit has been described, but in the present invention, the element forming the upper arm and the element forming the lower arm are different. It is also applicable to totem pole circuits. For example, IGB on the upper arm
Anti-parallel circuit of T and diode, MOSF on the lower arm
Totem pole circuit using ET, IG on upper arm
Parallel circuit of BT and MOSFET, MOS on the lower arm
Totem pole circuit using FET, conversely, MOSFET on upper arm, anti-parallel circuit of IGBT and diode on lower arm, MOSFET on upper arm, totem pole using parallel circuit of IGBT and MOSFET on lower arm The present invention can be applied to a totem pole circuit by various combinations such as circuits by connecting a P-channel type insulated gate device between the gate of the device forming the upper arm and the output (Vout). You can

[0059]

As described above, the p-channel insulated gate for preventing malfunction is provided between the gate of the n-channel insulated gate device forming the upper arm of the totem pole circuit and the output terminal of the totem pole circuit. The main terminal of the device is connected, and the gate terminal of the p-channel type insulated gate device is connected to the gate of the n-channel type insulated gate device on the upper arm side through the gate resistance of the p-channel type insulated gate device. With this configuration, the circuit of the upper arm of the totem pole circuit is simultaneously turned on due to a malfunction caused by a sudden voltage change of the output terminal of the totem pole circuit caused by the device of the lower arm being turned on. You can surely prevent without doing.

Further, the p-channel type insulated gate device for preventing the malfunction is arranged and connected in the vicinity of the gate terminal of the n-channel type insulated gate device which constitutes the upper arm, so that the influence of noise due to the routing of the wiring and the wiring are prevented. It is possible to eliminate the influence of the above parasitic capacitance and parasitic inductance and reliably prevent malfunction. Also,
By forming the p-channel type insulated gate device for preventing malfunction in the high breakdown voltage device formation region, the p-type insulated gate device is formed.
A low withstand voltage device reduces the influence of noise and the like due to the influence of the voltage fluctuation of the output terminal connected between the gate terminal and the output terminal Vout of the n-channel insulated gate device that constitutes the upper arm of the channel type insulated gate device. Other low breakdown voltage devices (control circuits) formed in the formation area
Can be avoided from.

If the p-channel insulated gate device for malfunction prevention is formed in an empty region such as a corner of a high breakdown voltage device, the device area is not increased, and the p-channel insulation gate device for malfunction prevention is provided. If the insulated gate device is formed at the same time as the process of forming another low breakdown voltage device, the manufacturing process will not be increased. Therefore, the above-mentioned arm short circuit can be made inexpensively and reliably without increasing the circuit size and the cost of the chip. Can be prevented.

For a semiconductor device having a plurality of sets of totem pole circuits for multi-bit output, the p-channel type insulated gate device for preventing malfunction can be formed without increasing the chip size. Is effective as a configuration of.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment.

FIG. 2 is a diagram showing a second embodiment.

FIG. 3 is a diagram showing a third embodiment.

FIG. 4 is a diagram showing a conventional example of a totem pole circuit and its peripheral circuits.

FIG. 5 is a diagram showing another level shift circuit.

FIG. 6 is a diagram showing another conventional example of a totem pole circuit and its peripheral circuits.

FIG. 7 is a diagram showing another conventional example of a totem pole circuit and its peripheral circuits.

[Explanation of symbols]

10,11 Totem pole circuit 20,21 Drive circuit 30 control circuit 40, 41, 42 level shift circuit 100 IC chip 200 Low voltage device formation area 300 High voltage device formation area 310 High voltage device 311, 312, 313 Element formation area 320 p-channel insulated gate device for malfunction prevention 330 Polysilicon resistor 340 gate wiring

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5H007 AA06 AA17 BB06 CA01 CA02                       CB04 CB05 DB03 EA02 FA06                       FA09 FA13                 5J055 AX34 BX16 CX19 CX20 CX29                       DX09 DX22 DX56 DX72 EX07                       EX21 EY01 EY12 EY13 EY21                       EZ07 EZ20 GX01 GX02 GX08

Claims (7)

[Claims] 1. Two n-channel insulated gate devices are connected in series, and the n-channel insulated gate device is driven between the gate of the n-channel insulated gate device on the upper arm side and a high-potential side main terminal. A load drive circuit for driving a load connected to the connection point of the series connection by alternately turning on and off the two n-channel type insulated gate devices. , A main terminal of the second p-channel type insulated gate device is connected between the gate of the n-channel type insulated gate device on the upper arm side and the connection point, and a gate resistance of the second p-channel type insulated gate device is connected. A load driving circuit, wherein the gate is connected to the gate of the n-channel insulated gate device on the high potential side via the gate. 2. The load drive circuit according to claim 1, wherein in the second p-channel type insulated gate device, the potential of the connection point is changed from a high potential to a low potential by turning on the n-channel type insulated gate device on the lower arm side. A load drive circuit, which is turned on when the potential changes. 3. Two high breakdown voltage n-channel insulated gate devices are connected in series, and the high breakdown voltage n channel is provided between the gate of the high breakdown voltage n channel insulated gate device on the upper arm side and the high potential side main terminal. A high breakdown voltage p-channel insulated gate device for driving the insulated gate device
A semiconductor device having a load drive circuit for driving a load connected to the connection point of the series connection by alternately turning on and off the two high breakdown voltage n-channel type insulated gate devices, wherein a second p-channel type insulated gate device is provided. A device is formed, and a main terminal of the second p-channel type insulated gate device is connected between the gate of the high withstand voltage n-channel type insulated gate device on the upper arm side and the connection point, and the second p-channel type insulated gate device is connected. A semiconductor device having a load drive circuit, wherein the gate is connected to the gate of the high breakdown voltage n-channel type insulated gate device on the high potential side through a gate resistance of the gate device. 4. The semiconductor device having the load drive circuit according to claim 3, wherein the second p-channel type insulated gate device has a potential at the connection point which is set by turning on the n-channel type insulated gate device on the lower arm side. A semiconductor device having a load drive circuit, which is turned on when changing from a high potential to a low potential. 5. A semiconductor device having the load drive circuit according to claim 3 or 4, wherein the second p-channel type insulated gate device is formed near a gate terminal of the upper arm side high breakdown voltage insulated gate device. A semiconductor device having a load drive circuit characterized by the above. 6. A semiconductor device having the load drive circuit according to claim 3 or 4, wherein the second p-channel type insulated gate device is formed near a corner portion of the high breakdown voltage insulated gate device. Characteristic semiconductor device. 7. A semiconductor device having the load drive circuit according to claim 3, wherein the second p-channel type insulated gate device is a low withstand voltage device, and the high withstand voltage insulated gate device is formed in the high withstand voltage device. A semiconductor device having a load drive circuit, which is formed in a formation region.