JP2014158192A - Drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drive circuit that more reliably prevents a malfunction caused by a false signal output from a level shift circuit owing to a dv/dt displacement current.SOLUTION: A level shift circuit 110 of a P side drive circuit 100 has a series connection of a resistive element 112 and a high voltage MOS transistor 111 controlled by an input signal DC, and outputs a signal corresponding to a voltage drop of the resistive element 112 as a level shift signal LS. A dv/dt detection circuit 140 has a series connection of a resistive element 142 and a high voltage MOS transistor 141 fixedly kept off in a steady state, and outputs a signal corresponding to a voltage drop of the resistive element 142 as a mask signal MS. A P side switching device 10 is provided with a mask circuit 120 for masking the level shift signal LS in response to the mask signal MS.

Description

  The present invention relates to a drive circuit for driving a power semiconductor device (power device), and more particularly to a drive circuit including a level shift circuit for converting the level of an input signal.

  An inverter as a power device has a high-potential side (P-side) switching device connected to a totem pole between a high potential of about 600 to 1200 V (hereinafter “VP potential”) and a ground potential (hereinafter “GND potential”) and a low potential. It is composed of a potential side (N side) switching device. Therefore, the inverter drive circuit includes a P-side drive circuit that drives the P-side switching device and an N-side drive circuit that drives the N-side switching device.

  The N-side switching device operates using the GND potential as the reference potential, but the P-side switching device operates using the potential at the connection point with the N-side switching device (hereinafter referred to as “VS potential”) as a reference potential. Is provided with a level shift circuit for converting an input signal into a signal having the VS potential as a reference potential.

  The operating power supply of the P-side drive circuit is a floating power supply that floats with respect to the GND potential because the VS potential is the reference potential. That is, the operating power supply potential (hereinafter referred to as “VB potential”) of the P-side drive circuit floats between the GND potential and the VP potential as the P-side and N-side switching devices are turned on (conductive) and turned off (non-conductive). Will do.

  The fluctuation of the VB potential causes a current (dv / dt displacement current) to flow through the parasitic capacitor of the MOS transistor constituting the level shift circuit, and causes an error signal to be output from the level shift circuit. For example, Patent Document 1 below proposes a technique for preventing a malfunction of a P-side drive circuit caused by the error signal.

Japanese Patent Laid-Open No. 9-200017

  In Patent Document 1, in order to reduce power consumption, a DC input signal is divided into a pulse signal (ON signal) for turning on a P-side switching device and a pulse signal (OFF signal) for turning off a P-side switching device. The side drive circuit includes two level shift circuits that convert the on signal and the off signal into signals having the VS potential as a reference potential. The on signal and the off signal that have been level-converted by the two level shift circuits are decoded into one DC signal that drives the P-side switching device by the RS flip-flop circuit.

  In Patent Document 1, a malfunction prevention circuit that considers a signal output from two level shift circuits at the same time as an error signal and shuts it off under the assumption that a dv / dt displacement current causes an error signal simultaneously in the two level shift circuits. (Logic filter) is provided in the P-side drive circuit.

  However, the malfunction prevention circuit of Patent Document 1 cannot completely shut off an error signal when an ON signal error signal and an OFF signal error signal occur at different timings due to manufacturing variations.

  The present invention has been made to solve the above-described problems, and provides a drive circuit that can more reliably prevent a malfunction due to a false signal output from a level shift circuit due to a dv / dt displacement current. For the purpose.

  The drive circuit according to the present invention includes a level shift circuit that converts an input signal, which is a direct current signal, into a level shift signal that is level-shifted to a signal based on a predetermined potential, and a dv / dt displacement caused by the variation of the predetermined potential. A dv / dt detection circuit that detects the generation of current and outputs a detection signal indicating the generation of the dv / dt displacement current, and transmits the level shift signal to the output circuit of the drive signal, and according to the detection signal A mask circuit for masking the level shift signal, the level shift circuit having a first load element connected in series and a first switching element controlled by the input signal, and a voltage drop of the first load element Is output as the level shift signal, and the dv / dt detection circuit is fixed off in a steady state with the second load element connected in series. A second switching element, and outputs a signal corresponding to the voltage drop of the second load element as the detection signal.

  According to the present invention, since the level shift signal LS is masked according to the detection signal of the dv / dt displacement current, the error signal of the level shift signal LS caused by the dv / dt displacement current is transmitted to the output circuit. And malfunction of the drive circuit can be prevented. In addition, since a DC signal is used as an input signal, it is not necessary to consider the generation timing of an ON signal error signal and an OFF signal error signal.

1 is a diagram illustrating a configuration of a drive circuit according to a first embodiment. It is a circuit diagram of D latch circuit (mask circuit). FIG. 6 is a diagram for explaining the operation of the D latch circuit (mask circuit) in the first embodiment. FIG. 4 is a diagram illustrating a configuration of a drive circuit according to a second embodiment. FIG. 10 is a diagram for explaining an operation of a D latch circuit (mask circuit) in the second embodiment. It is a figure which shows the structural example of a delay circuit. It is a figure for demonstrating the principle of operation of a delay circuit. It is a figure which shows the example of operation | movement of a delay circuit. It is a figure which shows the example of operation | movement of a delay circuit. FIG. 6 is a diagram illustrating a configuration of a drive circuit according to a third embodiment. FIG. 6 is a diagram illustrating a configuration of a drive circuit according to a fourth embodiment.

<Embodiment 1>
FIG. 1 is a diagram illustrating a configuration of a drive circuit according to the first embodiment. The driving circuit drives a half-bridge type power device (inverter) composed of P-side and N-side switching devices 10 and 20 that are totem-pole connected between a VP potential and a GND potential.

  The P-side switching device 10 operates using the potential (VS potential) at the connection point with the N-side switching device 20 as a reference potential. On the other hand, the N-side switching device 20 operates using the GND potential as a reference potential. The drive circuit according to the first embodiment includes a P-side drive circuit 100 that drives the P-side switching device 10 and an N-side drive circuit 200 that drives the N-side switching device 20. Is not related to the invention of the present application and will not be described.

  The P-side drive circuit 100 includes a level shift circuit 110, a mask circuit 120, an output circuit 130, and a dv / dt detection circuit 140. The P-side drive circuit 100 is supplied with an operating power supply potential (VB potential) from a power supply 150 (P-side power supply) with reference to the VS potential.

  In the present embodiment, the input signal DC for controlling the P-side switching device 10 is a DC signal based on the GND potential. The level shift circuit 110 converts the input signal DC into a level shift signal LS having the VS potential as a reference potential.

  The level shift circuit 110 includes a high breakdown voltage field effect transistor (high voltage MOS transistor) 111 that is a switching element having a gate to which an input signal DC is supplied, and a load element connected between the drain of the high voltage MOS transistor 111 and the VB potential. And an inverter 114 that receives a signal appearing at the drain of the high-voltage MOS transistor 111 and outputs a level shift signal LS. The source of the high voltage MOS transistor 111 is connected to the GND potential (that is, the resistance element 112 and the high voltage MOS transistor 111 are connected in series between the VB potential and the GND potential). Further, the level shift circuit 110 is provided with a diode 113 whose anode is connected to the VS potential and whose cathode is connected to the drain of the high-voltage MOS transistor 111. The diode 113 is for clamping the VS potential.

  The dv / dt detection circuit 140 detects the occurrence of a dv / dt displacement current caused by a change in the VB potential, and outputs a detection signal when the dv / dt displacement current is detected. Hereinafter, this detection signal is referred to as a “mask signal MS”.

  Similarly to the level shift circuit 110, the dv / dt detection circuit 140 includes a high voltage MOS transistor 141 and a resistance element 142 as a load element connected between the drain of the high voltage MOS transistor 141 and the VB potential. However, the gate of the high voltage MOS transistor 141 is connected to the GND potential together with the source, and is configured to be fixed off in a steady state (that is, the resistance element 142 and the high voltage MOS transistor 141 have the VB potential and the GND potential. Are connected in series). Furthermore, the dv / dt detection circuit 140 includes an inverter 144 that receives a signal appearing at the drain of the high-voltage MOS transistor 141 and an inverter 145 that receives the output of the inverter 144. The output of the inverter 145 becomes the mask signal MS. The dv / dt detection circuit 140 is provided with a diode 143 having an anode connected to the VS potential and a cathode connected to the high voltage MOS transistor 141.

  The mask circuit 120 is constituted by a D latch circuit 121. When the strobe terminal (STB terminal) is at the H (High) level, the D latch circuit 121 transmits the level of the input terminal (D terminal) to the output terminal (Q terminal), and the STB terminal is at the L (Low) level. When the signal is transmitted from the D terminal to the Q terminal, the operation is performed so as to maintain the previous output level.

  FIG. 2 is an example of a circuit diagram of the D latch circuit 121. The D latch circuit 121 can be composed of switch elements SW1 and SW2 and inverters IV1 to IV4. When the STB terminal is at the H level, the output (point a) of the inverter IV1 is at the L level and the output (point b) of the inverter IV2 is at the H level, so that the switch element SW1 is turned on and the switch element SW2 is turned off. In this state, the switch element SW1 transmits the signal at the D terminal to the Q terminal through the inverters IV3 and IV4.

  When the STB terminal is at L level, the output (point a) of the inverter IV1 is at H level and the output of the inverter IV2 (point b) is at L level, so that the switch element SW1 is off and the switch element SW2 is on. Become. In this state, the switch element SW1 cuts off the signal at the D terminal, and the switch element SW2 and the inverters IV3 and IV4 hold the output (point c) of the switch element SW1 and the level of the Q terminal so far.

  As shown in FIG. 1, the level shift signal LS output from the level shift circuit 110 is input to the D terminal of the D latch circuit 121. The mask signal MS output from the dv / dt detection circuit 140 is input to the STB terminal of the D latch circuit 121.

  An output signal (Q terminal signal) of the D latch circuit 121 is input to the output circuit 130. The output circuit 130 is a buffer circuit that increases the drive capability of the output signal of the D latch circuit 121 and outputs the drive signal of the P-side switching device 10.

  The operation of the P-side drive circuit 100 will be described. Here, a steady state in which no dv / dt displacement current is generated is assumed. In the steady state, since the high voltage MOS transistor 141 of the dv / dt detection circuit 140 is off, the input of the inverter 144 is at the H level. Therefore, the input of inverter 145 is at L level, and mask signal MS output from inverter 145 is at H level. Therefore, the STB terminal of the D latch circuit 121 is at the H level.

  When the P-side switching device 10 is turned on, the input signal DC is set to H level. Then, in the level shift circuit 110, the high voltage MOS transistor 111 is turned on, a voltage drop occurs in the resistance element 112, and the input of the inverter 114 becomes L level. Therefore, the level shift signal LS input to the D terminal of the D latch circuit 121 becomes H level. Since the STB terminal of the D latch circuit 121 is at the H level, when the D terminal of the D latch circuit 121 is at the H level, the Q terminal also changes to the H level. As a result, an H level signal is input to the output circuit 130, and the output circuit 130 turns on the P-side switching device 10.

  When the P-side switching device 10 is turned off, the input signal DC is set to L level. Then, in the level shift circuit 110, the high voltage MOS transistor 111 is turned off, no voltage drop occurs in the resistance element 112, and the input of the inverter 114 becomes H level. Therefore, the level shift input to the D terminal of the D latch circuit 121 The signal LS becomes L level. Since the STB terminal of the D latch circuit 121 is at the H level, when the D terminal of the D latch circuit 121 becomes the L level, the Q terminal also changes to the L level. As a result, an L level signal is input to the output circuit 130, and the output circuit 130 turns off the P-side switching device 10.

  Next, the operation of the level shift circuit 110 in a transient state in which a dv / dt displacement current flows through the parasitic capacitor of the high voltage MOS transistor 111 of the level shift circuit 110 will be described. FIG. 3 is a timing chart showing the operation. Here, in the steady state where the P-side switching device 10 is off, the VS potential varies and the VB potential varies accordingly.

  When the VB potential fluctuates and a dv / dt displacement current flows through the parasitic capacitor of the high voltage MOS transistor 111 of the level shift circuit 110, a voltage drop occurs in the resistance element 112. Therefore, the level shift signal LS is output from the P-side drive circuit 100. Is output to the D terminal of the D latch circuit 121.

  On the other hand, at the same timing when the dv / dt displacement current flows to the high voltage MOS transistor 111, the dv / dt displacement current also flows to the parasitic capacitor of the high voltage MOS transistor 141 of the dv / dt detection circuit 140. As a result, a voltage drop occurs in the resistance element 142, and the input of the inverter 144 becomes L level and the input of the inverter 145 becomes H level. As a result, the mask signal MS output from the dv / dt detection circuit 140 becomes L level. When the mask signal MS becomes L level, the STB terminal of the D latch circuit 121 becomes L level as shown in FIG.

  When the STB terminal becomes L level, the switch element SW1 of the D latch circuit 121 (FIG. 2) is turned off (non-conducting), so that an error signal of the level shift signal LS input to the D terminal is not transmitted to the Q terminal. . Further, since the switch element SW2 is turned on (conductive), the level of the Q terminal is maintained in the state before the generation of the error signal (L level).

  Thereafter, when the fluctuation of the VB potential is reduced, the dv / dt displacement current of the high voltage MOS transistor 111 of the level shift circuit 110 does not flow. In response, the level shift signal LS returns to the L level, and the erroneous signal input to the D terminal of the D latch circuit 121 disappears. At this time, since the dv / dt displacement current does not flow through the high voltage MOS transistor 141 of the dv / dt detection circuit 140, the mask signal MS becomes H level, and the STB terminal of the D latch circuit 121 returns to H level. As a result, the D latch circuit 121 transmits the signal at the D terminal to the Q terminal, and the P-side drive circuit 100 returns to a state in which a normal operation can be performed.

  In this way, the D latch circuit 121 masks the level shift signal LS output from the level shift circuit 110 in response to the mask signal MS becoming L level while the dv / dt displacement current is generated. To work. Thereby, even if an error signal is generated in the level shift signal LS due to the dv / dt displacement current, it is prevented from being transmitted to the output circuit 130, and the malfunction of the P-side drive circuit 100 is prevented. .

  In this embodiment, since the input signal DC input to the level shift circuit 110 is a single-system DC signal, the generation timing of the erroneous signal of the on signal and the erroneous signal of the off signal as in Patent Document 1. There is no need to consider.

[First Modification]
When the difference between the VB potential and the VS potential is reduced, the current flowing through the high-voltage MOS transistor 111 is reduced in the level shift circuit 110, so that the amplitude of the signal input to the inverter 114 is reduced. In that case, the inverter 114 may chatter and the operation of the P-side drive circuit 100 may become unstable.

  In order to solve this problem, the inverter 114 may be replaced with a Schmitt trigger circuit. Since the threshold voltage of the Schmitt trigger circuit has hysteresis characteristics, chattering can be prevented, thereby preventing the operation of the P-side drive circuit 100 from becoming unstable.

  After the input of the Schmitt trigger circuit is set to the L level and the output thereof is set to the H level, the threshold voltage of the Schmitt trigger circuit rises due to the hysteresis characteristics described above. Therefore, the Schmitt trigger circuit can maintain the output at the H level using the input signal DC having a small amplitude. Therefore, the current flowing through the high voltage MOS transistor 111 can be intentionally reduced to reduce power consumption.

[Second Modification]
In the dv / dt detection circuit 140, the resistance element 142 may be replaced with a Zener diode. In this case, when the dv / dt displacement current is generated, the speed at which the drain level of the high-voltage MOS transistor 141 is lowered becomes high, and the timing at which the mask signal MS output from the dv / dt detection circuit 140 becomes L level is advanced. Accordingly, the STB terminal of the D latch circuit 121 can be set to the L level earlier than the error signal is output from the level shift circuit 110, and the error signal can be more reliably masked in the D latch circuit 121.

<Embodiment 2>
FIG. 4 is a diagram illustrating a configuration of a drive circuit according to the second embodiment. In the drive circuit, delay circuits 161 and 162 are inserted in the subsequent stage of the level shift circuit 110 of the P-side drive circuit 100 and the subsequent stage of the dv / dt detection circuit 140 in the configuration of FIG.

  The delay circuit 161 functions to delay the rising timing of the level shift signal LS (the falling timing is hardly delayed). The delay circuit 162 functions to delay the rising timing of the mask signal MS (the falling timing is hardly delayed).

  FIG. 5 shows the operation of the D latch circuit (mask circuit) in the second embodiment. In the present embodiment, a signal whose leading edge (leading edge) of the convex pulse of the level shift signal LS is delayed by the delay time td1 is input to the D terminal of the D latch circuit 121, and the trailing edge ( A signal whose trading edge is delayed by a delay time td2 is input. That is, the delay circuit 161 functions as a pulse width conversion circuit that narrows the width of the convex pulse of the level shift signal LS, and the delay circuit 162 functions as a pulse width conversion circuit that widens the width of the concave pulse of the mask signal MS.

  As a result, when a dv / dt displacement current is generated, the D terminal changes to H level after the STB terminal changes to L level, and then the STB terminal changes to H level after the D terminal changes to L level. To come. That is, since the STB terminal is always at the L level while the D terminal changes to the H level due to the occurrence of the dv / dt displacement current (while the error signal is generated), the error signal of the level shift signal LS. Can be more reliably masked, and the effect of preventing malfunction is enhanced.

  Each of the delay circuits 161 and 162 can be realized by, for example, the delay circuit shown in FIG. This delay circuit is connected to an inverter IV11 that receives an input signal (corresponding to a level shift signal LS or a mask signal MS), an inverter IV12 that receives an output of the inverter IV11, and a connection point (point e) between the inverter IV11 and the inverter IV12. And the capacitor C10.

  As a method of operating the delay circuit of FIG. 6 so as to delay only the rising timing of the input signal (not delaying the falling timing), for example, it is conceivable to make a difference between the charging speed and the discharging speed of the capacitor C10. For example, as shown in FIG. 7, the inverter IV11 can be composed of a transistor Tc that charges the capacitor C10 and a transistor Td that discharges the capacitor C10. However, the current Id when the transistor Td discharges the capacitor C10 is changed to the transistor Tc. Is smaller than the current Ic that flows when charging the capacitor C10.

  The operation of the delay circuit in that case is shown in FIG. “Vth” in the figure indicates the threshold voltage of the inverter IV12. Since the current Id that discharges the capacitor C10 is small, the speed at which the level at the point e decreases when the input signal rises, and the rise timing of the output signal (output of the inverter IV12) is delayed by that amount. On the other hand, since the current Ic for charging the capacitor C10 is large, the level at the point e rises quickly when the input signal falls, and the fall timing of the output signal is not delayed.

  As another method, it is conceivable to lower the threshold voltage Vth of the inverter IV12. The operation of the delay circuit in that case is shown in FIG. Since the threshold voltage Vth of the inverter IV2 is low, when the input signal rises, the output of the inverter IV1 is not inverted until the level at the point e is sufficiently lowered, and the rise timing of the output signal is delayed by that amount. On the other hand, when the input signal falls, the level at the point e immediately exceeds the threshold voltage Vth, so the fall timing of the output signal is not delayed.

<Embodiment 3>
FIG. 10 is a diagram illustrating a configuration of a drive circuit according to the third embodiment. The drive circuit is obtained by providing a speed-up circuit 170 in the P-side drive circuit 100 with respect to the configuration of FIG.

  The speed-up circuit 170 includes an inverter 171 that inverts the input signal DC, a pulse generation circuit 172 that outputs a one-shot pulse signal when the output of the inverter 171 rises, a level shift circuit that receives the pulse signal, and the level shift A P-channel type high voltage MOS transistor 178 driven by the output of the circuit.

  The level shift circuit in the high speed circuit 170 includes a high voltage MOS transistor 173 having a gate to which a pulse signal from the pulse generation circuit 172 is supplied, and a resistance element 174 connected between the drain of the high voltage MOS transistor 173 and the VB potential. And an inverter 176 that receives a signal appearing at the drain of the high-voltage MOS transistor 173, and an inverter 177 that receives the output of the inverter 176. The source of the high voltage MOS transistor 173 is connected to the GND potential. The level shift circuit is provided with a diode 175 having an anode connected to the VS potential and connected to the drain of the high voltage MOS transistor 173.

  The high-voltage MOS transistor 178 has a gate to which the output of the inverter 177 is supplied, and is connected in parallel to the resistance element 112 of the level shift circuit 110.

  The speed-up circuit 170 operates during the off period of the high voltage MOS transistor 111 of the level shift circuit 110, at least when the high voltage MOS transistor 111 is turned off. That is, when the input signal DC changes from the H level to the L level, the output of the inverter 171 changes from the L level to the H level, and the pulse generation circuit 172 outputs a one-shot pulse signal in response to the rise. This pulse signal turns on the high voltage MOS transistor 173, a voltage drop occurs in the resistance element 174, and the input of the inverter 176 becomes L level. Accordingly, the output of inverter 176 becomes H level, the output of inverter 177 becomes L level, and high voltage MOS transistor 178 is turned on.

  On the other hand, in the level shift circuit 110, when the input signal DC becomes L level, the high voltage MOS transistor 111 is turned off and the drain level rises. At this time, the high voltage MOS transistor 178 connected in parallel to the resistance element 112 By turning on, the time constant of the circuit is reduced, and the rising speed of the drain level of the high-voltage MOS transistor 111 is increased. As a result, the response speed of the level shift circuit 110 increases, and the operation speed can be increased.

  The high-voltage MOS transistor 173 of the high-speed circuit 170 is driven by a DC signal having a phase opposite to that of the input signal DC (that is, the pulse generation circuit 172 is omitted), and the high-voltage MOS transistor 111 is turned off while it is off. The MOS transistor 178 may be configured to be continuously turned on, but in that case, the time during which the high-voltage MOS transistor 173 is turned on becomes longer, so that power consumption increases. As in this embodiment, the pulse generation circuit 172 is driven by a pulse signal, and the high voltage MOS transistor 173 is turned on only when the high voltage MOS transistor 111 is turned off, so that an increase in power consumption can be suppressed.

<Embodiment 4>
FIG. 11 is a diagram illustrating a configuration of a drive circuit according to the fourth embodiment. The drive circuit is obtained by adding an inverter 115 to the input stage of the level shift circuit 110 and adding an inverter 116 to the output stage in the configuration of FIG.

  In the present embodiment, the period during which the high voltage MOS transistor 111 of the level shift circuit 110 is turned on and the period during which the high voltage MOS transistor 111 is turned off are opposite to those in the first embodiment. That is, the high-voltage MOS transistor 111 is turned off while the input signal DC is H level and the P-side switching device 10 is on, and the input signal DC is L level and the P-side switching device 10 is turned off. Turns on while

  The VB potential transitions between a high voltage state (VP side) and a low voltage state (GND side) by switching of the P side and N side switching devices 10, but according to the present embodiment, the VB potential is in a low voltage state in a steady state. (When the P-side switching device 10 is off), the high voltage MOS transistor 111 is turned on. In the present invention, since the input signal DC is a direct current signal, the high voltage MOS transistor 111 is turned on for a relatively long time, causing an increase in power consumption. In this embodiment, the VB potential is in a low voltage state. Since the high voltage MOS transistor 111 is sometimes turned on, an increase in power consumption can be suppressed.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  10 P side switching device, 20 N side switching device, 100 P side drive circuit, 110 level shift circuit, 111, 141, 173, 178 high voltage MOS transistor, 112, 142, 174 resistance element, 113, 143 diode, 114-116 , 144 to 145, 171, 176, 177 Inverter, 120 mask circuit, 121 D latch circuit, 130 output circuit, 140 dv / dt detection circuit, 150 P side power supply, 161, 162 delay circuit, 170 high speed circuit, 172 pulses Generation circuit, 200 N side drive circuit.

Claims (8)

A level shift circuit that converts an input signal, which is a DC signal, into a level shift signal that is level-shifted to a signal with a predetermined potential as a reference;
A dv / dt detection circuit that detects the occurrence of a dv / dt displacement current due to the fluctuation of the predetermined potential and outputs a detection signal indicating the occurrence of the dv / dt displacement current;
A mask circuit for transmitting the level shift signal to an output circuit of a drive signal and masking the level shift signal according to the detection signal;
The level shift circuit includes a first load element connected in series and a first switching element controlled by the input signal, and outputs a signal corresponding to a voltage drop of the first load element as the level shift signal,
The dv / dt detection circuit includes a second load element connected in series and a second switching element fixed off in a steady state, and outputs a signal corresponding to a voltage drop of the second load element as the detection signal. A driving circuit. 2. The drive circuit according to claim 1, wherein the mask circuit is a D latch circuit including an input terminal to which the level shift signal is supplied, a strobe terminal to which the detection signal is supplied, and an output terminal connected to the output circuit. The drive circuit according to claim 1, wherein the level shift circuit further includes a Schmitt trigger circuit to which a signal appearing at a connection point between the first load element and the first switching element is input. The drive circuit according to any one of claims 1 to 3, wherein the second load element is a Zener diode. The level shift signal is supplied to the mask circuit via a first pulse width conversion circuit that narrows the pulse width,
5. The drive circuit according to claim 1, wherein the detection signal is supplied to the mask circuit via a second pulse width conversion circuit that widens the pulse width. 6. A third switching element connected in parallel to the first load element;
6. The drive circuit according to claim 1, wherein the third switching element is controlled to be turned on during an off period of the first switching element. The drive circuit according to claim 6, wherein the third switching element is controlled to be turned on only when the first switching element is turned off. The level shift circuit is configured to output the level shift signal for turning off a switching device driven by the drive circuit when the first switching element is turned off. Item 8. The drive circuit according to any one of Items 7.

Images