CN117220661A - Anti-noise-interference gate driving circuit - Google Patents

Abstract

The present disclosure provides a gate driving circuit resistant to noise interference, comprising: the PWM waveform shaping circuit is used for shaping the initial square wave signal; the dead zone control logic circuit is used for generating a non-overlapped first square wave signal and a second square wave signal based on the shaped initial square wave signal, and the non-overlapped time of the first square wave signal and the second square wave signal forms dead zone time; the voltage level conversion circuit is used for converting the first square wave signal and the second square wave signal into a first high-voltage square wave signal and a second high-voltage square wave signal; the output stage circuit is used for pulling the output signal of the output stage circuit to the high level when the first high-voltage square wave signal is at the high level and the second high-voltage square wave signal is at the low level, and outputting current to the output port of the output stage circuit when the miller platform appears; when the first high-voltage square wave signal is at a low level and the second high-voltage square wave signal is at a high level, the electric charge of the output port of the output stage circuit is released, and the output signal of the output stage circuit is pulled to the low level.

Description

Anti-noise-interference gate driving circuit

Technical Field

The present disclosure relates to the field of semiconductor integrated circuits, and more particularly, to a gate driving circuit with noise immunity.

Background

The MOSFET grid driving circuit is widely applied to switching power supplies, photovoltaic inverters and motor driver systems, is connected with a microcontroller MCU and a driven large-size power MOSFET, and the voltage and the current of PWM signals output by the microcontroller MCU are small and insufficient to enable the power MOSFET with a high voltage threshold to be fully conducted. The output PWM wave driving capability of the microcontroller is increased by the grid driving circuit, and the large-size MOSFET can be driven under a smaller signal. To implement the digital logic control circuit to control the power MOSFET.

The MOSFET grid driving circuit is used for eliminating voltage noise coupled to the system in the environment in one system, so that the capability of driving signals is improved; secondly, accelerating the switching process of the MOSFET and reducing the switching loss of the MOSFET; and finally, reducing the current change rate di/dt generated by the MOSFET switch, and protecting the grid electrode from breakdown of the grid electrode of the MOSFET by abnormal high voltage. However, it is difficult for the basic gate driving circuit to achieve these excellent performances at the same time, and thus it is necessary to develop a gate driving circuit having noise immunity and a large driving current to achieve the above functions.

Disclosure of Invention

In view of the above, the present invention provides a gate driving circuit with noise immunity to solve the above technical problems.

One aspect of the present disclosure provides a gate driving circuit resistant to noise interference, comprising: the input end of the PWM waveform shaping circuit is input with an initial square wave signal and is used for shaping the initial square wave signal; the dead zone control logic circuit is connected with the output end of the PWM waveform shaping circuit, and is used for generating a non-overlapped first square wave signal and a second square wave signal based on the shaped initial square wave signal, generating a Miller clamp control signal based on the first square wave signal and the second square wave signal, and forming dead zone time by the non-overlapped time of the first square wave signal and the second square wave signal; the first input end of the voltage level conversion circuit is connected with the output end of the first square wave signal, the second input end of the voltage level conversion circuit is connected with the output end of the second square wave signal, and the voltage level conversion circuit is used for lifting the voltages of the first square wave signal and the second square wave signal to obtain a first high-voltage square wave signal and a second high-voltage square wave signal; the first input end of the miller compensation output stage circuit is connected with the output end of the first high-voltage square wave signal, the second input end of the miller compensation output stage circuit is connected with the output end of the second high-voltage square wave signal, and the miller compensation output stage circuit is used for pulling the output signal of the miller compensation output stage circuit to the high level when the first high-voltage square wave signal is in the high level and the second high-voltage square wave signal is in the low level, and outputting current to the output port of the miller compensation output stage circuit when a miller platform appears so as to shorten the miller platform time; and when the first high-voltage square wave signal is at a low level and the second high-voltage square wave signal is at a high level, releasing the charge of the output port of the miller compensation output stage circuit, and pulling the output signal of the miller compensation output stage circuit to a low level.

According to an embodiment of the present disclosure, the PWM waveform shaping circuit includes: the front-stage open-loop hysteresis comparator is used for carrying out differential comparison on the initial square wave signal and the comp signal, generating hysteresis voltage and outputting a voltage signal based on a differential comparison result and the hysteresis voltage; and the second stage of Schmitt trigger is used for strengthening the hysteresis effect of the hysteresis voltage, shaping the voltage signal and outputting the initial square wave signal for filtering noise interference.

According to an embodiment of the present disclosure, the pre-stage open loop hysteresis comparator includes: NMOS tubes M1, M2, M7, M8, M9 and M12, PMOS tubes M3, M4, M5, M6, M10 and M11, and resistors R1, R2 and R3; the grid of M1 is the input end of the initial square wave signal, the sources of M1 and M2 are connected with the drain electrode of M7, the drain electrode of M1 is connected with the drain electrodes of M3 and M6, the drain electrode of M2 is connected with the drain electrodes of M4 and M5, the sources of M3, M4, M5, M6, M10 and M11 are connected with the power supply end of VDDL, the grids of M3, M5 and M10 are connected, the grids of M4, M6 and M11 are connected, the drain electrode of M10 is connected with the drain electrode of M8, the drain electrode of M8 is connected with the grid electrode thereof, the drain electrode of M11 is connected with the drain electrode of M9, the grid of M8 and M9 is connected, the sources of M7, M8, M9 and M12 are grounded, the grid of M7 and M12 are connected, the grid of M12 is connected with the drain, the drain of M12 is connected with one end of R3, the other end of R3 is connected with a VDDL power supply end, R1 and R2 are connected in series between the VDDL power supply end and the grounding end, the grid of M2 is connected between R1 and R2, the comp signal is input, and the comp signal is one half of the voltage signal of the VDDL power supply end.

According to an embodiment of the present disclosure, the second stage schmitt trigger includes: NMOS tubes M13, M14 and M18, PMOS tubes M15, M16 and M17; the gates of M13, M14, M15 and M16 are connected with the drains of M9 and M11, the source of M13 and the drain of M17 are grounded, the drain of M13, the source of M14 and the source of M18 are connected, the drain of M14 is connected with the drain of M15, the source of M15, the drain of M16 and the source of M17 are connected, the source of M16 and the drain of M18 are connected with the VDDL power supply end, and the drains of M14 and M15 and the gates of M17 and M18 are commonly connected with the output end of the PWM waveform shaping circuit.

According to an embodiment of the present disclosure, the dead zone control logic circuit includes: NAND gates NAND1 and NAND2, inverters INV1, INV2, INV3, INV4, and INV5; the first input end of the NAND1 and the input end of the INV1 are commonly connected with the input end of the dead zone control logic circuit, the first input end of the output end NAND2 of the INV1 is connected with the input end of the INV2, the output end of the INV2 is connected with the input end of the INV4, the output end of the INV4 is connected with the second input end of the NAND2, the output end of the NAND3 is connected with the input end of the INV3, the output end of the INV3 is connected with the input end of the INV5, and the output end of the INV5 is connected with the second input end of the NAND 1; the output end of INV2 outputs the first square wave signal, the output end of INV3 outputs the second square wave signal, and the output end of INV4 outputs the miller clamp control signal.

According to an embodiment of the present disclosure, the voltage level conversion circuit includes a first sub-conversion circuit and a second sub-conversion circuit, input terminals of the first sub-conversion circuit and the second sub-conversion circuit respectively correspond to the first input terminal and the second input terminal; the first sub-conversion circuit and the second sub-conversion circuit each include: NMOS tubes M1 and M2, PMOS tubes M3, M4, M5 and M6, inverters INV1, INV2; the first input end or the second input end is connected with the grid electrode of the M1 and the first input end of the INV1, the second input end of the INV1 is connected with the VDDL power end, the INV1 is grounded, the output end of the INV1 is connected with the grid electrode of the M2, the sources of the M1 and the M2 are grounded, the drains of the M1 and the M3 are connected with the grid electrode of the M5, the drains of the M2 and the M4 are connected with the grid electrode of the M6, the sources of the M5 and the M6 are connected with the source electrode of the M3, the drains of the M6 are connected with the source electrode of the M4, the grid electrode of the M3 and the drain electrode of the M4 are in cross connection, the first input end of the INV2 is connected with the drain electrode of the M1, the second input end of the INV5 and the source electrode of the M6 are grounded, and the output end of the INV2 outputs the first high-voltage square wave signal or the second high-voltage square wave signal; VBST voltage is led out from the connection position of the sources of M5 and M6 and the second input end of INV2 in the first sub-conversion circuit to the Miller compensation output stage circuit, and the sources of M5 and M6 and the second input end of INV2 in the second sub-conversion circuit are connected with the VDDL power end.

According to an embodiment of the present disclosure, the miller compensation output stage circuit includes: NMOS tubes M1, M2, M4, M6, M7, M8, M9, M10, M11, M12 and M13, PMOS tubes M3 and M5, and a capacitor C; the gates of M1, M3, M4 and M7 are input with the first high voltage square wave signal, the drain of M3, the drain of M4 and the gate of M8 are connected, the source of M7, the drain of M8 and the gate of M11 are connected, the source of M3, the drain of M7, the source of M13 and one end of C are connected with the output terminal of the voltage level conversion circuit output VBST voltage, the drains and gates of M1, M11 and M13 are connected with the VDDL power supply terminal, the source of M13 is connected with the output terminal of the VBST voltage, the source of M1 is connected with the drain of M2, the source of M4, the source of M8 and the source of M11, the gate of M5, the source of M6 and the gate of M10 are led out of the output terminal at the junction point of the source of M1 and the source of M11, the other end of C is connected with the output terminal, the gate of M2 is input with the second high voltage square wave signal, the sources of M2, M6, M10 and M12 are grounded, the drain of M2 is connected with the gates of M5, M6 and M10, the drain of M5 and the drain of M10 is connected with the junction point of the drain of M9 and the drain of M12 and the source of M12 is connected with the source of M9 and the source of M11.

The above at least one technical scheme adopted in the embodiment of the disclosure can achieve the following beneficial effects:

the anti-noise-interference grid driving circuit provided by the embodiment of the disclosure shapes the PWM square wave, improves the anti-noise interference capability of the circuit, improves the PWM voltage, generates a certain dead time, improves the output current driving capability, compensates the Miller platform of the switching MOSFET, accelerates the switching speed of the driven MOSFET, reduces the switching loss, and weakens the adverse effects caused by the voltage and current change rate.

Drawings

For a more complete understanding of the present disclosure and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 schematically illustrates a block topology of a noise-immune gate drive circuit provided by an embodiment of the present disclosure;

fig. 2 schematically illustrates a topology structure diagram of a PWM shaping circuit provided by an embodiment of the present disclosure;

FIG. 3 schematically illustrates a schematic block diagram of a dead zone control logic circuit provided by an embodiment of the present disclosure;

FIG. 4 schematically illustrates a Level Shift topology of a voltage Level conversion circuit provided by an embodiment of the present disclosure;

FIG. 5 schematically illustrates a circuit topology of a Miller compensated output stage provided by an embodiment of the disclosure;

fig. 6 schematically illustrates a connection manner of each part of a gate driving circuit according to an embodiment of the present disclosure.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and/or the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.

All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It should be noted that the terms used herein should be construed to have meanings consistent with the context of the present specification and should not be construed in an idealized or overly formal manner.

Fig. 1 schematically illustrates a topological block diagram of a gate drive circuit that is resistant to noise interference provided by an embodiment of the present disclosure.

As shown in fig. 1, an embodiment of the present disclosure provides a gate driving circuit that is resistant to noise interference, including a PWM waveform shaping circuit, a dead zone control logic circuit, a voltage level conversion circuit, and a miller compensation output stage circuit.

The input end of the PWM waveform shaping circuit inputs an initial square wave signal for shaping the initial square wave signal.

The input end of the dead zone control logic circuit is connected with the output end of the PWM waveform shaping circuit and is used for generating a non-overlapped first square wave signal and a second square wave signal based on the shaped initial square wave signal, generating a Miller clamp control signal based on the first square wave signal and the second square wave signal, and forming dead zone time by the non-overlapped time of the first square wave signal and the second square wave signal.

And the first input end of the voltage level conversion circuit is connected with the output end of the first square wave signal, and the second input end of the voltage level conversion circuit is connected with the output end of the second square wave signal and is used for boosting the voltage of the first square wave signal and the second square wave signal to obtain a first high-voltage square wave signal and a second high-voltage square wave signal.

The first input end of the miller compensation output stage circuit is connected with the output end of the first high-voltage square wave signal, the second input end of the miller compensation output stage circuit is connected with the output end of the second high-voltage square wave signal, and the miller compensation output stage circuit is used for pulling the output signal of the miller compensation output stage circuit to the high level when the first high-voltage square wave signal is in the high level and the second high-voltage square wave signal is in the low level, and outputting current to the output port of the miller compensation output stage circuit when the miller platform appears so as to shorten the miller platform time; when the first high-voltage square wave signal is at a low level and the second high-voltage square wave signal is at a high level, the electric charge of the output port of the miller compensation output stage circuit is released, and the output signal of the miller compensation output stage circuit is pulled to the low level.

Fig. 2 schematically illustrates a topology structure diagram of a PWM shaping circuit provided by an embodiment of the present disclosure.

As shown in fig. 2, the PWM wave shaping circuit mainly includes a front-stage open-loop hysteresis comparator formed by transistors M1-M12 and a second-stage schmitt trigger formed by M13-M18, the front-stage open-loop hysteresis comparator is configured to differentially compare an initial square wave signal and a comp signal and generate a hysteresis voltage, and output a voltage signal based on the differential comparison result and the hysteresis voltage; the second stage schmitt trigger is used for strengthening the hysteresis effect of the hysteresis voltage, shaping the voltage signal and outputting an initial square wave signal for filtering noise interference.

Specifically, the front-stage open-loop hysteresis comparator includes: NMOS tubes M1, M2, M7, M8, M9 and M12, PMOS tubes M3, M4, M5, M6, M10 and M11, and resistors R1, R2 and R3; the grid electrode of M1 is an input end of an initial square wave signal, the source electrodes of M1 and M2 are connected with the drain electrode of M7, the drain electrodes of M1 are connected with the drain electrodes of M3 and M6, the drain electrode of M2 is connected with the drain electrodes of M4 and M5, the source electrodes of M3, M4, M5, M6, M10 are connected with the power supply end of VDDL, the grid electrodes of M3, M5 and M10 are connected with the grid electrodes of M4, M6 and M11, the drain electrode of M10 is connected with the drain electrode of M8, the drain electrode of M8 is connected with the drain electrode of M9, the source electrodes of M7, M8, M9 and M12 are grounded, the grid electrode of M7 is connected with the grid electrode of M12, the drain electrode of M12 is connected with the drain electrode of M3, the other end of R3 is connected with the power supply end of VDDL, the R1 and R2 are connected between the power supply end of VDDL and the ground, the grid electrode of M2 is connected between R1 and R2, the grid electrode of M8 is connected with the power supply end of C, the comp signal is one half of the voltage of the VDDL.

The second stage Schmidt trigger comprises NMOS tubes M13, M14 and M18, and PMOS tubes M15, M16 and M17; the gates of M13, M14, M15 and M16 are connected with the drains of M9 and M11, the source of M13 and the drain of M17 are grounded, the drain of M13, the source of M14 and the source of M18 are connected, the drain of M14 is connected with the drain of M15, the source of M15, the drain of M16 and the source of M17 are connected, the source of M16 and the drain of M18 are connected with the VDDL power supply end, and the drains of M14 and M15 and the gates of M17 and M18 are commonly connected with the output end of the PWM waveform shaping circuit.

The front stage adopts M1 and M2 as differential input, and the mode of M3-M6 cross coupling pair is used for making load to improve the gain of the front stage comparator to make up the disadvantages of small mobility and lower intrinsic gain of the 4H-SiC MOSFET, and in addition, the hysteresis voltage effect can be generated; M8-M11 are complementary output stages of the comparator, and can increase the capacity of output current and increase the slew rate of output voltage; meanwhile, the positive feedback in the M13-M18 Schmitt trigger is utilized to play roles in strengthening hysteresis effect and accelerating the comparison result of the front stage to be pulled to the power supply voltage and the ground. Input of a noisy PWM signal V with a high level of 5V and a low level of 0V _in Comparing with about one half of the power supply voltage comp signal, outputting PWM square wave signal V with noise interference filtered by the action of the reverse phase and hysteresis of the Schmitt trigger _out ，V _out The signal is connected with the input signal of the logic circuit.

Input voltage V _in Assuming that the initial input signal voltage is at a high level of 5V, the gate voltage of the transistor M1 is greater than the gate voltage of the transistor M2, the current of the transistor M1 is greater than the current of the transistor M2, the gate voltage of the transistor M10 is less than the gate voltage of the transistor M11, and then the current of the transistor M10 is greater than the current of the transistor M11, the current copied to the transistor M9 through the transistor M8 is greater than the current of the transistor M11, so the transistor M9 is required to draw current from the output terminal, so the comparator output voltage is at a low level of 0V,and then outputs to high level 5V through a Schmitt trigger. Input voltage V _in When the voltage of the grid electrode of the transistor M1 is lower than that of the grid electrode of the transistor M2 when the voltage is reduced from 5V to 0V, the current of the transistor M1 is lower than that of the transistor M2, the grid electrode of the transistor M10 is higher than that of the transistor M11, the current of the transistor M10 is lower than that of the transistor M11, the current copied to the transistor M9 through the transistor M8 is lower than that of the transistor M11, and therefore the transistor M11 outputs current from an output end, the output voltage of the comparator is high level 5V, and the output voltage of the comparator is low level 0V through a Schmidt trigger.

Fig. 3 schematically illustrates a topology structure of a dead zone control logic circuit provided by an embodiment of the present disclosure.

As shown in fig. 3, the dead zone control logic circuit may generate dead zone time and miller clamp control signals, and is composed of NAND gate NAND and inverter INV delay units, wherein the inverter delay units are composed of an even number of inverter cascade units, and may be configured as nanosecond dead zone time according to the requirements of an applied system.

Specifically, the dead zone control logic circuit may include NAND gates NAND1 and NAND2, inverters INV1, INV2, INV3, INV4, and INV5; the first input end of the NAND1 and the input end of the INV1 are commonly connected with the input end of the dead zone control logic circuit, the output end of the INV1 is connected with the first input end of the NAND2, the output end of the INV2 is connected with the input end of the INV4, the output end of the INV4 is connected with the second input end of the NAND2, the output end of the NAND3 is connected with the input end of the INV3, the output end of the INV3 is connected with the input end of the INV5, and the output end of the INV5 is connected with the second input end of the NAND 1; the output end of the INV2 outputs a first square wave signal, the output end of the INV3 outputs a second square wave signal, and the output end of the INV4 outputs a miller clamp control signal.

The wave-shaped square wave signal can generate two paths of non-overlapped square wave signals V _OTL And M _OTH The non-overlap time is dead time, and the external miller clamp signal V is generated _CTRL . The output signal of the PWM wave shaping circuit is connected with the input of the logic control circuit, and when the input V of the logic control circuit _in V when jumping from low level to high level _OTL The falling edge of the signal is earlier than M _OTH The rising edge of the signal is delayed by a dead time. From an input square wave signal V _in Generating control signals for high-side and low-side MOSFETs, V _OTL The falling edge of the signal always being earlier than M _OTH Rising edge of signal M _OTH The falling edge of the signal always being earlier than V _OTL Rising edges of the signal. V (V) _OTL Signal sum M _OTH The signals are respectively connected with a level conversion circuit.

Fig. 4 schematically illustrates a Level Shift topology of a voltage Level conversion circuit according to an embodiment of the present disclosure.

As shown in fig. 4, the voltage level conversion circuit includes NMOS transistors M1 and M2, PMOS transistors M3, M4, M5 and M6, and inverters INV1 and INV2. The first input end or the second input end is connected with the grid electrode of the M1 and the first input end of the INV1, the second input end of the INV1 is connected with the VDDL power end, the INV1 is grounded, the output end of the INV1 is connected with the grid electrode of the M2, the source electrodes of the M1 and the M2 are grounded, the drain electrodes of the M1 and the M3 are connected with the grid electrode of the M5, the drain electrodes of the M2 and the M4 are connected with the grid electrode of the M6, the drain electrode of the M5 is connected with the source electrode of the M3, the drain electrodes of the M3 and the M4 are in crossed interconnection, the first input end of the INV2 is connected with the drain electrode of the M1, the second input end of the INV2 is connected with the source electrodes of the M5 and the M6, the drain electrodes of the INV2 are grounded, and the output end of the INV2 outputs a first high-voltage square wave signal or a second high-voltage square wave signal.

In this embodiment, the voltage level conversion circuit includes a first sub-conversion circuit and a second sub-conversion circuit, the input terminals of the first sub-conversion circuit and the second sub-conversion circuit correspond to the first input terminal and the second input terminal, respectively, and the first sub-conversion circuit and the second sub-conversion circuit have the structure shown in fig. 4. Referring to fig. 6, the difference between the first sub-conversion circuit and the second sub-conversion circuit is that the connection between the sources of M5 and M6 and the second input end of INV2 in the first sub-conversion circuit leads out VBST voltage to the miller compensation output stage circuit, and the sources of M5 and M6 and the second input end of INV2 in the second sub-conversion circuit are connected to the VDDL power supply end.

By using new adjustable cross-coupled pull-up transistors M5 and M6, the node voltage discharge speed is increased and reducedThe dynamic power consumption of the circuit is low. The proposed level shift circuit can convert two paths of non-overlapping square wave signals V with high level of 5V generated by a logic circuit _OTL And M _OTH Converted into a square wave voltage with a high level of 20V, and then transmitted to an output stage circuit for inputting a signal V _CTH And V _CTL 。

Assume at an initial time that the voltage at node V1 is relatively high and the voltage at V2 is relatively low. Thus, the M3 and M6 tubes are on, and the M4 and M5 tubes are off. When the input signal jumps from low to high, the M1 pipe is caused to be turned on, and the M2 pipe is caused to be turned off. Thus, the parasitic capacitance in the V1 node begins to discharge, and the node V1 discharges very quickly since the pull-up current through the M3 tube is very low when the M5 tube is turned off, continuing until the V1 node voltage drops to VDDH-V _TP V at the time of _TP The threshold voltage of PMOS, at which time the M4 and M5 tubes start to turn on. When the M4 tube is turned on, the V2 node voltage starts to increase and causes the M3 tube and the M6 tube to gradually turn off. In this process, the pull-up PMOS structure plays an important role again and causes the voltage of the V2 node to increase rapidly. The M6 tube is turned off before the voltage at the V2 node reaches VDDH, so the voltage at the V2 node is always slightly lower than VDDH. Thus, the maximum voltage of the intermediate nodes V1 and V2 is always lower than VDDH, which helps to reduce dynamic power consumption. In addition, transistors in the pull-up PMOS structure never completely turn off and always operate in the deep sub-threshold region because there is always a small voltage difference between their gate and source voltages, which helps the PMOS pull-up transistors change their operating states faster, further improving circuit speed. Finally, when the M3 pipe is turned off, the M1 pipe can reduce the voltage of the node V1 even if the input voltage is lower than the M1 pipe threshold voltage. By closing the M3 and M6 tubes, no quiescent current will eventually flow through the left and right branches, and therefore the PMOS pull-up section in the level shift circuit reduces power consumption and level shift time significantly. Similarly, when the input signal jumps from high level to low level, the circuit operates in a similar manner, but the same acceleration effect can be achieved.

Fig. 5 schematically illustrates a miller compensated output stage circuit topology provided by an embodiment of the disclosure.

As shown in FIG. 5, the Miller compensation output stage circuit comprises NMOS transistors M1, M2, M4, M6, M7, M8, M9, M10, M11, M12 and M13, PMOS transistors M3 and M5, and a capacitor C; the gates of M1, M3, M4 and M7 are input with a first high-voltage square wave signal, the drain of M3, the drain of M4 and the gate of M8 are connected, the source of M7, the drain of M8 and the gate of M11 are connected, the source of M3, the drain of M7, the source of M13 and one end of C are connected with the output end of the voltage level conversion circuit output VBST voltage, the drains of M1, M11 and the drains and gates of M13 are connected with the power supply end of VDDL, the source of M13 is connected with the output end of VBST voltage, the source of M1 is connected with the drain of M2, the source of M4, the source of M8 and the source of M11, the gate of M5, the gate of M6 and the gate of M10 are connected with the source of M1, the junction of the source of M2, the source of M6 and the source of M11 are led out of the output end, the other end of C is connected with the output end of C, the gate of M2 is input with a second high-voltage square wave signal, the drains of M2, M6, M10 and M12 are grounded, the drains of M2 are connected with the drains of M5, M6 and M10, the drain of M5 and the drain of M6 and the drain of M9 are connected with the drain of M9 and the source of M12 are connected with the source of M11, and the junction of the drain of M9 and M12 is connected with the source of M12.

The output stage circuit can provide high power output, large output and current filling capacity, compensates the miller stage and avoids the design of a single device with very large size. The high-power output stage is based on a double NMOS half-bridge output stage structure, the driving transistors of main excessive current are NMOS transistors M1, M2, M11 and M12 with four large sizes, and the size of each MOSFET can be reduced in a mode of forming two-stage driving by dividing the transistors into four. Transistors M3 and M4, M5 and M6 form an inverter structure providing correct logic for the second stage transistors M11 and M12, providing a large current at the miller stage. When V is _CTH Is of high level VDDH, V _CTL When the voltage is at low level, the M2 pipe and the M12 pipe are kept to be turned off, the M1 pipe is rapidly opened to drive V _OUT When the voltage is pulled to a high level VDDH, the M11 tube is conducted to output large current to VOUT when the Miller platform appears, the Miller platform time is reduced, the grid voltage of the driven power MOSFET is rapidly increased, and the bootstrap capacitor is connected with V _OUT The voltage rise is close to VDDH, V _BST The voltage will also rise approximately twice VDDH, whichGate-source voltage V of sample upper side driving tube M1 tube and M11 tube _gs At V _OUT During the voltage rise the clock remains close to the level of VDDH and the output current will be very large. When V is _CTH At low level, V _CTL When VDDH is at high level, the transistors M1 and M11 are turned off, the transistors M2 and M12 are turned on rapidly, the driven power MOSFET discharges charges through the transistors M2 and M12, and the output voltage V is outputted by matching with the low-resistance path of the Miller clamp _OUT Pulled low.

Fig. 6 schematically illustrates a connection manner of each part of a gate driving circuit according to an embodiment of the present disclosure.

As shown in fig. 6, the gate driving circuit includes a PWM waveform shaping circuit, a dead zone control logic circuit, a voltage level converting circuit, and a miller compensation output stage circuit as shown in fig. 2 to 5.

In the gate driving circuit provided by the embodiment of the disclosure, the PWM shaping circuit shapes the input square wave, and has efficient shaping to noise burrs coupled into the square wave from the environment. The voltage level conversion circuit converts the low-voltage square wave signal output by the micro controller MCU into a high-voltage control signal; the dead zone control logic circuit generates dead zone time to prevent the PMOS and NMOS of the output stage from being conducted simultaneously and generate a Miller clamp control signal at the same time; the miller stage compensation output stage circuit provides a large driving current to compensate the miller stage of the switching MOSFET, and improves the switching speed of the MOSFET. The grid driving circuit shapes the PWM square wave to improve the noise interference resistance of the circuit, improves the voltage of the PWM square wave, generates certain dead time, improves the driving capability of output current, compensates a miller platform of a switching MOSFET, accelerates the switching speed of the driven MOSFET, reduces the switching loss, and weakens the adverse effects caused by the change rate of the voltage and the current.

Those skilled in the art will appreciate that the features recited in the various embodiments of the disclosure and/or in the claims may be provided in a variety of combinations and/or combinations, even if such combinations or combinations are not explicitly recited in the disclosure. In particular, the features recited in the various embodiments of the present disclosure and/or the claims may be variously combined and/or combined without departing from the spirit and teachings of the present disclosure. All such combinations and/or combinations fall within the scope of the present disclosure.

While the present disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. The scope of the disclosure should, therefore, not be limited to the above-described embodiments, but should be determined not only by the following claims, but also by the equivalents of the following claims.

Claims (7)

1. A gate drive circuit that is resistant to noise interference, comprising:

the input end of the PWM waveform shaping circuit is input with an initial square wave signal and is used for shaping the initial square wave signal;

the dead zone control logic circuit is connected with the output end of the PWM waveform shaping circuit, and is used for generating a non-overlapped first square wave signal and a second square wave signal based on the shaped initial square wave signal, generating a Miller clamp control signal based on the first square wave signal and the second square wave signal, and forming dead zone time by the non-overlapped time of the first square wave signal and the second square wave signal;

the first input end of the voltage level conversion circuit is connected with the output end of the first square wave signal, the second input end of the voltage level conversion circuit is connected with the output end of the second square wave signal, and the voltage level conversion circuit is used for lifting the voltages of the first square wave signal and the second square wave signal to obtain a first high-voltage square wave signal and a second high-voltage square wave signal;

the first input end of the miller compensation output stage circuit is connected with the output end of the first high-voltage square wave signal, the second input end of the miller compensation output stage circuit is connected with the output end of the second high-voltage square wave signal, and the miller compensation output stage circuit is used for pulling the output signal of the miller compensation output stage circuit to the high level when the first high-voltage square wave signal is in the high level and the second high-voltage square wave signal is in the low level, and outputting current to the output port of the miller compensation output stage circuit when a miller platform appears so as to shorten the miller platform time; and when the first high-voltage square wave signal is at a low level and the second high-voltage square wave signal is at a high level, releasing the charge of the output port of the miller compensation output stage circuit, and pulling the output signal of the miller compensation output stage circuit to a low level.

2. The noise-immune gate drive circuit of claim 1, wherein the PWM waveform shaping circuit comprises:

the front-stage open-loop hysteresis comparator is used for carrying out differential comparison on the initial square wave signal and the comp signal, generating hysteresis voltage and outputting a voltage signal based on a differential comparison result and the hysteresis voltage;

and the second stage of Schmitt trigger is used for strengthening the hysteresis effect of the hysteresis voltage, shaping the voltage signal and outputting the initial square wave signal for filtering noise interference.

3. The noise-immune gate drive circuit of claim 2, wherein the pre-stage open-loop hysteresis comparator comprises:

NMOS tubes M1, M2, M7, M8, M9 and M12, PMOS tubes M3, M4, M5, M6, M10 and M11, and resistors R1, R2 and R3;

the grid of M1 is the input end of the initial square wave signal, the sources of M1 and M2 are connected with the drain electrode of M7, the drain electrode of M1 is connected with the drain electrodes of M3 and M6, the drain electrode of M2 is connected with the drain electrodes of M4 and M5, the sources of M3, M4, M5, M6, M10 and M11 are connected with the power supply end of VDDL, the grids of M3, M5 and M10 are connected, the grids of M4, M6 and M11 are connected, the drain electrode of M10 is connected with the drain electrode of M8, the drain electrode of M8 is connected with the grid electrode thereof, the drain electrode of Mi1 is connected with the drain electrode of M9, the grid of M8 and M9 is connected, the sources of M7, M8, M9 and M12 are grounded, the grid of M7 and M12 are connected, the grid of M12 is connected with the drain, the drain of M12 is connected with one end of R3, the other end of R3 is connected with a VDDL power supply end, R1 and R2 are connected in series between the VDDL power supply end and the grounding end, the grid of M2 is connected between R1 and R2, the comp signal is input, and the comp signal is one half of the voltage signal of the VDDL power supply end.

4. The noise-immune gate drive circuit of claim 3, wherein the second stage schmitt trigger comprises:

NMOS tubes M13, M14 and M18, PMOS tubes M15, M16 and M17;

the gates of M13, M14, M15 and M16 are connected with the drains of M9 and M11, the source of M13 and the drain of M17 are grounded, the drain of M13, the source of M14 and the source of M18 are connected, the drain of M14 is connected with the drain of M15, the source of M15, the drain of M16 and the source of M17 are connected, the source of M16 and the drain of M18 are connected with the VDDL power supply end, and the drains of M14 and M15 and the gates of M17 and M18 are commonly connected with the output end of the PWM waveform shaping circuit.

5. The noise-immune gate drive circuit of claim 1, wherein the dead zone control logic circuit comprises:

NAND gates NAND1 and NAND2, inverters INV1, INV2, INV3, INV4, and INV5;

the first input end of the NAND1 and the input end of the INV1 are commonly connected with the input end of the dead zone control logic circuit, the first input end of the output end NAND2 of the INV1 is connected with the input end of the INV2, the output end of the INV2 is connected with the input end of the INV4, the output end of the INV4 is connected with the second input end of the NAND2, the output end of the NAND3 is connected with the input end of the INV3, the output end of the INV3 is connected with the input end of the INV5, and the output end of the INV5 is connected with the second input end of the NAND 1;

the output end of INV2 outputs the first square wave signal, the output end of INV3 outputs the second square wave signal, and the output end of INV4 outputs the miller clamp control signal.

6. The noise-immune gate drive circuit of claim 1, wherein the voltage level conversion circuit comprises a first sub-conversion circuit and a second sub-conversion circuit, the inputs of the first sub-conversion circuit and the second sub-conversion circuit corresponding to the first input and the second input, respectively;

the first sub-conversion circuit and the second sub-conversion circuit each include:

NMOS tubes M1 and M2, PMOS tubes M3, M4, M5 and M6, inverters INV1, INV2;

the first input end or the second input end is connected with the grid electrode of the M1 and the first input end of the INV1, the second input end of the INV1 is connected with the VDDL power end, the INV1 is grounded, the output end of the INV1 is connected with the grid electrode of the M2, the sources of the M1 and the M2 are grounded, the drains of the M1 and the M3 are connected with the grid electrode of the M5, the drains of the M2 and the M4 are connected with the grid electrode of the M6, the sources of the M5 and the M6 are connected with the source electrode of the M3, the drains of the M6 are connected with the source electrode of the M4, the grid electrode of the M3 and the drain electrode of the M4 are in cross connection, the first input end of the INV2 is connected with the drain electrode of the M1, the second input end of the INV5 and the source electrode of the M6 are grounded, and the output end of the INV2 outputs the first high-voltage square wave signal or the second high-voltage square wave signal;

VBST voltage is led out from the connection position of the sources of M5 and M6 and the second input end of INV2 in the first sub-conversion circuit to the Miller compensation output stage circuit, and the sources of M5 and M6 and the second input end of INV2 in the second sub-conversion circuit are connected with the VDDL power end.

7. The noise-immune gate drive circuit of claim 1, wherein the miller compensation output stage circuit comprises:

NMOS tubes M1, M2, M4, M6, M7, M8, M9, M10, M1l, M12 and M13, PMOS tubes M3 and M5, and capacitor C;

the gates of M1, M3, M4 and M7 are input with the first high voltage square wave signal, the drain of M3, the drain of M4 and the gate of M8 are connected, the source of M7, the drain of M8 and the gate of M11 are connected, the source of M3, the drain of M7, the source of M13 and one end of C are connected with the output terminal of the voltage level conversion circuit output VBST voltage, the drains and gates of M1, M11 and M13 are connected with the VDDL power supply terminal, the source of M13 is connected with the output terminal of the VBST voltage, the source of M1 is connected with the drain of M2, the source of M4, the source of M8 and the source of M11, the gate of M5, the source of M6 and the gate of M10 are led out of the output terminal at the junction point of the source of M1 and the source of M11, the other end of C is connected with the output terminal, the gate of M2 is input with the second high voltage square wave signal, the sources of M2, M6, M10 and M12 are grounded, the drain of M2 is connected with the gates of M5, M6 and M10, the drain of M5 and the drain of M10 is connected with the junction point of the drain of M9 and the drain of M12 and the source of M12 is connected with the source of M9 and the source of M11.