CN109687861B

CN109687861B - Anti-noise high-voltage grid driving circuit

Info

Publication number: CN109687861B
Application number: CN201811612718.0A
Authority: CN
Inventors: 方健; 王定良; 雷一博; 张波; 王卓
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2018-12-27
Filing date: 2018-12-27
Publication date: 2021-05-14
Anticipated expiration: 2038-12-27
Also published as: CN109687861A

Abstract

An anti-noise high-voltage gate drive circuit belongs to the technical field of analog integrated circuits. The high-voltage level shift module improves signal level through an LDMOS (laterally diffused metal oxide semiconductor) tube, two input low-voltage pulse control signals are converted into high-voltage pulse signals and output to the common-mode noise elimination circuit together with the high-voltage common-mode signal, the common-mode noise elimination circuit eliminates common-mode noise by utilizing the principle of a differential mode amplifier, and the RS latch and the driving module convert narrow pulse signals with noise eliminated into output signals again for driving a high-side power tube. The invention can eliminate various common mode interference noises, can be suitable for narrower narrow pulse input signals and has lower circuit power consumption.

Description

Anti-noise high-voltage grid driving circuit

Technical Field

The invention belongs to the technical field of analog integrated circuits, and relates to an anti-noise high-voltage gate driving circuit.

Background

In a power chip or an integrated circuit driving chip, a high-voltage gate driving circuit exists, and the circuit adopts a high-voltage level shift technology to realize conversion from low voltage to high voltage so as to drive a high-side power tube. The high-voltage grid driving circuit belongs to a typical circuit of a high-voltage integrated circuit (HVIC), has wide application in the fields of motor driving, flat panel display and other consumer electronics, adopts a high-voltage and low-voltage compatible process, converts a low-voltage control signal into a high-voltage control signal by using a high-voltage LDMOS device so as to drive a high-end circuit to work, and generally adopts a half-bridge topology structure.

The half-bridge driving chip is mainly used for driving a power tube of an external topological structure, an internal driving circuit is divided into a high-voltage grid driving circuit and a low-voltage side driving circuit according to different working power supply voltages, and output point voltages work in a floating state along with the on and off of the power tube of the half-bridge topological structure, so that the voltage of the high-voltage grid driving circuit also works in the floating state along with the change of the output point voltages, and the function can be realized mainly through an external bootstrap circuit.

As shown in fig. 1, which is a structural diagram of a high voltage half-bridge driving circuit including a high voltage level shift circuit, T1 and T2 are two IGBT power transistors driven by a high voltage gate driving circuit, and the high voltage gate driving circuit is mainly used for driving the high side power transistor T1 to operate. The high-voltage gate driving circuit in the prior art mainly comprises a pulse generator, a high-voltage level shift circuit, a pulse filter circuit, an SR latch and a high-side driving circuit. In order to reduce the power consumption of the circuit, the pulse generator converts an input signal into a narrow pulse signal, the high-voltage level shift circuit converts a low-voltage narrow pulse relative to a ground signal GND into a high-voltage narrow pulse relative to a high-end floating ground VS, the pulse filter circuit filters out noise in an output signal of the high-voltage level shift circuit, the SR latch and the high-side driving circuit convert the narrow pulse signal into an output signal again, and the high-side power tube T1 is controlled to be switched on and off.

However, the high voltage level shift circuit is powered by the floating power supply VB, and since the drain terminal of the LDMOS transistor of the high voltage level shift circuit has a large parasitic capacitance, when the external power transistor is turned on and off, the floating power supply VB and the high terminal floating ground VS of the floating power supply VB will change dramatically, dv/dt interference noise is generated at the nodes of the floating power supply VB and the high terminal floating ground VS, the noise will form a charging current to the LDMOS parasitic capacitance through a load resistor on the LDMOS drain electrode, and the charging current will cause a certain voltage drop on the load resistor, that is, the output signal of the high voltage level shift circuit has a large common mode interference noise.

A level shift circuit is mentioned in the patent application with the name of 201510476899.9, entitled level shift circuit with anti-noise interference characteristic, and as shown in fig. 8, the level shift circuit eliminates interference by adopting additional LDMOS and PMOS transistors to charge the parasitic capacitance of two-input LDMOS transistors, but the requirement for narrow pulse width of a previous stage circuit is high, and the power consumption of the circuit is large.

Disclosure of Invention

Aiming at the problems of interference noise, narrow pulse width requirement and power consumption of the traditional high-voltage gate driving circuit, the invention provides the high-voltage gate driving circuit capable of resisting the noise interference, so that the transmission of normal signals is not influenced while the common-mode noise interference is eliminated, the power consumption is lower, and the narrow-pulse signal can be applied to narrower narrow-pulse signals.

The technical scheme of the invention is as follows:

an anti-noise high-voltage gate drive circuit comprises a high-voltage level shift module, a first common-mode noise elimination module, a second common-mode noise elimination module, an RS latch and a drive module,

the high-voltage level shift module comprises a first Zener diode, a second Zener diode, a third Zener diode, a fourth Zener diode, a fifth Zener diode, a sixth Zener diode, a seventh Zener diode, an eighth Zener diode, a ninth Zener diode, a first LDMOS transistor, a second LDMOS transistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and an eighth resistor,

the grid end of the first LDMOS tube is used as the first input end of the high-voltage level shift module, the drain end of the first LDMOS tube is used as the first output end of the high-voltage level shift module and is connected with a floating power supply through a third resistor, and the source end of the first LDMOS tube is grounded through a sixth resistor;

the grid end of the third LDMOS transistor is used as the second input end of the high-voltage level shift module, the drain end of the third LDMOS transistor is used as the second output end of the high-voltage level shift module and is connected with the floating power supply through the fifth resistor, and the source end of the third LDMOS transistor is grounded through the eighth resistor;

the grid end of the second LDMOS transistor is grounded, the drain end of the second LDMOS transistor is used as the third output end of the high-voltage level shift module and is connected with the floating power supply through the fourth resistor, and the source end of the second LDMOS transistor is grounded through the seventh resistor;

the cathode of the first Zener diode is connected with the floating power supply, and the anode of the first Zener diode is connected with the cathode of the second Zener diode; the cathode of the third Zener diode is connected with the anode of the second Zener diode, and the anode of the third Zener diode is connected with the drain terminal of the first LDMOS transistor;

the cathode of the fourth Zener diode is connected with the floating power supply, and the anode of the fourth Zener diode is connected with the cathode of the fifth Zener diode; the cathode of the sixth Zener diode is connected with the anode of the fifth Zener diode, and the anode of the sixth Zener diode is connected with the drain terminal of the second LDMOS transistor;

the cathode of the seventh Zener diode is connected with the floating power supply, and the anode of the seventh Zener diode is connected with the cathode of the eighth Zener diode; the cathode of the ninth Zener diode is connected with the anode of the eighth Zener diode, and the anode of the ninth Zener diode is connected with the drain terminal of the third LDMOS transistor;

a first input end of the first common mode noise elimination module is connected with a first output end of the high-voltage level shift module, a second input end of the first common mode noise elimination module is connected with a third output end of the high-voltage level shift module, and an output end of the first common mode noise elimination module is connected with an R input end of the RS latch;

the first input end of the second common mode noise elimination module is connected with the second output end of the high-voltage level shift module, the second input end of the second common mode noise elimination module is connected with the third output end of the high-voltage level shift module, and the output end of the second common mode noise elimination module is connected with the S input end of the RS latch;

the input end of the driving module is connected with the output end of the RS latch, and the output end of the driving module is used as the output end of the high-voltage grid driving circuit.

Specifically, the first common mode noise elimination module and the second common mode noise elimination module have the same structure, the first common mode noise elimination module comprises a first resistor, a second resistor, a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube,

the grid end of the first NMOS tube is connected with the grid end of the first PMOS tube and serves as the first input end of the first common mode noise elimination module, the drain end of the first NMOS tube is connected with the drain end of the first PMOS tube and the grid end of the second NMOS tube, and the source end of the first NMOS tube is connected with the source ends of the second NMOS tube, the third NMOS tube, the fourth NMOS tube and the fifth NMOS tube and is connected with a high-end floating ground;

the grid end of the second PMOS tube is connected with the grid end of the fifth NMOS tube and serves as the second input end of the first common mode noise elimination module, the drain end of the second PMOS tube is connected with the drain end of the fifth NMOS tube and the grid end of the fourth NMOS tube, and the source end of the second PMOS tube is connected with the source ends of the first PMOS tube and the third PMOS tube and is connected with the floating power supply;

one end of the first resistor is connected with the floating power supply, and the other end of the first resistor is connected with the drain end of the second NMOS tube; one end of the second resistor is connected with the floating power supply, and the other end of the second resistor is connected with the drain end of the fourth NMOS tube, the gate end of the third NMOS tube and the gate end of the third PMOS tube;

and the drain terminal of the third NMOS tube is connected with the drain terminal of the third PMOS tube and is used as the output terminal of the first common mode noise elimination module.

The invention has the beneficial effects that: the invention can effectively eliminate the influence of common mode dv/dt interference noise on the working state of the circuit under various conditions by utilizing the common mode noise elimination circuit, and does not influence normal signal transmission; the common mode noise elimination circuit is introduced to reduce the requirement on the narrow pulse width of a preceding stage circuit and reduce the conduction time of the LDMOS in the high-voltage level shift circuit, thereby effectively reducing the power consumption of the circuit.

Drawings

Fig. 1 is a block diagram of a high voltage half bridge driver circuit including a high voltage level shift circuit in the prior art.

Fig. 2 is a block diagram of a noise-immune high-voltage gate driving circuit according to the present invention.

Fig. 3 is a schematic diagram of a specific circuit structure of the high voltage level shift module according to the present invention.

Fig. 4 is a specific circuit diagram of the first common mode noise canceling first module in the present invention.

Fig. 5 is an equivalent architecture diagram of the drive module in the present invention.

Fig. 6 is a timing diagram of a noise immune high voltage gate driver circuit according to the present invention.

Fig. 7 is a waveform diagram of the operation of the noise-immune high-voltage gate driving circuit in the presence of noise interference only, wherein dv/dt noise is common-mode noise.

Fig. 8 is a schematic diagram of a prior art interference cancellation level shift circuit.

Detailed Description

The technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

Fig. 2 shows a noise-resistant high-voltage gate driving circuit according to the present invention, which includes a high-voltage level shifting module 1, a common mode noise cancellation circuit 2 composed of a first common mode noise cancellation module CMR1 and a second common mode noise cancellation module CMR2, an SR latch 3, and a driving module 4. The high-voltage gate driving circuit mainly uses narrow pulses to reduce the power consumption of the circuit, and the high-voltage level displacement module 1 comprises two input ends and three output ends and is used for converting two input low-voltage pulse control signals into high-voltage pulse signals and outputting the high-voltage pulse signals together with a high-voltage common-mode signal, so that the signal level is improved through an LDMOS (laterally diffused metal oxide semiconductor) tube; the high-voltage pulse signal passes through a common-mode noise elimination circuit, and the common-mode noise elimination circuit eliminates common-mode noise by utilizing the principle of a differential-mode amplifier; an output signal of the common mode noise elimination circuit enters the driving module through the RS latch, and the driving module outputs a driving signal to control the on-off of the external power tube.

As shown in fig. 3, which is a schematic structural diagram of the high voltage level shift module of the present invention, a circuit for generating a high voltage common mode signal is added on the basis of two circuits of high voltage level shift circuits, and includes a first zener diode D1, a second zener diode D2, a third zener diode D3, a fourth zener diode D4, a fifth zener diode D5, a sixth zener diode D6, a seventh zener diode D7, an eighth zener diode D8, a ninth zener diode D9, a first LDMOS transistor LDM1, a second LDMOS transistor LDM2, a third LDMOS transistor LDM3, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8, a gate terminal of the first LDMOS transistor LDM1 is used as a first input terminal of the high voltage level shift module to be connected to a narrow pulse signal generated by the narrow pulse signal generator, a drain terminal of the high voltage level shift module is used as a first output terminal of the high voltage level shift module to be connected to a first common mode power supply 46r 1 and to be connected to a floating noise elimination module through a first input terminal of, the source end of the resistor is grounded through a sixth resistor R6; a gate end of the third LDMOS transistor LDM3 serving as a second input end of the high-voltage level shift module is connected to a narrow pulse signal generated by a preceding stage circuit, a drain end thereof serving as a second output end of the high-voltage level shift module is connected to a first input end of the second common mode noise cancellation module CMR2 and is connected to the floating power supply VB through the fifth resistor R5, and a source end thereof is grounded through the eighth resistor R8; the gate terminal of the second LDMOS transistor LDM2 is grounded, the drain terminal of the second LDMOS transistor LDM2 serving as the third output terminal of the high-voltage level shift module is connected to the second input terminals of the first common mode noise cancellation module CMR1 and the second common mode noise cancellation module CMR2, and is connected to the floating power supply VB through the fourth resistor R4, and the source terminal of the second LDMOS transistor LDM2 is grounded through the seventh resistor R7; the cathode of the first zener diode D1 is connected to the floating power supply VB, and the anode thereof is connected to the cathode of the second zener diode D2; the cathode of the third zener diode D3 is connected to the anode of the second zener diode D2, and the anode thereof is connected to the drain terminal of the first LDMOS transistor LDM 1; the cathode of the fourth zener diode D4 is connected to the floating power supply VB, and the anode thereof is connected to the cathode of the fifth zener diode D5; the cathode of the sixth zener diode D6 is connected to the anode of the fifth zener diode D5, and the anode thereof is connected to the drain of the second LDMOS transistor LDM 2; the cathode of the seventh zener diode D7 is connected to the floating power supply VB, and the anode thereof is connected to the cathode of the eighth zener diode D8; the cathode of the ninth zener diode D9 is connected to the anode of the eighth zener diode D8, and the anode thereof is connected to the drain of the third LDMOS transistor LDM 3.

The power consumption of the chip is directly determined by the pulse width, so that the input signal of the high-voltage level shift module is controlled by a narrow-band pulse input signal. When the input signal IN1 at the first input terminal of the high voltage level shift module is at a high level, the first LDMOS transistor LDM1 will be triggered to turn on, and the output will generate a low level signal with respect to the floating power supply VB, which is pulled down to (VB-3Vclamp) V, and when the input signal IN1 is at a low level, the first LDMOS transistor LDM1 will turn off, and the output signal level will be equal to the floating power supply VB, where Vclamp is the clamping voltage across the zener diode. Similarly, when the input signal IN2 at the second input terminal of the high voltage level shift module is at a high level, the third LDMOS transistor LDM3 will be triggered to turn on, and the output will generate a low level signal with respect to the floating power supply VB, which is pulled down to (VB-3Vclamp) V, and when the input signal IN2 is at a low level, the third LDMOS transistor LDM3 will turn off, and the output signal level will be equal to the floating power supply VB. The gate terminal of the second LDMOS transistor LDM2 is constantly connected with low level, and the drain terminal thereof outputs V_COMA common mode signal is provided for the common mode noise cancellation circuit.

In the present embodiment, the first common mode noise cancellation module CMR1 and the second common mode noise cancellation module CMR2 have the same internal structure, and the internal circuit structure of the first common mode noise cancellation module CMR1 is taken as an example for explanation, fig. 4 is a schematic diagram of an internal structure of the first common mode noise cancellation module CMR1, which includes a first resistor R1, a second resistor R2, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, and a fifth NMOS transistor MN5, wherein a gate terminal of the first NMOS transistor MN1 is connected to a gate terminal of the first PMOS transistor MP1 and serves as a first input terminal of the first common mode noise cancellation module, the drain terminal of the NMOS transistor is connected to the drain terminal of the first PMOS transistor MP1 and the gate terminal of the second NMOS transistor MN2, the source ends of the NMOS transistors are connected with the source ends of a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4 and a fifth NMOS transistor MN5 and connected with a high-end floating ground VS; the gate end of the second PMOS transistor MP2 is connected to the gate end of the fifth NMOS transistor MN5 and serves as the second input end of the first common mode noise cancellation module, the drain end of the second PMOS transistor MP2 is connected to the drain end of the fifth NMOS transistor MN5 and the gate end of the fourth NMOS transistor MN4, and the source end of the second PMOS transistor MP2 is connected to the source ends of the first PMOS transistor MP1 and the third PMOS transistor MP3 and is connected to the floating power supply VB; one end of the first resistor R1 is connected with a floating power supply VB, and the other end is connected with the drain terminal of the second NMOS transistor MN 2; one end of the second resistor R2 is connected with a floating power supply VB, and the other end is connected with the drain end of the fourth NMOS tube MN4, the gate end of the third NMOS tube MN3 and the gate end of the third PMOS tube MP 3; the drain terminal of the third NMOS transistor MN3 is connected to the drain terminal of the third PMOS transistor MP3 and serves as the output terminal of the first common mode noise cancellation module.

The second NMOS transistor MN2, the fourth NMOS transistor MN4, the first resistor R1, and the second resistor R2 form a differential amplifier for eliminating common mode noise. The first PMOS transistor MP1, the first NMOS transistor MN1, the second PMOS transistor MP2, the fifth NMOS transistor MN5, the third PMOS transistor MP3 and the third NMOS transistor MN3 respectively form inverters for shaping signals. The traditional high-voltage gate driving circuit is provided with the filter circuit behind the high-voltage level shift circuit, so that the narrow pulse signal input by the high-voltage level shift circuit is required to be wider, and the power consumption is higher.

Fig. 5 is a circuit configuration diagram of a driving module used in the embodiment. The circuit is formed by a phase inverter chain, the size of the phase inverter is increased step by step, and the transmission delay of the driving circuit is effectively reduced while the loading capacity of the driving circuit is increased.

Fig. 6 is a timing diagram of the noise-immune high-voltage gate driving circuit according to the present invention. The original input signals are narrow pulse signals In1 and In2, the voltage is boosted by the high-voltage level shifting module, and signals of the common-mode output signal Vcom generated by the high-voltage level shifting module, which are respectively differenced with the output signals Vset and Vrst at the first output end and the second output end are Vcom-Vset and Vcom-Vrst. Signals after common mode noise is removed by the common mode noise elimination circuit are Vset _ and Vrst _, the output after the SR latch is VQ, and the output after the driving module is HO.

Fig. 7 is a waveform diagram illustrating the common mode dv/dt noise in the noise-immune high-voltage gate driving circuit according to the present invention. When the voltage at the VB terminal of the floating power supply rises rapidly, common-mode dv/dt noise is generated, the common-mode noise is effectively inhibited through the use of a differential mode amplifier in the common-mode noise elimination circuit, a noise signal cannot be transmitted continuously, and the normal work of the circuit is ensured.

In summary, the anti-noise high-voltage gate driving circuit provided by the invention has the advantages that the high-voltage level displacement module improves the signal level through the LDMOS transistor, converts two input low-voltage pulse control signals into high-voltage pulse signals, and outputs a high-voltage common-mode signal generated by the additional second LDMOS transistor LDMOS 2 and the high-voltage pulse signals to the common-mode noise elimination circuit together, the common-mode noise elimination circuit utilizes the principle of a differential mode amplifier to compare the high-voltage common-mode signal with the signals output by the first LDMOS transistor ldmo 1 and the second LDMOS transistor ldmo 2 to eliminate noise interference without affecting normal signal transmission, and the RS latch and the driving module convert the narrow pulse signals after noise elimination into output signals again to drive the high-side power transistor. The invention can eliminate various common mode dv/dt interference noises, can be suitable for narrower narrow pulse input signals, and reduces the power consumption of the circuit.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and all simple modifications, changes and equivalent structural changes made to the above embodiment according to the technical spirit of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

1. An anti-noise high-voltage gate drive circuit is characterized by comprising a high-voltage level shift module, a first common-mode noise elimination module, a second common-mode noise elimination module, an RS latch and a drive module,

the input end of the driving module is connected with the output end of the RS latch, and the output end of the driving module is used as the output end of the high-voltage gate driving circuit;

the first common mode noise elimination module and the second common mode noise elimination module have the same structure, the first common mode noise elimination module comprises a first resistor, a second resistor, a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube,