JP5471862B2 - Level shift circuit and switching power supply device - Google Patents

Description

  The present invention relates to a level shift circuit used for an interface between circuits having different power supply voltages and a switching power supply apparatus using the level shift circuit.

  A switching power supply device used for a flat panel display or the like that is particularly demanding to be thin is often a half-bridge type using two switching elements and a current resonance type that can further reduce switching loss. Furthermore, in order to reduce the size and thickness of consumer devices typified by flat panel displays (LCD-TV, etc.) in the future, downsizing of each component by increasing the frequency of the switching power supply is required.

  In the half-bridge configuration, two Nch-type MOSFETs are used, and a level shift circuit that transmits a control signal on the low side to the high side is required. Since the primary side converter input voltage of the consumer switching power supply is an output of a PFC (Power Factor Correction) circuit that complies with the harmonic regulation, it is generally about DC 400V. Also in the level shift circuit, since it is necessary to shift the level by approximately the same voltage from the low side potential to about 400 V, a specific problem occurs, and various countermeasures are being studied.

  FIG. 8 is a diagram showing a configuration example of a current resonance type power supply having a half bridge configuration using a conventional level shift circuit. The level shift circuit is used as a high side driver in the control circuit 2.

  In the power supply device shown in FIG. 8, the control circuit 2 alternately turns on / off the high-side switching element and the low-side switching element and changes the charge / discharge period to the resonance capacitor Ci by controlling the frequency. Controls the amount of power induced on the secondary side.

  Patent Document 1 describes a semiconductor device that protects a switching device by preventing malfunction of a flip-flop circuit due to a dv / dt current. FIG. 9 is a circuit diagram showing a configuration of a semiconductor device including a conventional level shift circuit described in Patent Document 1, and shows a configuration of a general high-side driver circuit HD1. As shown in FIG. 9, this semiconductor device constitutes a half-bridge type power device 19 in which switching elements 17 and 18 such as IGBTs (insulated gate bipolar transistors) are connected in series between a power source and a ground. A load (inductive load such as a motor) 21 is connected to a connection point N1 between the switching element 17 and the switching element 18.

  The high-side switching element 17 is an element that performs a switching operation between the reference potential and a power supply potential (for example, 400 V) supplied from the power supply with the potential at the connection point N1 as a reference potential. On the other hand, the switching element 18 on the low side is an element that performs a switching operation between the reference potential and the potential at the connection point N1 with the ground potential as a reference potential.

  In the high-side driver circuit HD1 as shown in FIG. 9, depending on the switching state of the half-bridge type power device 19, the high-side side using the lines L1 and L1 from the connection point N1 to the anodes of the diodes 8 and 9 as a reference potential. A fast dv / dt transient signal is applied to the circuit. The high breakdown voltage MOSFETs 20 and 30 have a large element region for providing a drain and a breakdown voltage of each part (usually about 700 to 1100 V), and have a parasitic capacitance between the drain and the source, the back gate, the gate, and the sub-substrate.

  If the filter circuit 26 does not exist, the dv / dt current obtained by integrating the parasitic capacitance and the dv / dt transient signal flows through the high side driver circuit HD1 due to the parasitic capacitance existing between the drain and source of the MOSFETs 20 and 30. Since the voltage drop occurs at the resistors 4 and 5 at the same time, the inverters 6 and 7 may be operated to erroneously give the “H (High)” signal to the set input and reset input of the flip-flop circuit 12.

  The high side driver circuit HD1 shown in FIG. 9 includes a filter circuit 26 in front of the input of the flip-flop circuit 12, so that a dv / dt transient signal is applied to the line L1 and the dv / dt current is simultaneously applied to the MOSFETs 20 and 30. The filter circuit 26 prevents the “H” signal output from the inverter circuits 6 and 7 even when a voltage drop occurs simultaneously in the resistors 4 and 5 due to the flow of.

  That is, the filter circuit 26 does not output the “H” signal to the flip-flop circuit 12 until the time according to the time constant of the CR filter that the filter circuit 26 has passes, so the delay time is longer than the application time of the dv / dt transient signal. By setting the length longer, it is possible to prevent the “H” signal due to the dv / dt current from being input to the flip-flop circuit 12 and to prevent malfunction of the flip-flop circuit 12.

  On the other hand, by setting the pulse width of the ON signal and OFF signal output from the pulse generation circuit 10 to be sufficiently longer than the dv / dt transient signal application time, that is, longer than the delay time by the filter circuit 26, the pulse generation circuit The output signals of the inverter circuits 6 and 7 based on the ON signal and the OFF signal output by the signal 10 are supplied to the flip-flop circuit 12 to operate the flip-flop circuit 12 normally.

  FIG. 10 is a timing chart showing the operation of the semiconductor device including the conventional level shift circuit described in Patent Document 1. When the switching element 17 is turned on, the pulse generation circuit 10 outputs an “H” signal as an on signal and an “L (Low)” signal as an off signal. In this case, the output of the on-side CR filter circuit that has received the “H” signal from the inverter circuit 7 gradually rises until the capacitor 25 is filled with electric charge, as shown in FIG. The same applies to the falling. When the output of the on-side CR filter circuit rises, the flip-flop circuit 12 outputs an “H” signal as the Q output.

  When the switching element 17 is turned off, the pulse generation circuit 10 outputs an “L” signal as an on signal and an “H” signal as an off signal. In this case, the output of the off-side CR filter circuit receiving the “H” signal by the inverter circuit 6 gradually rises until the capacitor 24 is charged, as shown in FIG. The same applies to the falling. When the output of the off-side CR filter circuit rises, the flip-flop circuit 12 outputs an “L” signal as the Q output.

  Therefore, the switching element 17 is on during the period when the “H” signal is output from the Q output of the flip-flop circuit 12, and the on-side off-side CR filter circuit as compared with the case where the filter circuit 26 is not provided. The Q output of the flip-flop circuit 12 is turned on / off with a delay corresponding to the delay time.

  Further, as described above, the MOSFETs 20 and 30 need to have the on / off pulse width set longer than the delay time by the filter circuit 26. However, in order to increase the malfunction tolerance, the filter time of the filter circuit 26 is increased. Then, there is a problem of increasing power consumption. Therefore, Patent Document 1 also describes a semiconductor device having a protection circuit that does not cause a delay time by being configured with a logic circuit.

  Patent Document 2 describes a level shift circuit having a capability of eliminating interference against a dv / dt transient phenomenon. This level shift circuit includes a pulse filter circuit, which identifies a pulse generated by a dv / dt transient signal based on the pulse width and selects and passes only a normal operation pulse. A malfunction due to a dv / dt transient signal can be avoided.

  The level shift circuit described in Patent Document 3 includes a reset priority circuit that operates a reset level circuit and turns off a power MOSFET with an input signal lower than a value necessary for operating the set level circuit. That is, this level shift circuit is configured to give priority to reset by increasing the size of the reset voltage drop resistor or by adjusting the input threshold of the circuit that reads the set and reset voltage drop resistors, It is possible to prevent malfunction due to noise pulses.

  The concept of reset priority can also be applied to the level shift circuit shown in FIG. By increasing the resistance 4 on the reset side, the level shift circuit shown in FIG. 9 turns off the switching element 17 on the high side with priority on resetting, thereby preventing the switching elements 17 and 18 from turning on simultaneously.

Japanese Patent Laid-Open No. 9-200017 JP-A-4-230117 JP-A-8-65143

  In the level shift circuit, for example, when the low-side switching element is turned off and the high-side switching element is turned on to change from 0 V to 400 V (or the high-side switching element is turned off and the low-side switching element is turned on. Dv / dt is applied to the level shift circuit in synchronization with on / off of the switching element. In this case, it is necessary to take measures so as not to malfunction due to dv / dt resulting from on / off of the switching element.

  The semiconductor device described in Patent Document 1 prevents malfunction by inserting a protection circuit for the high-side flip-flop when dv / dt becomes high. Therefore, even if a proper signal is transmitted from the low side via the MOSFETs 20 and 30 during the transition time from the low side to the high side during the time when dv / dt becomes high, the protection circuit is operated. There is a problem that the on / off signal cannot be sent to the camera.

  This problem is not likely to be a problem because dv / dt is small in motor applications where the switching frequency is about 20 KHz at the highest using an IGBT or the like as the main switching element. However, when the current resonance switching power supply is increased in frequency (about 500 kHz), it is necessary to increase dv / dt. The on / off cycle for switching becomes short (a cycle of 2 μs at 500 kHz), and the required on time cannot be secured unless dv / dt is made relatively fast (for example, the dv / dt period is long). If it is 0.5 μS, the complete on / off time is half the remaining 1 μS at 500 kHz.) Therefore, since dv / dt has to be increased, the possibility of a problem increases.

  When designing a semiconductor product that clears the above-described problems in the apparatus described in Patent Document 1 (for example, designing a current resonance type IC or the like), when aiming at high frequency, the apparatus is normally assumed. It is necessary to set an appropriate constant so that the protection circuit does not operate during the operation. Specifically, the designer reduces the resistance values of the resistors 4 and 5 shown in FIG. 9 to reduce the voltage drop of the resistors 4 and 5 due to the charging current flowing through the parasitic capacitances of the MOSFETs 20 and 30 by dv / dt. Then, the design is performed so that the detection circuit in the subsequent stage does not operate. Further, the current flowing through the MOSFETs 20 and 30 is increased so that a current necessary for operating the detection circuit at the subsequent stage can be supplied. As this problem, since dv / dt increases as the frequency increases, the resistance values of the resistors 4 and 5 become lower, the current flowing through the MOSFETs 20 and 30 increases, and the current consumption increases. A point is mentioned.

  Further, in the level shift circuit, when the high-side potential VB is low (for example, 10 V or less) and when the high-side reference potential is low, the MOSFETs 20 and 30 are changed from the saturated region to the non-saturated region, so Go down. However, the level shift circuit is required to transmit a signal from the low side to the high side whatever the high side potential is. For this reason, the drain currents of the MOSFETs 20 and 30 are set so that signals can be transmitted even when the high side potential is low, and the resistors 4 and 5 are designed to ensure a sufficient signal. In this case, when the high-side potential is high, the drain current increases, so that power consumption increases. Normally, the drain current of the MOSFETs 20 and 30 when the high-side potential is low (for example, 10 V or less) drops to about 1 to 5 mA, and the drain current of the MOSFETs 20 and 30 when the high-side potential is high (such as 400 V). Increases to about 7 to 30 mA, and when the high-side potential is high, the drain current increases three times or more due to the static characteristics of the MOSFETs 20 and 30.

  The loss of the level shift circuit is 2 × 150 ns × 400 V × 10 mA × 200 kHz = 0.24 W when the gate width of the MOSFETs 20 and 30 is set to 150 ns, the oscillation frequency is set to 200 kHz, and the drain current is set to 10 mA. It is. Since loss increases in proportion to the oscillation frequency, it is necessary to reduce the loss of one pulse in order to increase the frequency. Alternatively, in order to reduce the circuit current, there is a method in which the voltage amplitude is increased by increasing the resistances 4 and 5 in anticipation of when the high-side potential is low (10 V or less). Increases the time constant with respect to the parasitic capacitance, and charging of the parasitic capacitance is not in time when dv / dt is applied, and the inverters 6 and 7 operate to transmit signals to the subsequent stage, causing the flip-flop circuit 12 to malfunction. .

  The present invention prevents a malfunction of the flip-flop circuit due to application of dv / dt, transmits a signal from the low side to the high side even when dv / dt is applied, and reduces power consumption even when the high side potential is low. It is an object of the present invention to provide a level shift circuit that can operate in a wide range and a switching power supply device using the level shift circuit.

  In order to solve the above problems, a level shift circuit according to the present invention has one end connected to a level shift power supply and having a resistance value equal to or higher than a predetermined value, and a drain connected to the other end of the first resistor. A first N-type MOSFET whose source is connected to the ground, a second resistor having the same resistance value as the first resistor, one end connected to the level shift power supply, and the other end of the second resistor And a pulse for controlling on / off of the first N-type MOSFET and the second N-type MOSFET based on an input signal. A first series circuit in which a generation circuit and a semiconductor element that has a non-linear characteristic with a third resistance and is turned on when a dv / dt transient signal of a certain level or more is applied to both ends of the first resistance; The second A second series circuit in which a fourth resistor having the same resistance value as the third resistor and the semiconductor element are connected to both ends of the resistor and a set signal is generated when the first N-type MOSFET is on A reset signal is generated when the second N-type MOSFET is on, and a voltage difference is generated between the potential at the drain of the first N-type MOSFET and the potential at the drain of the second N-type MOSFET. A control unit that does not generate any of the set signal and the reset signal, and an output obtained by level-shifting the input signal based on the set signal and the reset signal generated by the control unit. And a flip-flop for outputting a signal.

  In order to solve the above problems, a switching power supply according to the present invention is a switching power supply device having a high-side switching element and a low-side switching element, and as a circuit for controlling the high-side switching element. A level shift circuit according to any one of claims 1 to 6 is used.

  According to the present invention, the malfunction of the flip-flop circuit due to the application of dv / dt is prevented, the signal is transmitted from the low side to the high side even when dv / dt is applied, and the power consumption is low even when the voltage on the high side is low. A level shift circuit and a switching power supply device that can operate over a wide range with electric power can be provided.

It is a circuit diagram which shows the structure of the level shift circuit of the form of Example 1 of this invention. It is a circuit diagram which shows the structure of the switching power supply device of the form of Example 1 of this invention. It is a timing chart which shows operation | movement of the level shift circuit of the form of Example 1 of this invention. It is another example of the timing chart which shows operation | movement of the level shift circuit of the form of Example 1 of this invention. It is another example of the timing chart which shows operation | movement of the level shift circuit of the form of Example 1 of this invention. It is a circuit diagram which shows the structure of the level shift circuit of the form of Example 2 of this invention. It is a circuit diagram which shows the structure of the level shift circuit of the modification of the form of Example 1 and Example 2 of this invention. It is a figure which shows the structural example of the current resonance type | mold power supply of a half bridge structure using the conventional level shift circuit. It is a circuit diagram which shows the structure of the semiconductor device containing the conventional level shift circuit. It is a timing chart which shows operation | movement of the semiconductor device containing the conventional level shift circuit.

  Embodiments of a level shift circuit and a switching power supply apparatus according to the present invention will be described below in detail with reference to the drawings.

  Embodiments of the present invention will be described below with reference to the drawings. First, the configuration of the present embodiment will be described. 1 is a circuit diagram showing a configuration of a level shift circuit according to a first embodiment of the present invention. As shown in FIG. 1, the level shift circuit includes resistors R1 to R6, R9, and R10, a pulse generation circuit 10, transistors MN1, MN2, MN3, and MN4, a flip-flop 12, and diodes D1 to D6. I have. That is, in the level shift circuit of this embodiment, the filter circuit 26 is deleted from the conventional level shift circuit shown in FIG. 9, and resistors R5, R6, R9, R10, transistors MN1, MN2, and diodes D1-D6 are added.

  FIG. 2 is a circuit diagram illustrating a configuration of the switching power supply device according to the first embodiment of the present invention. As shown in FIG. 2, this switching power supply device is a current resonance type switching power supply device having a high-side switching element 17a and a low-side switching element 18a having a half bridge configuration, and controls the high-side switching element 17a. For this purpose, a level shift circuit in the control circuit 2 is used. However, the application of the present invention does not necessarily require a half-bridge configuration, and can also be applied to a switching power supply device having a full-bridge configuration.

  In the switching power supply device shown in FIG. 2, the control circuit 2 changes the charging / discharging period of the resonant capacitor Ci by alternately turning on / off the high-side switching element 17a and the low-side switching element 18a and controlling the frequency. And control the amount of power induced on the secondary side of the transformer.

  As shown in FIG. 2, the midpoint voltage (level shift reference potential) is a potential on a line connected to the source of the high-side switching element 17a and the drain of the low-side switching element 18a. On the other hand, it has a predetermined voltage difference. In this embodiment, the voltage difference between the level shift power supply VB (high side power supply) and the level shift reference potential VS (high side reference potential) is about 10V.

  The resistor R1 in FIG. 1 corresponds to the first resistor of the present invention, and has one end connected to the level shift power supply and the other end connected to the drain of the transistor MN3.

  The transistor MN3 corresponds to the first N-type MOSFET of the present invention, the drain is connected to the other end of the resistor R1, and the source is connected to the ground. However, in the present embodiment, the source of the transistor MN3 is connected to the ground via the resistor R3. That is, the resistor R3 corresponds to the ninth resistor of the present invention and is connected between the source of the transistor MN3 and the ground. Further, a parasitic capacitance C1 exists between the drain of the transistor MN3 and the ground. The gate of the transistor MN3 is connected to the pulse generation circuit 10.

  The resistor R2 corresponds to the second resistor of the present invention, has the same resistance value as the resistor R1, has one end connected to the level shift power source and the other end connected to the drain of the transistor MN4. The resistors R1 and R2 have a predetermined resistance value of 1 kΩ or more, have a resistance value of about 1 kΩ to 10 kΩ, and are, for example, 5 kΩ.

  The transistor MN4 corresponds to the second N-type MOSFET of the present invention, the drain is connected to the other end of the resistor R2, and the source is connected to the ground. However, in the present embodiment, the source of the transistor MN4 is connected to the ground via the resistor R4. That is, the resistor R4 corresponds to the tenth resistor of the present invention and is connected between the source of the transistor MN4 and the ground. Further, a parasitic capacitance C2 exists between the drain of the transistor MN4 and the ground. The gate of the transistor MN4 is connected to the pulse generation circuit 10.

  The pulse generation circuit 10 controls on / off of the transistors MN3 and MN4 based on the input signal. Specifically, the pulse generation circuit 10 outputs a set pulse signal to the gate of the transistor MN3 when the input signal rises, as depicted below the pulse generation circuit 10 in FIG. The pulse generation circuit 10 outputs a reset pulse signal to the gate of the transistor MN4 when the input signal falls.

  Note that the gate drive pulses of the transistors MN3 and MN4 are, for example, about 50 nS to 200 nS.

  The resistors R5 and R6 and the transistors MN1 and MN2 correspond to the control unit of the present invention. The control unit including the resistors R5 and R6 and the transistors MN1 and MN2 generates a set signal when the transistor MN3 is on, generates a reset signal when the transistor MN4 is on, and generates a reset signal at the drain of the transistor MN3. If there is no voltage difference between the potential and the potential at the drain of transistor MN4, no signal is generated.

  The resistor R5 corresponds to the fifth resistor of the present invention, and has one end connected to the level shift power supply and the other end connected to the drain of the transistor MN1.

  The transistor MN1 corresponds to the third N-type MOSFET of the present invention, the drain is connected to the other end of the resistor R5 and the set terminal of the flip-flop 12, the source is connected to the drain of the transistor MN3, and the gate is the transistor MN4. Connected to the drain. Note that the drain of the transistor MN1 of this embodiment is connected to the set terminal of the flip-flop 12 through an inverter.

  The resistor R6 corresponds to the sixth resistor of the present invention, has the same resistance value as the resistor R5, one end is connected to the level shift power supply, and the other end is connected to the drain of the transistor MN2. The resistors R5 and R6 have a resistance value that is about 2 to 20 times that of the resistors R1 and R2, for example.

  The transistor MN2 corresponds to the fourth N-type MOSFET of the present invention, the drain is connected to the other end of the resistor R6 and the reset terminal of the flip-flop 12, the source is connected to the drain of the transistor MN4, and the gate is the transistor MN3. Connected to the drain. Note that the drain of the transistor MN2 of this embodiment is connected to the reset terminal of the flip-flop 12 through an inverter.

  The threshold of the detection inverter circuit connected to the resistors R5 and R6 is 50% (between 20% and 80%) of the voltage difference between the level shift power supply and the level shift reference potential.

  The flip-flop 12 outputs an output signal obtained by level-shifting the input signal based on the set signal and reset signal generated by the control unit. In the present embodiment, the output signal from the flip-flop 12 is applied to the gate of the high-side switching element 17a shown in FIG.

  A first series circuit in which diodes D3 to D6 connected in series and a resistor R9 are connected in series is connected to both ends of the resistor R1. The anode of the diode D3 is connected to one ends of the resistors R1 and R2, and one end of the resistor R9 is connected to the other end of the resistor R1, the source of the transistor MN1, the drain of the transistor MN3, the gate of the transistor MN2, and the cathode of the diode D2. ing.

  A second series circuit in which diodes D3 to D6 connected in series and a resistor R10 are connected in series is connected to both ends of the resistor R2. One end of the resistor R10 is connected to the other end of the resistor R2, the source of the transistor MN2, the drain of the transistor MN4, the gate of the transistor MN1, and the cathode of the diode D1.

  The diodes D3 to D6 are semiconductor elements having nonlinear characteristics, and are turned on when a dv / dt transient signal of a certain value or more is applied. The resistor R9 corresponds to the third resistor of the present invention and is, for example, 5 kΩ. The resistor R10 corresponds to the fourth resistor of the present invention, has the same resistance value as that of the resistor R9, and is 5 kΩ, for example.

  Next, the operation of the present embodiment configured as described above will be described. The level shift circuit of this embodiment is roughly divided into four operations, and will be described separately.

  First, the malfunction tolerance when dv / dt is applied to the level shift circuit will be described (operation 1). FIG. 3 is a timing chart showing the operation of the level shift circuit of this embodiment, and assumes a current resonance type switching power supply device as shown in FIG. In FIG. 3, LO is a voltage applied to the gate of the low-side switching element 18a, and HO is a voltage applied to the gate of the high-side switching element 17a.

  When the low-side switching element 18a is turned off at time t1, the midpoint voltage changes from 0 V to 400 V (dv / dt is applied) from time t1 to time t2 due to the influence of the resonance circuit. Since the high-side switching element 17a is turned on at the time t2 when the midpoint voltage has fully increased, the voltage between the switch terminals of the high-side switching element 17a is almost 0 V, and the switching power supply shown in FIG. Switching), which is effective in reducing switching cross (= improvement of power supply efficiency) and noise.

  When dv / dt is applied, the current for charging the parasitic capacitances C1 and C2 flows through the resistors R1 and R2 in accordance with dv / dt, so that a voltage drop occurs across the resistors R1 and R2. In this case, since the voltage drop amounts in the resistors R1 and R2 are the same, there is no voltage difference between the potential at the drain of the transistor MN3 and the potential at the drain of the transistor MN4. Therefore, the transistors MN1 and MN2 have their gate-source voltages of about 0 V, so that the transistors MN1 and MN2 are kept off, and no voltage drop occurs across the resistors R5 and R6. As a result, the control unit including the resistors R5 and R6 and the transistors MN1 and MN2 does not output a signal to the subsequent inverter and the flip-flop 12, and thus does not cause a malfunction due to dv / dt.

  In the cited example of Patent Document 1, since the current for charging the parasitic capacitances C1 and C2 flows through the resistors 4 and 5 according to dv / dt when dv / dt is applied, a voltage drop occurs at both ends of the resistors 4 and 5. To do. When this voltage drop reaches the thresholds of the inverters 6 and 7, a signal is transmitted to the subsequent stage, and the filter circuit 26 cuts off the signal, but the pulse of the on signal off signal output from the pulse generation circuit 10 is longer than the delay time. Since the width is made sufficiently long, a problem of increased power consumption occurs, and if a noise signal exceeding the processing capability of the filter circuit 26 is input, an error signal is transmitted to the flip-flop 12 and operation becomes unstable. It may cause malfunction. The same applies to Patent Document 2.

  Next, the operation at the time of transmitting the set pulse and the reset pulse will be described (operation 2). However, the operation at the time of transmitting the set pulse and the operation at the time of transmitting the reset pulse are not different in the operation itself only by using different transistors and resistances. Therefore, only the operation at the time of transmitting the set pulse is described here.

  At time t2 in FIG. 3, when the pulse generation circuit 10 outputs a set pulse signal to the gate of the transistor MN3, the transistor MN3 is turned on to pass a current through the resistor R1. As a result, a voltage difference is generated between both ends of the resistor R1, and when the source voltage of the transistor MN1 decreases and the gate-source voltage becomes equal to or higher than the threshold, the transistor MN1 is turned on to pass a current through the resistor R5. When the voltage drop generated across the resistor R5 reaches the threshold in the subsequent inverter, the set signal is input to the flip-flop 12, and the flip-flop 12 receives a signal of H (HIGH) level at the gate of the high-side switching element 17a. Is output to turn on the switching element 17a.

  Next, an operation at the time of applying dv / dt and transmitting a signal from the low side to the high side will be described (operation 3). FIG. 4 is another example of a timing chart showing the operation of the level shift circuit of this embodiment, and assumes a current resonance type switching power supply device as shown in FIG.

  When the low-side switching element 18a is turned off at time t1, the midpoint voltage rises from 0V (dv / dt is applied) due to the influence of the resonance circuit. When dv / dt is applied, the current for charging the parasitic capacitances C1 and C2 flows through the resistors R1 and R2 in accordance with dv / dt, so that a voltage drop occurs across the resistors R1 and R2. In this case, since the voltage drop amounts in the resistors R1 and R2 are the same, there is no voltage difference between the potential at the drain of the transistor MN3 and the potential at the drain of the transistor MN4. Therefore, the transistors MN1 and MN2 maintain the OFF state because the gate-source voltage in each transistor is about 0 V, and no voltage drop is generated across the resistors R5 and R6, so that no signal is transmitted to the subsequent stage.

  At this time, there are the following problems. That is, a voltage drop occurs in the resistor R1 and the resistor R2, and this voltage drop is ((VB-VS) + (forward voltage VF of D1 or D2) + (threshold value Vth of MN1 or MN2)). -(The overdrive voltage of MN1 or MN2 where a signal is transmitted to the subsequent stage of MN1 or MN2) and below, it is abbreviated as a critical drop voltage.) Do not turn on. For this reason, a signal cannot be transmitted to the flip-flop 12.

  However, in the first embodiment, when the dv / dt transient signal is applied and the level shift reference potential VS rises at high speed, the voltage across the resistors R1 and R2 rises due to the current charged in the parasitic capacitors C1 and C2. At this time, the diodes D3 to D6 are turned on, and a current flows through the resistors R9 and R10. In this case, since the resistor R9 is connected in parallel to the resistor R1, and the resistor R10 is connected in parallel to the resistor R2, the voltage across the resistors R1 and R2 is adjusted so that it does not reach the limit voltage drop. Can do.

  If the voltage across the resistors R1 and R2 does not reach the limit drop voltage, the transistor MN1 (when set) or the transistor MN2 (when reset) is turned on, and even when dv / dt is applied, a signal is sent from the low side to the high side. Can communicate.

  Although the load resistance is lowered by the resistors R9 and R10, the drain currents of the transistors MN3 and MN4 increase several times because the voltages at both ends increase and transition from the unsaturated region to the saturated region. For this reason, the signal amplitude on the high side can be sufficiently obtained.

  On the other hand, in Patent Document 1, when a set signal is input while the flip-flop is off, the set signal is not input to the flip-flop circuit by the protection circuit and is not output to the high side. If the resistances 4 and 5 are small, the protection circuit does not operate, so that signal transmission is possible if a set signal is input. However, if the resistance values of the resistances 4 and 5 are small, power consumption increases. End up.

  In Patent Document 2, since an erroneous signal at the time of applying dv / dt is filtered, the set signal is also filtered, so that signal transmission cannot be performed. In Patent Document 3, if a set signal is input when dv / dt is applied, both the set signal and the reset signal are applied to the flip-flop, and the operation of the flip-flop has a reset priority, so the set signal is not accepted. Note that if the resistors 4 and 5 are small, the inverter 6 does not operate, so that signal transmission is possible if a set signal is input. However, if the resistance values of the resistors 4 and 5 are reduced, power consumption increases. .

  Next, an operation for transmitting a signal when the voltage applied to the level shift circuit is low will be described (operation 4).

  Basically, it is the same as the operation 2 described above, but the resistors R1 and R2 are set larger than the resistance values of Patent Documents 1 to 3. When the level shift power supply VS potential is low (for example, 10 V or less), the current values of the transistors MN3 and MN4 decrease. Therefore, by increasing the resistance values of the resistors R1 and R2 to 5 kΩ, for example, The signal can be increased.

  Thus, since the signal is transmitted to the flip-flop, the signal can be transmitted even if the voltage applied to the level shift circuit is lower than that of the conventional circuit. When the level shift power supply VB potential is low and dv / dt is not applied, the impedance is increased by disconnecting the resistor R9 (R10) from the resistor R1 (R2) while the diodes D3 to D6 are off. Can do.

  Thus, even if the resistances R1 and R2 are made larger than the resistance values of Patent Documents 1 to 3, the flip-flop 12 does not malfunction, and a signal can be transmitted even at dv / dt. Therefore, the voltage applied to the level shift circuit Even if it is low, it can operate in a wider range. In particular, the level shift side reference potential VS becomes a negative potential due to the stray inductance and the resonance operation of the resonance circuit (Lr, Cv, Ci) during switching, and at the same time, even when the level shift power supply is lowered, the signal is in a wider range than before. Can be transmitted. Note that in the operation range up to the same level as the operation range of the prior art, the drain currents of the transistors MN3 and MN4 can be reduced, so that the power consumption can be reduced and the speed can be increased.

  As described above, according to the level shift circuit and the switching power supply device using the level shift circuit according to the first embodiment of the present invention, the load impedance is set by turning on the diodes D3 to D6 when dv / dt is applied. By lowering to an appropriate value, a signal can be transmitted from the low side to the high side. In this case, the transistors MN3 and MN4 enter the saturation region from the non-saturation region, the current increases, the impedance is lowered, and the signal amplitude on the high side is sufficiently secured, so that the signal can be transmitted. In addition, when the voltage applied to the high side is low, the impedance can be increased by increasing the resistances R1 and R2, and the operation can be performed up to a lower voltage.

  Therefore, the malfunction of the flip-flop circuit due to the application of dv / dt is prevented, the signal is transmitted from the low side to the high side even when dv / dt is applied, and a wide range is achieved with low power consumption even when the voltage on the high side is low. A level shift circuit and a switching power supply device that can operate in the above manner can be provided.

  Furthermore, the level shift circuit of the embodiment can limit the current that flows when the transistors MN3 and MN4 are turned on by providing the resistors R3 and R4. More specifically, the source current of the transistor MN3 (MN4) causes a voltage drop across the resistor R3 (R4). Since the pulse signal output from the pulse generation circuit 10 has a constant voltage value, the gate-source voltage of the transistor MN3 (MN4) is reduced by the voltage drop of the resistor R3 (R4), so that the source current is constant. Equilibrium at the current value of. Therefore, the level shift circuit according to this embodiment includes the resistor R3 (R4), so that the drain current flowing through the transistor MN3 (MN4) can be driven with a constant current.

  FIG. 5 is a timing chart showing the operation of the level shift circuit of this embodiment when an optimum design for increasing the frequency is performed, and assumes a current resonance type switching power supply device as shown in FIG. It is a thing.

  Usually, a dead time circuit is provided in the ON signal on the high side and the low side to prevent simultaneous ON. This dead time circuit can usually be set to an arbitrary value by a resistor or the like. The dv / dt time is determined to some extent by the resonance circuit and the load current. Here, the application circuit that has been optimally designed is that the dead time is adjusted by resistance or the like, signal transmission is started from the low side to the high side during dv / dt time, and the high side is determined by the transmission delay time. The side is turned on and the end of the dv / dt application time is set almost simultaneously (actually, a slight margin is set and the turn-on is slightly delayed).

  In FIG. 5, the dead time is from time t1 to t3, and both the high-side switching element 17a and the low-side switching element 18a shown in FIG. 2 are in an off state. Ideally, when the voltage (HO) applied to the gate of the high-side switching element 17a becomes H level at time t3 when the rise of the midpoint voltage ends, the maximum time that the high-side switching element 17a can be turned on. Therefore, the utilization factor of the high-side switching element 17a is maximized.

  In the waveforms described with reference to FIGS. 3 and 4, it is described that the set pulse signal is output from the pulse generation circuit 10 and the HO is at the H level by the flip-flop 12. 5 takes into account the delay time. That is, in an actual circuit, there is a circuit delay time that cannot be ignored until the set pulse signal (MN3Gate) is output by the pulse generation circuit 10 and the HO terminal becomes High. Therefore, in order to set HO to H level at time t3, it is necessary for the pulse generation circuit 10 to output a set pulse signal in a state where dv / dt is applied to the midpoint voltage. Signal transmission from the circuit to the high-side control circuit is required.

  Therefore, the level shift circuit of the present embodiment realizes the ideal operation described above because even when dv / dt is applied, the voltage balance between the drain of the transistor MN3 and the drain of the transistor MN4 is lost. It becomes possible to do. That is, since the high-side switching element 17a is turned on at the same time as the application of dv / dt is finished, the switching element can be maximized in on time and ZVS can be performed.

  FIG. 6 is a circuit diagram showing the configuration of the level shift circuit according to the second embodiment of the present invention. A difference from the configuration of the level shift circuit of the first embodiment shown in FIG. 1 is that a buffer unit 14 and a filter unit 16 are newly provided. The level shift circuit in this embodiment is assumed to be used in the switching power supply device shown in FIG.

  The buffer unit 14 includes a transistor MP1, a transistor MP2, a resistor R7, and a resistor R8.

  The transistor MP2 and the resistor R8 correspond to the first signal amplifying unit of the present invention, and are provided between the control unit and the flip-flop 12, and the set signal generated by the control unit is detected by the flip-flop 12. Amplify to.

  Here, the transistor MP2 corresponds to the first P-type MOSFET of the present invention, the source is connected to the level shift power supply and the gate is connected to the resistor R5, and is turned on based on the set signal generated by the control unit. / Performs an off operation. The resistor R8 corresponds to the seventh resistor of the present invention, and has one end connected to the drain of the transistor MP2 and the other end connected to the level shift reference potential.

  That is, the first signal amplifying unit includes the transistor MP2 and the resistor R8 connected in series between the level shift power supply and the level shift reference potential having a predetermined voltage difference with respect to the level shift power supply.

  The transistor MP1 and the resistor R7 correspond to the second signal amplification unit of the present invention, and are provided between the control unit and the flip-flop 12. The reset signal generated by the control unit is detected by the flip-flop 12. Amplify to a certain extent.

  Here, the transistor MP1 corresponds to the second P-type MOSFET of the present invention, the source is connected to the level shift power supply and the gate is connected to the resistor R6, and is turned on based on the reset signal generated by the control unit. / Performs an off operation. The resistor R7 corresponds to the eighth resistor of the present invention, and has one end connected to the drain of the transistor MP1 and the other end connected to the level shift reference potential.

  That is, the second signal amplifying unit includes the transistor MP1 and the resistor R7 connected in series between the level shift power supply and the level shift reference potential having a predetermined voltage difference with respect to the level shift power supply.

  The filter unit 16 performs filtering on the set signal and the reset signal amplified by the buffer unit 14 and outputs the filtered signal to the flip-flop 12. The filter unit 16 is provided to further improve noise tolerance, but is not an essential configuration. However, an inverter or buffer for converting an analog signal into a digital signal is necessary.

  The diodes D1 and D2 function as a protection circuit for the transistors MN1 and MN2, and prevent a voltage from being applied beyond the breakdown voltage of the transistors MN1 and MN2 even when the transistors MN3 and MN4 are operating. .

  Other configurations are the same as those of the first embodiment, and redundant description is omitted.

  Next, the operation of the present embodiment configured as described above will be described. First, the problems of the conventional circuit will be described. The conventional level shift circuit shown in FIG. The voltage converted by 7 is detected. The detection threshold in the inverters 6 and 7 at that time is normally set with respect to the level shift reference potential (line L1 in FIG. 9). Therefore, when the level shift reference potential falls below the ground potential which is the reference potential on the low side due to the stray inductance of the load 21 and the resonance operation of the resonance circuit (Lr, Cv, Ci) during switching (for example, −3 V) In the conventional level shift circuit, even when the MOSFETs 20 and 30 are turned on when transmitting a signal from the low side to the high side, the potential does not drop to the detection potential of the inverters 6 and 7, and the signal is transmitted to the subsequent stage of the inverters 6 and 7. It may not be possible.

  On the other hand, since the level shift circuit of the present embodiment includes the buffer unit 14, the signal generated by the control unit is amplified by the transistors MP1 and MP2, and the resistors R7, R7, Even if the detection voltage is obtained using R8 and the level shift reference potential is lower than the low-side reference potential, an appropriate operation is possible, and the operation range can be expanded as compared with the conventional case.

  That is, the resistors R8 and R7 have a role of shifting the set signal and the reset signal to the level shift reference potential side so as to be reliably detected by the subsequent inverter.

  Other operations are the same as those in the first embodiment, and redundant description is omitted.

  As described above, according to the level shift circuit and the switching power supply using the level shift circuit according to the second embodiment of the present invention, in addition to the effects of the first embodiment, the level shift reference potential is the low-side reference potential. Even if the voltage drops to a negative potential, the set signal and the reset signal can be appropriately detected, and the signal can be reliably transmitted from the low side to the high side.

  The level shift reference potential may be overshooted and lowered to a negative potential when the high-side switching element 17a is turned off and the voltage drops from around 400V to 0V. It can be said that the level shift circuit of this embodiment has a high characteristic improvement effect.

(Modification)
FIG. 7 is a circuit diagram showing a configuration of a level shift circuit according to a modification of the first and second embodiments of the present invention. In the level shift circuits of the first and second embodiments shown in FIGS. 1 and 6, diodes D3 to D6 are used as nonlinear elements between the points P1 and P2, but instead of the diodes D3 to D6, for example, A Zener diode shown in FIG. 7A may be used. The breakdown voltage of this one Zener diode may be about the same as the sum of the forward voltages VF of the diodes D3 to D6. By using this Zener diode, it becomes cheaper.

  Instead of the diodes D3 to D6, a series circuit of a transistor MP3 made of a P-type MOSFET shown in FIG. 7B and a resistor R11 and a resistor R12 may be provided between the points P1 and P2. . In this case, the drain of the transistor MP3 is connected to one end of the resistor R11, the source is connected to one end of the resistor R12, and the connection point between the other end of the resistor R11 and the other end of the resistor R12 is connected to the gate. The resistor R11 is, for example, 30 kΩ, and the resistor R12 is, for example, a high resistance of 60 kΩ. What is necessary is just to let an electric current flow into transistor MP3 from the arbitrary operating points by resistance R11 and resistance R12.

  Thus, even if the configuration shown in FIGS. 7A and 7B is used, the operations and effects of the first and second embodiments can be obtained.

  The level shift circuit according to the present invention can be used for a level shift circuit and a switching power supply used for an interface between circuits having different power supply voltages.

DESCRIPTION OF SYMBOLS 1 Full wave rectifier circuit 2 Control circuit 3 Error amplifier 4, 5 Resistor 6, 7, 11 Inverter circuit 8, 9, D1-D6 Diode 10 Pulse generation circuit 12 Flip-flop 14 Buffer part 16 Filter part 17, 17a High side switching Element 18, 18a Low side switching element 19 Half-bridge type power device 20, 30 MOSFET
21 Load 22, 23 Resistor 24, 25 Capacitor 26 Filter circuit 31 High potential side power supply C1, C2 Parasitic capacitance Ci Resonance capacitor HD1 High side driver circuit L1 Line Lr Resonance reactor MN1, MN2, MN3, MN4, MP1, MP2, MP3 Transistor ZD Zener diode P Primary winding R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12 Resistors S1, S2 Secondary winding

Claims (7)

A first resistor having one end connected to the level shift power supply and having a resistance value equal to or greater than a predetermined value;
A first N-type MOSFET having a drain connected to the other end of the first resistor and a source connected to the ground;
A second resistor having the same resistance value as the first resistor and having one end connected to the level shift power supply;
A second N-type MOSFET having a drain connected to the other end of the second resistor and a source connected to the ground;
A pulse generation circuit for controlling on / off of the first N-type MOSFET and the second N-type MOSFET based on an input signal;
A first series circuit in which a semiconductor element that has a non-linear characteristic and a non-linear characteristic and is turned on when a dv / dt transient signal of a certain level or more is applied to both ends of the first resistor;
A second series circuit in which a fourth resistor having the same resistance value as the third resistor and the semiconductor element are connected to both ends of the second resistor;
A set signal is generated when the first N-type MOSFET is on, a reset signal is generated when the second N-type MOSFET is on, and the potential at the drain of the first N-type MOSFET is A control unit that does not generate any of the set signal and the reset signal when there is no voltage difference with the potential at the drain of the second N-type MOSFET;
A flip-flop that outputs an output signal obtained by level-shifting the input signal based on a set signal and a reset signal generated by the control unit;
A level shift circuit comprising: A first signal amplifying unit, which is provided between the control unit and the flip-flop, and amplifies the set signal generated by the control unit to the extent detected by the flip-flop;
A second signal amplifying unit provided between the control unit and the flip-flop, and amplifies a reset signal generated by the control unit to an extent detected by the flip-flop;
The level shift circuit according to claim 1, further comprising: The controller is
A fifth resistor having one end connected to the level shift power supply;
The drain is connected to the other end of the fifth resistor and the set terminal of the flip-flop, the source is connected to the drain of the first N-type MOSFET and one end of the first series circuit, and the gate is the second. A third N-type MOSFET connected to the drain of the N-type MOSFET;
A sixth resistor having the same resistance value as the fifth resistor and having one end connected to a level shift power supply;
The drain is connected to the other end of the sixth resistor and the reset terminal of the flip-flop, the source is connected to the drain of the second N-type MOSFET and one end of the second series circuit, and the gate is the first. A fourth N-type MOSFET connected to the drain of the N-type MOSFET,
The level shift circuit according to claim 1 or 2, characterized by comprising: The first signal amplifying unit includes a first P-type MOSFET and a seventh resistor connected in series between the level shift power source and a level shift reference potential having a predetermined voltage difference with respect to the level shift power source. And consist of
The second signal amplification unit includes a second P-type MOSFET and an eighth resistor connected in series between the level shift power supply and the level shift reference potential.
The first P-type MOSFET performs an on / off operation based on a set signal generated by the control unit,
4. The level shift circuit according to claim 1, wherein the second P-type MOSFET performs an on / off operation based on a reset signal generated by the control unit. 5. A ninth resistor connected between the source of the first N-type MOSFET and the ground;
A tenth resistor connected between the source of the second N-type MOSFET and the ground;
The level shift circuit according to claim 1, further comprising:   The level shift circuit according to claim 1, wherein the semiconductor element is a diode. In a switching power supply device having a high-side switching element and a low-side switching element,
7. A switching power supply apparatus using the level shift circuit according to claim 1 as a circuit for controlling the high-side switching element.

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