JP2016197935A - Switching power supply circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching power supply circuit capable of making the rise of a gate voltage of an FET switching element gentler, at the time of surge voltage input during burst oscillation of a switching power supply.SOLUTION: A drive circuit 5 includes: a negative voltage generation circuit 6 operating to include a negative voltage by shifting a square voltage to the negative side, so as to turn off an FET switching element 3 by applying a negative voltage to a gate voltage of the FET switching element 3; a protection circuit 7 disposed between the negative voltage generation circuit 6 and a gate G of the FET switching element 3, and applying a voltage of square wave including a negative voltage to the gate voltage of the FET switching element 3, by operating the negative voltage generation circuit 6 so as not to be affected by a parasitic diode Dp of the FET switching element 3; and a protection forcible operation circuit 9 for operating the protection circuit 7 forcibly, in the idle period of burst oscillation.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a switching power supply circuit that converts DC power of a DC power supply into DC power of a predetermined voltage by using an FET switching element, and a bridge type DC-DC converter including the same.

  For example, in a synchronous rectification application of a switching power supply circuit using an FET switching element having a parasitic diode such as a MOS-FET, a reverse current (through current) is prevented from flowing in the forward direction of the parasitic diode. The recovery time (Trr) is required to be fast, and the timing for turning on and off the FET switching element is important. Conventionally, as an example of this, a switching power supply circuit that improves the power conversion efficiency by optimally controlling the off-timing of the MOS-FET with a square-wave voltage by driving a drive circuit is known (for example, Patent Documents). 1).

  There is also known a power conversion device in which two such switching power supply circuits are connected in parallel and used as a bridge type DC-DC converter to convert DC power of a predetermined voltage into commercial AC power by an inverter. .

JP 2011-72160 A

  By the way, in order to improve the power conversion efficiency by increasing the switching speed of the FET switching element, or to sufficiently reduce the noise caused by the reverse recovery time (Trr) when the FET switching element is OFF, etc. A negative voltage generation circuit is provided that operates so as to include a negative voltage by shifting the square wave voltage to the negative side by driving the circuit, and applying the negative voltage to the gate voltage of the MOS-FET to turn off the MOS-FET Is assumed. This negative voltage generation circuit is configured, for example, by connecting a Zener diode ZD1 and a capacitor C1 in parallel.

  In this case, for the operation of the circuit, it is necessary to satisfy the capacitance of the capacitor C1 >> the input capacitance Ciss (Cgs) of the MOS-FET. When the MOS-FET is on, the input capacitance Ciss of the MOS-FET is almost equal to the power supply voltage. It is charged until. At this time, the capacitor C1 is hardly charged. As a result, when the MOS-FET is off, a negative voltage is hardly applied between the gate and the source.

  Then, the negative voltage generation circuit does not work sufficiently, and it becomes difficult to improve the intended power conversion efficiency and prevent malfunction due to noise. Further, even if an FET switching element having a high switching speed is used, the power conversion efficiency is improved, but there is a problem that noise is easily generated.

  Furthermore, when a bridge type is formed with two MOS-FETs, noise is applied to the gate voltage of the MOS-FET when the switching power supply is activated or when a surge voltage is input during burst oscillation, and the two MOS-FETs are At the same time, it may be turned on, and the reverse current may damage the MOS-FET. In addition, when the rise of the gate voltage of the MOS-FET is steep, there is a problem that LC resonance occurs due to the junction capacitance of the parasitic diode and the circuit wiring.

  The present invention solves the above-described problems, prevents malfunction due to noise with a simple configuration, and moderates the rise of the gate voltage of the FET switching element when a surge voltage is input during burst oscillation of the switching power supply. An object of the present invention is to provide a switching power supply circuit capable of preventing the occurrence of resonance, and a bridge type DC-DC converter including the same.

  In order to achieve the above object, a switching power supply circuit according to one configuration of the present invention is configured to control a DC power of a DC power supply by turning on and off a FET switching element with a square wave voltage by driving a drive circuit. The direct current power is output. The drive circuit operates so as to include a negative voltage by shifting the square wave voltage to the negative side so that a negative voltage is applied to the gate voltage of the FET switching element to turn off the FET switching element. And the negative voltage generation circuit is arranged between the negative voltage generation circuit and the gate of the FET switching element, operates the negative voltage generation circuit so as not to be affected by the parasitic diode of the FET switching element, and generates a square wave including the negative voltage. A protection circuit that applies a voltage to the gate voltage of the FET switching element, and a burst oscillation circuit that intermittently oscillates the gate control signal of the FET switching element so as to suppress an increase in the output voltage of the switching power supply circuit; A protection forcible operation circuit for forcibly operating the protection circuit within a burst oscillation pause period; Eteiru. Here, the FET switching element refers to a switching element including a MOS-FET, an IGBT element having a part of the FET, and the like.

  According to this configuration, the negative voltage generating circuit is operated so as to include the negative voltage in the square wave without being affected by the parasitic diode of the FET switching element, and the square wave voltage including the negative voltage is applied to the gate of the FET switching element. The protection circuit that is applied to the voltage is forcibly operated during the burst oscillation pause period, so it is possible to prevent malfunction due to noise with a simple configuration, and at the time of burst oscillation of the switching power supply. When the surge voltage is input, the rise of the gate voltage of the FET switching element can be moderated to prevent the occurrence of resonance.

  Preferably, the FET switching element is a MOS-FET, and the protection circuit is provided between a gate and a source of the MOS-FET, and a diode, a resistor and a capacitor connected in parallel are connected in series. The time constant of the resistance and capacitor of the protection circuit is increased so as to moderate the rise of the gate voltage of the MOS-FET, and the protection forcible operation circuit is within the burst oscillation pause period. The capacitor voltage of the protection circuit is discharged to forcibly reduce the capacitor voltage. Therefore, the rise of the gate voltage of the FET switching element can be moderated when a surge voltage is input during burst oscillation of the switching power supply with a simpler configuration.

  In the bridge type DC-DC converter according to another configuration of the present invention, the two switching power supply circuits are connected in parallel, and the DC power of the DC power supply is converted into DC power of a predetermined voltage. According to this configuration, with a simple configuration, it is possible to prevent malfunction due to switching power supply noise in the bridge type DC-DC converter, and at the time of surge voltage input during burst oscillation, the rise of the gate voltage of the FET switching element is moderated. Therefore, it is possible to prevent the occurrence of resonance.

  The present invention operates a negative voltage generation circuit so that a square wave includes a negative voltage without being affected by a parasitic diode of the FET switching element, and converts the square wave voltage including the negative voltage into the gate voltage of the FET switching element. Since the protection forcible operation circuit that forcibly operates the protection circuit to be applied during the burst oscillation pause period is provided, it is possible to prevent malfunction due to noise with a simple configuration and to prevent surges during burst oscillation of the switching power supply. At the time of voltage input, the FET switching element can be prevented from being damaged, and the rise of the gate voltage can be moderated to prevent resonance.

It is a circuit block diagram which shows the 1st premise technique in the switching power supply circuit which concerns on 1st Embodiment of this invention. It is a characteristic view which shows the gate waveform at the time of starting in MOS-FET of the switching power supply circuit of FIG. FIG. 6 is a characteristic diagram showing a gate waveform at the start-up time in a MOS-FET in which a switching power supply circuit is a bridge type without a protection circuit. It is a circuit block diagram which shows the 2nd premise technique of this invention. FIG. 5 is a characteristic diagram showing a gate waveform at the start-up in the MOS-FET of the switching power supply circuit of FIG. 4. It is a characteristic view which shows the gate waveform at the time of starting in MOS-FET which made the switching power supply circuit the bridge type. It is a circuit block diagram which shows the switching power supply circuit which concerns on the 1st form of this invention. FIG. 8 is a characteristic diagram illustrating an operation of the switching power supply circuit of FIG. 7. It is a circuit block diagram of the power converter device provided with the bridge type DC-DC converter which is 2nd Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit configuration diagram showing a first prerequisite technique in a switching power supply circuit according to a first embodiment of the present invention. As shown in FIG. 1, the switching power supply circuit 1A according to the first premise technology turns on and off the FET switching element 3 such as a MOS-FET with a square wave voltage by driving the drive circuit 5 with the DC power of the DC power supply Vcc. By controlling, DC power of a predetermined voltage is output. The drive circuit 5 includes a negative voltage generation circuit 6 and a protection circuit 7. This switching power supply circuit is used, for example, in a power conversion device including a bridge type DC-DC converter in which two are connected in parallel to convert DC power of a DC power supply into DC power of a predetermined voltage (FIG. 9). .

  The negative voltage generation circuit 6 operates so as to include the negative voltage by shifting the square wave voltage to the negative side so that the negative voltage is applied to the gate voltage of the MOS-FET 3 to turn off the MOS-FET 3. For example, the negative voltage generation circuit 6 is formed by connecting a Zener diode ZD1 and a capacitor C1 in parallel, and connecting points QH and QL of two switching MOS-FETs that generate a square wave from the DC power of the DC power supply Vcc. 8 and the gate G of the MOS-FET 3.

  The protection circuit 7 is disposed between the negative voltage generation circuit 6 and the gate G of the MOS-FET 3, operates the negative voltage generation circuit 6 so as not to be affected by the parasitic diode Dp of the MOS-FET 3, and Is applied to the gate voltage of the MOS-FET 3. In this example, the protection circuit 7 includes a diode D1 and a resistor R connected in series.

  First, the operation when the diode D1 and the protection circuit 7 for the resistor R are not provided in FIG. 1 will be described. As described above, in the operation of the switching power supply circuit, it is necessary to satisfy the capacitance of the capacitor C1 >> the input capacitance Ciss (Cgs) of the FET. When the QH is on, the QL is off, and the MOS-FET is on, the FET The input capacitor Ciss is charged to almost the power supply voltage Vcc, and the capacitor C1 is hardly charged. Then, when QH is off, QL is on, and the MOS-FET 3 is off, a negative voltage is hardly applied between the gate and the source.

  When the protection circuit 7 having the diode D1 and the resistor connected in series in FIG. 1 is mounted as in this example, when QH is on, QL is off, and the MOS-FET 3 is on, the input capacitance Ciss of the FET 3 Current flows through the protection circuit 7 connected in parallel to the capacitor C1, and the capacitor C1 is charged to the Zener voltage VZD1. As a result, when QH is off, QL is on, and the MOS-FET 3 is off, a negative voltage VZD1 is applied between the gate and source.

  FIG. 2 shows the gate voltage waveform VGS of the MOS-FET 3 when the switching power supply is activated by the circuit of FIG. The gate voltage waveform VGS is, for example, a burst oscillation signal that is intermittent in a pause period t2 (for example, several hundred μsec). As shown in this figure, the time of t (for example, hundreds of tens of milliseconds) is required from when the switching power supply is started until a square wave including a negative voltage is generated and a sufficient negative voltage is applied to the gate voltage VGS. Although necessary, it is possible to improve the power conversion efficiency and prevent malfunction due to noise when the MOS-FET 3 is turned off during the normal operation in which the MOS-FET 3 is turned off.

  By the way, when two MOS-FETs as shown in FIG. 1 are arranged in parallel to form a bridge circuit, the protection circuit 7 shown in FIG. FIG. 3 shows operation waveforms of the MOS-FETs when a surge voltage is input immediately after the switching power supply is started. The upper stage shows the low-side gate voltage waveform of the MOS-FET, and the lower stage shows the high-side drain current waveform.

  As described above, in the first base technology, since a time of tmsec is required from when the switching power supply is started until a sufficiently negative voltage is applied to the gate voltage VGS, the protection circuit 7 does not work during this time, and the bridge When one MOS-FET of the circuit is turned on, a reverse current (through current) is generated due to the recovery current during the reverse recovery time (Trr) in the parasitic diode Dp connected in parallel between the drain and source of the other MOS-FET. There is a risk that the MOS-FET may be damaged. Further, LC resonance occurs due to the junction capacitance of the parasitic diode Dp of the MOS-FET 3 and the L component of the circuit wire, and a spike-like voltage may be generated as shown in the lower part of FIG. In this case, the MOS-FET driving IC (charge pump type or the like), the driving photocoupler or the like may malfunction, and the MOS-FET may be damaged.

  A second prerequisite technique for solving this problem at the time of starting the switching power supply will be described. As shown in FIG. 4, in the switching power supply circuit 1B according to the second prerequisite technology, the configuration of the protection circuit 7 is different from that of the first prerequisite technology. That is, in the second prerequisite technology, the protection circuit 7 is configured by connecting a diode D1, a resistor R and a capacitor C2 connected in parallel, in series. Other configurations are the same as those of the first prerequisite technology.

  When the MOS-FET 3 is on, a square wave including a negative voltage is generated immediately after the switching power supply is started by the capacitor C2 of the protection circuit 7, and the capacitor C1 of the negative voltage generation circuit 6 is steered more rapidly. When the voltage is charged to VZD1 and the MOS-FET 3 is off, the negative voltage VZD1 is applied to the gate voltage VGS of the MOS-FET 3 immediately after the switching power supply is activated.

  FIG. 5 shows the gate waveform VGS of the MOS-FET 3 when the switching power supply is activated. A negative voltage has been applied since the switching power supply was activated, and when the surge voltage is input, when the MOS-FET 3 is turned off, noise is reduced and malfunction due to noise can be prevented.

  Further, by increasing the time constants of the resistor R and the capacitor C2 of the protection circuit 7, the rise of the gate voltage can be made more gradual. Then, in the bridge circuit, the MOS-FET is gradually turned on, and LC resonance due to the junction capacitance of the parasitic diode Dp of the other MOS-FET and the L component of the circuit wire does not occur.

  FIG. 6 shows a bridge circuit in which two MOS-FETs are arranged in parallel as shown in FIG. 9, which will be described later. Each of the MOS-FETs at the time of a surge voltage input immediately after the switching power supply is activated. An operation waveform is shown. The upper stage shows the low-side gate voltage waveform of the MOS-FET, and the lower stage shows the high-side drain current waveform. As in the lower part of FIG. 6, reverse current (through current) and spike-like voltage are not generated, and there is no possibility that the MOS-FET is damaged.

  Also, during normal operation other than immediately after the switching power supply is started, the time constant of R · C2 is large (several msec or more), so the cathode of the diode D1 is almost a DC voltage, and the capacitor C2 is not charged. Therefore, during normal operation, the gate waveform is not dull and does not affect the power conversion efficiency. That is, the protection circuit 7 according to the second premise technique operates steeply only when a surge voltage is input when the switching power supply is activated, and can prevent the MOS-FET from being damaged. It operates as a circuit of diode D1 and resistor R connected in series similar to the technology.

  FIG. 7 is a circuit configuration diagram showing the switching power supply circuit according to the first embodiment of the present invention. This switching power supply circuit 1 includes a control unit 16 that controls the entire circuit, and in this control unit 10, in order to suppress an increase in the output voltage of the switching power supply circuit, the input voltage from the DC power of the DC power supply 8 and It has a burst oscillation circuit 15 that performs burst (intermittent) oscillation by generating a trigger signal according to the power range and arbitrarily interrupting the gate control signal of the MOS-FET 3. Further, a protection forcible operation circuit 9 for forcibly operating the protection circuit 7 is provided within the burst oscillation pause period.

  The protection forcible operation circuit 9 includes, for example, a photocoupler PC that operates based on a control signal S1 from the control unit 16, a series resistance R1, R2, a series connection point of the series resistance R1, R, and a transistor 4 whose base is connected, and A resistor R3 provided between the collector of the transistor 4 and the series connection point of the resistor R and the capacitor C2 connected in parallel with the diode D1 in the protection circuit 7 is provided. The circuit 9 is an example, and may be constituted by a digital transistor, for example.

  In this case as well, a surge voltage immediately after the switching power supply is started is input every intermittent oscillation. However, normally, the protection circuit 7 operates to prevent the MOS-FET 3 from being damaged. However, for example, when the time constant of R · C2 of the protection circuit 7 becomes larger than the pause period during burst oscillation such as the period t2 shown in FIG. 2, the charge of the capacitor C2 cannot be sufficiently discharged, and the capacitor C2 The voltage across the terminal (or resistor R) does not decrease. As a result, when the burst oscillation operation is started from the pause state, the gate voltage of the MOS-FET 3 cannot be raised gently, and the protection circuit 7 may not operate normally.

  FIG. 8 is a characteristic diagram showing the operation of the protection forcible operation circuit 9, where a is the gate control signal of the MOS-FET 3 subjected to burst oscillation, and b is the control signal S1. The protection forcible operation circuit 9 sends out the control signal S1 from the control unit 16 during the period t2 within the period t1 from when the burst oscillation pause period starts until the next activation as shown in FIG. Thus, the transistor 4 is turned on, and the capacitor C2 of the protection circuit 7 is forcibly discharged to lower the capacitor voltage. In this way, by forcibly operating the protection circuit 7 within the burst oscillation pause period t1, the rise of the gate voltage of the MOS-FET 3 becomes gradual when the surge voltage is input during burst oscillation of the switching power supply. Generation of LC resonance between the junction capacitance of the diode Dp and the circuit wiring can be prevented, and the protection circuit 7 can be operated normally. When the control signal S1 is not sent and the transistor 4 is off, the protection circuit 7 performs a normal operation. Note that the protection circuit 7 may be forcibly operated not only when a surge voltage is input during burst oscillation of the switching power supply but also when a surge voltage is input during startup.

  FIG. 9 is a circuit configuration diagram of a power conversion device including a bridge type DC-DC converter according to a second embodiment of the present invention. This power conversion device converts DC power of a power source such as a solar cell or a fuel cell into AC power and connects it to the AC power system 11, and converts DC power of the DC power source Vcc into DC power of a predetermined voltage. A bridge-type DC-DC converter 10 in which two switching power supply circuits are connected in parallel, and an inverter 12 that converts boosted DC power from the DC-DC converter 10 into predetermined AC power are provided. The switching power supply circuits 1 and 2 have MOS-FETs 3 and 4, a protection circuit 7, and a protection forcible protection circuit 9, respectively.

  The DC-DC converter 10 includes a step-up transformer 14 having a primary winding Np and a secondary winding Ns that performs step-up output. In addition, a voltage doubler circuit 13 that doubles the secondary voltage of the step-up transformer 6 is also provided. In this case as well, in order to prevent malfunction due to noise of the switching power supply 1 in the bridge type DC-DC converter, when the surge voltage is input during burst oscillation, the rise of the gate voltage of the MOS-FETs 3 and 4 is moderated to generate LC resonance. Can be prevented.

  Thus, according to the present invention, the negative voltage generating circuit is operated so as to include the negative voltage in the square wave without being affected by the parasitic diode of the MOS-FET, and the square wave voltage including the negative voltage is applied to the gate of the MOS-FET. The protection circuit that is applied to the voltage is forcibly operated during the burst oscillation pause period, so it is possible to prevent malfunction due to noise with a simple configuration, and at the time of burst oscillation of the switching power supply. When the surge voltage is input, the rise of the gate voltage of the MOS-FET can be moderated to prevent occurrence of LC resonance between the junction capacitance of the parasitic diode and the circuit wiring, and the protection circuit can be operated normally.

  In this embodiment, a MOS-FET is used as the FET switching element. However, an IGBT element having a part of the FET may be used.

  As described above, the preferred embodiments have been described with reference to the drawings. However, those skilled in the art will readily consider various changes and modifications within the obvious scope by looking at the present specification. Accordingly, such changes and modifications are to be construed as within the scope of the invention as defined by the appended claims.

1: switching power supply circuit 2: switching power supply circuit 3: FET switching element 4: FET switching element 5: drive circuit 6: negative voltage generation circuit 7: protection circuit 9: protection forcible operation circuit 10: bridge type DC-DC converter 15 : Burst oscillation circuit 16: Control unit Vcc: DC power supply Dp: Parasitic diode C of FET switching element C1: Negative voltage generation circuit capacitor ZD1: Negative voltage generation circuit Zener diode D1: Protection circuit diode R: Protection circuit resistance C2 : Protection circuit capacitor t1: Burst oscillation suspension period

Claims (3)

A switching power supply circuit that outputs DC power of a predetermined output voltage by controlling on / off of the FET switching element with a square wave voltage by driving the DC power of the DC power supply,
The drive circuit is
A negative voltage generating circuit that operates to include the negative voltage by shifting the voltage of the square wave to the negative side so as to turn off the FET switching element by applying a negative voltage to the gate voltage of the FET switching element;
The negative voltage generation circuit is disposed between the negative voltage generation circuit and the gate of the FET switching element, operates the negative voltage generation circuit so as not to be affected by the parasitic diode of the FET switching element, and generates a square wave voltage including the negative voltage. A protection circuit that is applied to the gate voltage of the FET switching element, and
A burst oscillation circuit for intermittently oscillating the gate control signal of the FET switching element so as to suppress an increase in the output voltage of the switching power supply circuit;
A switching power supply circuit comprising: a protection forcible operation circuit that forcibly operates the protection circuit during a burst oscillation pause period. In claim 1,
The FET switching element is a MOS-FET, and the protection circuit is provided between the gate and the source of the MOS-FET, and is configured by connecting a diode, a resistor and a capacitor connected in parallel, in series. -To increase the time constant of the resistor and capacitor of the protection circuit so as to moderate the rise of the gate voltage of the FET,
The protection forcible operation circuit is a switching power supply circuit that forcibly lowers the capacitor voltage by discharging the charge of the capacitor of the protection circuit within a pause period of the burst oscillation. 3. A bridge type DC-DC converter comprising two switching power supply circuits of claim 1 or 2 connected in parallel to convert DC power of a DC power source into DC power of a predetermined output voltage.

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