JP3550453B2 - Inverter device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an inverter device having a level shift circuit in a drive circuit for a semiconductor switching element.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, an inverter device used for driving an electric motor or the like includes a first power switching element on a high voltage side arm (hereinafter referred to as an upper arm) between main power supply terminals and a low voltage side arm (hereinafter referred to as a lower arm). ), A second power switching element is disposed, and the first and second power switching elements are connected by a totem pole connection (series connection). In such an inverter device, since the first power switching element of the upper arm is driven in a floating state with respect to the reference potential, the drive circuit of the first power switching element is insulated by the transformer. Power was used.
[0003]
Further, a means (level shift) for transmitting a control signal from the low-voltage side circuit of the upper arm to the high-voltage side circuit for controlling the first power switching element is required. Possible photocouplers or pulse transformers have been used in the past.
[0004]
These level shift circuits are required to have a high-speed signal transmission capability in accordance with a demand for a higher switching frequency of the first and second power switching elements. Further, in the inverter device, a level shift circuit is required which is not affected by a sudden potential change at the totem pole connection midpoint generated when the first and second power switching elements are turned on and off.
[0005]
Recently, a level shift circuit that does not use the photocoupler, the pulse transformer, and the like has been studied for the purpose of reducing the size of the inverter device and increasing the speed of signal transmission. An example of this is the level shifting circuit discussed on page 74 of Proceedings of The 2nd International Symposium on Power Semiconductor Devices & ICs.
[0006]
FIG. 2 shows an example of an inverter device provided with the level shift circuit of the above document.
[0007]
In FIG. 2, QT1 is a first power switching element, QB1 is a second power switching element, and DT1 and DB1 are diodes reversely connected to the QT1 and QB1. The circuit configuration is a pole connection. 2 is a load device, and VE is a power supply of the totem pole connection circuit. QB1 is driven by a drive circuit 3 powered by VCC. On the other hand, the upper arm QT1 is driven by the drive circuit 3 using the upper arm power supply VCH as a power supply. The drive circuit is operated by a level shift unit described below.
[0008]
First, the upper-arm control signal generated by the low-voltage circuit is converted into a pulse, and a pulse for turning on and off the upper arm is generated by the pulse generator 10. This is applied to the level shift circuit 1 composed of the resistors Ra and Rb and the N-channel FETs 9a and 9b. The FET 9b is turned on by the ON pulse, and the drain voltage VS of the FET 9b is reduced in potential according to the pulse signal. The potential VS is connected to the logic inverter 5 to perform waveform shaping, and the output is connected to the set side of the flip-flop 4. Therefore, the flip-flop 4 is set and outputs a high level. Therefore, by driving the upper arm drive circuit 3 with the output, the upper arm power switching element QT1 operates. Also, when the QT 1 is turned off, an off pulse is input to the reset side of the flip-flop 4 via the other level shift and waveform shaping logic inverter 5 in the same manner as described above, and the flip-flop 4 is reset. Accordingly, QT1 turns off. The above operation enables high-speed signal transmission.
[0009]
Next, a sudden change in the floating potential VM generated when QT1 is turned on (this is referred to as self-excited dV / dt) and a sudden change in the VM generated by the on / off operation of the other arm (this is referred to as separately excited dV / Dt) will be described.
[0010]
First, when QT1 is turned on, VM rises sharply and the potential fluctuates toward main power supply VE. At this time, the source-drain parasitic capacitance 8 of the N-channel FETs 9a and 9b of the level shift circuit forms a current source determined by the product of the parasitic capacitance and the voltage change rate dV / dt of the VM potential. Therefore, the current causes a voltage drop in the resistors Ra and Rb, and a pulse signal is transmitted to the waveform shaping logic inverter 5 connected to the resistors Ra and Rb. At this time, if the signal is not transmitted to the flip-flop 4, the flip-flop 4 does not operate and the initial operation (set state) is maintained, so that QT1 is not affected by dV / dt of the VM potential. The above operation is the same when the separately excited dV / dt occurs.
[0011]
As a non-transmitting means in the logic inverter 5, a method of cutting off a signal using a filter or the like is generally used because the generation period of dV / dt of the VM potential is limited.
[0012]
[Problems to be solved by the invention]
The level shift circuit generally cuts off the pulse voltage caused by the dV / dt of the VM potential by using a filter or the like for the logic inverter 5, but when the dV / dt is very small, the filter is cut off. There is a possibility that a signal is transmitted to the flip-flop 4 without being able to do so. If the filter is to be cut off to a small dV / dt, the filter time constant becomes large, and the configuration of the filter circuit becomes large. At this time, the filter may cause a delay in a normal control signal, which may impair the original purpose of speeding up signal transmission. Further, since a normal control signal requires a pulse width longer than the filter time constant, it is conceivable that the ON period of the FETs 9a and 9b becomes longer and the power consumed by the FETs 9a and 9b increases.
[0013]
The present invention provides a level shift circuit capable of preventing a malfunction of the upper arm power switching element due to the dV / dt of the VM potential, and an inverter device including the same.
[0014]
[Means for Solving the Problems]
According to the present invention, in a level shift circuit for converting a low voltage side signal into an upper arm QT1 drive signal, a circuit configuration including N-channel FETs 9a and 9b operated complementarily by a pulse signal and resistors Ra and Rb connected to the drain side thereof. in a system for transmitting an on-side pulse, between the system for transmitting the off-side pulse, and dV / dt, each moment the signal is transmitted to be interposed transmission means to lower the other resistance values, and generates A means is used for setting the voltage drop of the resistors Ra and Rb caused by the current of the product of the parasitic capacitances 8 of the N-channel FETs 9a and 9b to be larger than the other in the off-side pulse transmission system.
[0015]
According to the above-mentioned means, when the above-mentioned separately excited dV / dt is generated, since the resistance voltage drop in the off-side pulse transmission system is large, the voltage drop at the resistance value is reduced by the other resistance value reducing means. Does not occur, the off-side pulse voltage is always transmitted to the flip-flop 4, and the flip-flop 4 is reset. As a result, the upper arm power switching element QT1 is turned off. At this time, if the upper-arm power switching element QT1 is turned on in advance, it is turned off by generation of separately excited dV / dt, so that the intended purpose cannot be achieved. However, as an operation of the inverter device, the upper arm is turned on. , It is unlikely that separate excitation dV / dt occurs.
[0016]
Therefore, the separately excited dV / dt does not affect the upper arm power switching element QT1.
[0017]
On the other hand, in the self-excited dV / dt, the ON signal pulse from the low-voltage circuit is first transmitted to the upper arm to turn on the upper arm power switching element QT1, and dV / dt at the floating potential VM is generated. . At this time, the resistance value Ra of the off-side pulse transmission system in the level shift circuit 1 is reduced by means for reducing the other resistance value. Therefore, no voltage drop occurs in the resistor Rb in the ON-side pulse transmission system when dV / dt occurs. Also, even if dV / dt continues to be generated with no on-signal pulse, the signal from the off-side pulse transmission system is transmitted to the flip-flop 4 by the holding function of "the means for lowering the other resistance value". I can't do that. Therefore, even when self-excited dV / dt occurs, there is no effect on the upper arm power switching element QT1.
[0018]
According to the above operation, it is possible to provide an inverter device which is not affected by dV / dt of the floating potential VM without providing a filter circuit in a stage preceding the flip-flop 4. As a result, according to the present invention, the power consumption can be reduced without impairing the original signal transmission speed in the level shift circuit, and the filter scale can be eliminated, so that the circuit scale can be reduced.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
A configuration of a circuit according to one embodiment of the present invention will be described with reference to FIG.
[0020]
FIG. 1 shows a first embodiment of the inverter device according to the present invention.
[0021]
In the figure, QT1 is a first power switching element that is an upper-arm output stage element of a U-phase inverter, QB1 is a second power switching element that is a lower-arm output stage element of a U-phase inverter, and QT2 is V QB2 is a second power switching element which is a lower-arm output stage element of the V-phase inverter, and DT1 is a U-phase upper arm of the V-phase inverter. A freewheeling diode connected antiparallel to QT1; DB1 is a freewheeling diode connected antiparallel to QB1 of the U-phase lower arm; DT2 is a freewheeling diode connected antiparallel to QT2 of the V-phase upper arm; DB2 is V This is a reflux diode connected in antiparallel to QB2 of the lower arm. Here, a load 2 is connected between the U-phase output terminal VM1 and the V-phase output terminal VM2, and a current is supplied from the main power supply VE to the load 2 according to the on / off state of QT1, QB1, QT2, and QB2. I do.
[0022]
Next, a method of driving each of the power switching elements and a signal transmission unit will be described. The following description is made for the U-phase inverter, and the description for the V-phase inverter is omitted because it has the same configuration as the U-phase inverter.
[0023]
ON / OFF of the lower arm QB1 is controlled by a control signal SB via a drive circuit 3 using VCC as a power supply. On the other hand, the upper arm QT1 is on / off controlled by a drive circuit 3 connected to a power supply VCH having the output terminal VM1 as a reference potential. A signal for controlling the driving circuit 3 is transmitted by the following means. First, a signal ST for controlling ON / OFF of the upper arm is generated by the low voltage side circuit. The signal ST forms an on-pulse signal synchronized with the rise and fall of ST by the pulse generator 10. The pulse signal is distributed to the upper arm ON side and the OFF side, and is input to the gate terminals of the N-channel FETs 9a and 9b of the level shift circuit 1. An off-side pulse is input to 9a, and an on-side pulse is input to 9b.
[0024]
Next, a resistor Ra using VCH as a power supply is connected to the drain terminal of the N-channel FET 9a responsible for turning off the upper arm, and a P-channel FET 7a is connected in parallel with the resistor. Further, a resistor Rb using VCH as a power supply is connected to a drain terminal of the N-channel FET 9b responsible for turning off the upper arm, and a P-channel FET 7b connected in parallel with the resistor is provided. Here, the gate terminal of the P-channel FET 7a is connected to the drain terminal of the P-channel FET 7b, and conversely, the gate terminal of the P-channel FET 7b is connected to the drain terminal of the P-channel FET 7a. This forms a means for lowering the resistance of the other resistor due to the voltage drop occurring at one resistor. Here, Zda and Zdb are Zener diodes for voltage clamping. In particular, it plays the role of protecting the gate of the next-stage logic inverter 5.
[0025]
The above is the basic configuration of the level shift circuit 1.
[0026]
Here, if the output nodes of the drain terminals of the P-channel FETs 7a and 7b, which are the outputs of the level shift circuit 1, are defined as VR and VS, respectively, via the logic inverter 5 in the next stage, The VS side is inputted to the set side of the flip-flop 4 and the VR side is inputted to the reset side of the flip-flop 4. Accordingly, the flip-flop 4 outputs a high-level signal to the output Q when an input signal is input to the set side, and outputs a low-level signal to the output Q when an input signal is input to the reset side. In response, the drive circuit 3 operates and the upper arm QT1 can be turned on and off.
[0027]
The signal transmission state at this time is shown in a timing chart of FIG.
[0028]
First, a pulse signal synchronized with the rise of the signal ST is supplied to the gate terminal of the N-channel FET, and the FET is turned on. At this time, a current flows through the resistor Rb, and a voltage drop occurs at the Rb. This voltage drop is equivalent to a drop to a low level when viewed from the reference potential VM1, so that the next-stage inverter 5 is inverted to a high level. Therefore, the flip-flop 4 is set, and as a result, QT1 turns on. The same applies to the off operation.
[0029]
Next, when QT1 is turned on, the potential of the output terminal VM1 rises sharply to generate dV / dt. The operation of the level shift circuit 1 at this time will be described. With the rise of VM1, the power supply VCH using this as a reference potential also rises. On the other hand, a current path is formed from VCH via the resistances Ra and Rb by the source-drain parasitic capacitance 8 of the N-channel FETs 9a and 9b. The current is determined by the product of the parasitic capacitance 8 and dV / dt. However, since the N-channel FET 9b has been turned on in advance to turn on the upper arm QT1, the voltage drop is promoted at Rb, and at the same time, the gate-source voltage of the P-channel FET 7a rises to turn on the FET 7a. Clamp VR. As a result, the voltage drop at the resistor Ra caused by the current charging the parasitic capacitance 8 of the N-channel FET 9a is reduced. Therefore, the voltage of the node VR remains at the high level when viewed from the reference potential VM1. Therefore, the reset signal is not input to the flip-flop 4.
[0030]
Further, even when the on-pulse of the N-channel FET 9b disappears and the FET is turned off, the charging current flows through the parasitic capacitance of the FET, so that the voltage drop at Rb continues to occur, and the potential of the node VR does not decrease. The gate voltage of the P-channel FET 7b is kept low by the ON operation of the other FET 7a, so that the FET 7b has a high resistance. Therefore, since this state is maintained for a time constant determined by the resistance Rb and the parasitic capacitance of the FET 9b, the reset operation of the flip-flop 4 does not occur when dV / dt occurs.
[0031]
Next, consider dV / dt (separately excited dV / dt) generated other than the ON operation of the upper arm QT1. In this state, the N-channel FETs 9a and 9b are both off. At this time, if both the on-side and off-side transmission systems in the level shift circuit 1 are electrically the same, the same amount of current flows through the parasitic capacitance of the N-channel FETs 9a and 9b when dV / dt occurs, and the voltage flows through Ra and Rb. As a result of the drop, the set and reset signals are simultaneously input to the flip-flop 4. That is, the flip-flop 4 is undefined. Therefore, if the electrical balance between the left and right in the level shift circuit is broken due to manufacturing variations or the like, it is unclear which of the flip-flops 4 will change its state to set or reset.
[0032]
In order to solve this, means for previously breaking the electrical balance between the left and right of the level shift circuit is used. In the inverter device, the separately excited dV / dt is generated when the upper arm QT1 is off, so that when the dV / dt occurs, the level shift circuit balances the left and right so that the flip-flop 4 is reset in advance. You just need to break it down.
[0033]
In the present embodiment, the balance is broken by setting the conditions of the resistors Ra and Rb to Ra> Rb.
[0034]
In the above embodiment, the resistance balance is changed. However, regardless of this, the left and right electrical imbalances such as the parasitic capacitance of the N-channel FET or the size of the P-channel FET occur, and the voltage drop at the resistor Ra is large. You may comprise so that it may become.
Next, FIG. 4 showing another embodiment of the present invention will be described.
[0035]
4 differs from the embodiment of FIG. 1 described above in the means for lowering the other resistance value in the level shift circuit. In FIG. 4, the gate terminals of the P-channel FETs 7a and 7b are supplied from the output of the flip-flop 4. As a result, one of the FETs is always on. On the other hand, in the embodiment of FIG. 1, since the potential is fixed by the pull-up resistors Ra and Rb, the FETs 7a and 7b are normally off.
[0036]
Thus, in the present embodiment, unlike the embodiment of FIG. 1, the other resistance value in the level shift circuit can be steadily reduced. Therefore, the tolerance of dV / dt is larger than that of the embodiment shown in FIG.
[0037]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, malfunction of the power switching element by dV / dt can be prevented beforehand. This eliminates the need for a filter circuit at the next stage of the level shift circuit, thereby simplifying the circuit configuration. Further, since there is no filter circuit that hinders signal transmission, the signal transmission speed is high, and power consumption can be reduced because power consumption in the filter circuit does not occur.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment according to the present invention.
FIG. 2 is a circuit diagram according to the related art.
FIG. 3 is a diagram showing a timing chart in the embodiment of FIG. 1 according to the present invention.
FIG. 4 is a circuit showing another embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Level shift circuit, 2 ... Load, 3 ... Power switching element drive circuit, 4 ... Flip-flop, 5 ... Logic inverter, 7a, 7b ... P-channel FET, 8 ... 9a, 9b FET source-drain parasitic capacitance, 9a , 9b: N-channel FET, 10: Upper arm control pulse generator, QT1, QT2: Upper arm power switching element, QB1, QB2: Lower arm power switching element, DT1, DT2, DB1, DB2: Reflux diode, VE: Main power supply, VCC: Lower arm control power supply, VCH: Upper arm control power supply, Ra, Rb: Resistor, Zda, Zdb: Zener diode for voltage clamp, ST: Upper arm control signal, SB: Lower arm control signal, VM1 ... U-phase inverter output terminal, VM2 ... V-phase inverter output terminal, VS ... level switch Tosetto side output, VR ... level shift the reset side output.

Claims (2)

In an inverter device including a plurality of power semiconductor switching elements, a plurality of drive circuits that drive the power semiconductor switching elements, and a level shift circuit that transmits a control signal to the drive circuit via a flip-flop ,
The plurality of power semiconductor switching elements are an upper-arm output stage element and a lower-arm output stage element of the inverter device,
The level shift circuit is a circuit that transmits the control signal from a low voltage side circuit to a high voltage side circuit to the power semiconductor switching element of the upper arm,
And the level shift circuit connects one end of the first switching element and one end of the first resistor, so that the first switching element and the first resistor are connected in series,
By connecting one end of the second switching element and one end of the second resistor, the second switching element and the second resistor are connected in series,
The other end of the first switching element and the other end of the second switching element are commonly connected,
The other end of the first resistor and the other end of the second resistor are commonly connected,
A third switching element which is turned off when the first switching element is turned on is connected in parallel to both ends of the first resistor,
A fourth switching element which is turned off when the second switching element is turned on is connected in parallel to both ends of the second resistor ,
One end of the first resistor is connected to a set side of the flip-flop,
One end of the second resistor is connected to a reset side of the flip-flop,
The magnitude | size of the 1st resistance of the said level shift circuit is larger than the magnitude | size of a 2nd resistance, The inverter apparatus characterized by the above-mentioned . In an inverter device including a plurality of power semiconductor switching elements, a plurality of drive circuits that drive the power semiconductor switching elements, and a level shift circuit that transmits a control signal to the drive circuit via a flip-flop,
The plurality of power semiconductor switching elements are an upper-arm output stage element and a lower-arm output stage element of the inverter device,
The level shift circuit is a circuit that transmits the control signal from a low voltage side circuit to a high voltage side circuit to the power semiconductor switching element of the upper arm,
And the level shift circuit connects one end of the first switching element and one end of the first resistor, so that the first switching element and the first resistor are connected in series,
By connecting one end of the second switching element and one end of the second resistor, the second switching element and the second resistor are connected in series,
The other end of the first switching element and the other end of the second switching element are commonly connected,
The other end of the first resistor and the other end of the second resistor are commonly connected,
A third switching element which is turned off when the first switching element is turned on is connected in parallel to both ends of the first resistor,
A fourth switching element which is turned off when the second switching element is turned on is connected in parallel to both ends of the second resistor,
One end of the first resistor is connected to a set side of the flip-flop,
One end of the second resistor is connected to a reset side of the flip-flop,
Said level shift circuit, said inverter device parasitic capacitance of the first switching element and wherein the larger parasitic capacitance of the second switching element.

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