CN117749165A

CN117749165A - High-side level conversion circuit with strong anti-interference function

Info

Publication number: CN117749165A
Application number: CN202311795079.7A
Authority: CN
Inventors: 徐剑; 徐京伟
Original assignee: Huada Semiconductor Co ltd
Current assignee: Huada Semiconductor Co ltd
Priority date: 2023-12-25
Filing date: 2023-12-25
Publication date: 2024-03-22

Abstract

The invention relates to the technical field of integrated circuits. The invention provides a high-side level conversion circuit, which is characterized by comprising the following components: the low-voltage domain logic NOT gate, a first driving circuit, a second driving circuit, a trigger, a bias current source, a current mirror, a first high-voltage driving device, a second high-voltage driving device, a first zener diode, a second zener diode, a first resistor, a second resistor, a first high-voltage domain logic NOT gate, a second high-voltage domain logic NOT gate, a first rising signal edge delay module, a second rising signal edge delay module, a high-voltage domain RS trigger and a third driving circuit.

Description

High-side level conversion circuit with strong anti-interference function

Technical Field

The invention belongs to the field of integrated circuits, and particularly relates to a high-side level conversion and driving circuit with strong anti-interference function, which is applied to a high-voltage floating gate driving architecture.

Background

Along with the development of electronic systems to the integration direction, the high-voltage driving chip has been widely applied to the fields of electronic computers, consumer electronic products, automobile electronic products and the like. The integrated high-voltage floating gate driving chip has the characteristics of high integration level, high cost performance, simple peripheral circuit, high efficiency and the like, so that the integrated high-voltage floating gate driving chip is widely applied.

The high-voltage floating gate driving circuit adopts a high-voltage translation technology to realize the conversion from low voltage to high voltage so as to drive the high-side power tube. The high-voltage floating gate driving circuit belongs to one of typical circuits of a high-voltage integrated circuit (HVIC), adopts a high-low voltage compatible process, and utilizes a high-voltage LDMOS device to convert a low-voltage control signal into a high-voltage control signal so as to drive a high-end circuit to work.

The driving circuit in the high-voltage floating gate driving circuit is divided into a high-side driving circuit and a low-side driving circuit according to different working power supply voltages. With the power tube turned on and off, the output point voltage works in a floating state, so that the high-side driving circuit voltage also works in a floating state along with the change of the output point voltage, and the function can be realized mainly through an external bootstrap circuit.

In order to reduce the power consumption of the high-side level conversion circuit, the traditional high-side level conversion circuit generally adopts a pulse triggering and latching mode to realize the on and off of the high-side driving tube. Because the node of the high-side level conversion circuit converted from the low-voltage domain to the high-voltage domain is usually a high-resistance node, the shorter driving pulse signal is extremely easy to be interfered by other signals, so that the driving output logic error is caused, and the risks of chip damage and the like are seriously caused. In particular, circuits capable of generating high-frequency interference signals, such as a multi-channel floating gate drive circuit or an integrated switching power supply circuit, are integrated in the same chip, so that the improvement of the anti-interference capability of the level conversion circuit is particularly important for the design of the reliability of the chip.

Disclosure of Invention

In order to at least partially solve the above problems in the prior art, the present invention provides a high-side level conversion circuit with high anti-interference capability, which not only meets the requirement of the level conversion circuit on power consumption, but also realizes high anti-interference capability, thereby greatly improving the reliability of the chip.

One embodiment of the present invention provides a high-side level shift circuit including: a low voltage domain logic NOT gate, a first driving circuit, a second driving circuit, a trigger, a bias current source, a current mirror, a first high voltage driving device, a second high voltage driving device, a first zener diode, a second zener diode, a first resistor, a second resistor, a first high voltage domain logic NOT gate, a second high voltage domain logic NOT gate, a first rising signal edge delay module, a second rising signal edge delay module, a high voltage domain RS trigger and a third driving circuit,

wherein the input end of the high-side level conversion circuit receives the high-side driving signal of the low-voltage domain and is connected with the logic NOT gate of the low-voltage domain and the input end of the trigger,

the output of the low voltage domain logic NOT gate is connected to the input of the first driver circuit. The output end of the first driving circuit is connected to the grid electrode of the second high-voltage driving device, the source electrode of the second high-voltage driving device is connected to the current mirror, the drain electrode is connected to the first node,

the output end of the trigger is connected with the input end of the second driving circuit, the output end of the second driving circuit is connected with the grid electrode of the first high-voltage driving device, the source electrode of the first high-voltage driving device is connected with the current mirror, the drain electrode is connected with the second node,

the first Zener diode and the first resistor are connected in parallel between the voltage node VBST and the second node, the anode of the first Zener diode is connected with the second node, the cathode is connected with the voltage node VBST,

the second zener diode and the second resistor are connected in parallel between the voltage node VBST and the first node, the anode of the second zener diode is connected with the first node, the cathode is connected with the voltage node VBST,

the input end of the first high-voltage domain logic NOT gate is connected with the first node, the output end of the first high-voltage domain logic NOT gate is connected to the input end of the first rising signal edge delay module, and the output end of the first rising signal edge delay module is connected to the reset end R of the RS trigger.

The input end of the second high-voltage domain logic NOT gate is connected with the second node, the output end of the second high-voltage domain logic NOT gate is connected with the input end of the second rising signal edge delay module, the output end of the second rising signal edge delay module is connected with the setting end S of the RS trigger,

the Q end of the RS trigger U1 is connected to the input end of the third driving circuit, and the output end of the third driving circuit is the output end of the high-side level converter.

In one embodiment of the present invention, the current mirror includes first to third transistors, the gate and drain of the first transistor are connected to the current source, the gates of the second and third transistors are both connected to the gate of the first transistor, the drain of the second transistor is connected to the source of the first high voltage driving device, the drain of the third transistor is connected to the source of the second high voltage driving device, and the sources of the first to third transistors are all grounded.

In one embodiment of the invention, the flip-flop implements a fixed time high logic pulse signal triggered by a rising signal edge; and/or

The first to third driving circuits are buffers; and/or

The first and second high voltage driving devices are NMOS transistors.

In one embodiment of the invention, the high-side level shift circuit further comprises a bootstrap circuit, the bootstrap circuit comprising a bootstrap diode and a bootstrap capacitor,

the bootstrap diode has an anode connected to a low-side power supply, a cathode connected to a voltage node VBST,

the first electrode of the bootstrap capacitor is connected to the voltage node VBST and the second electrode is connected to the high-side ground.

In one embodiment of the present invention, when the low-voltage domain high-side driving signal pwm_hs at the input terminal changes from low level to high level, the high-level signal turns off the second high-voltage driving device through the low-voltage domain logic NOT gate and the first driving circuit; meanwhile, a high-level pulse is generated through the trigger, the first high-voltage driving device is conducted through the second driving circuit, at the moment, a signal VSET_HS at the second node is pulled down in the high-level pulse, a rising edge pulse is output by the second high-voltage domain logic NOT gate, the rising edge pulse is delayed through the second rising signal edge delay module and then is input to a set end S of the RS trigger, a logic high is output at a Q end of the RS trigger U1, and a PWM_HS_OUT high logic is output through the third driving circuit.

In one embodiment of the present invention, the high pulse time generated by the flip-flop is greater than the delay time of the second rising signal edge delay module.

In one embodiment of the present invention, when the low-voltage domain high-side driving signal pwm_hs is changed from high level to low level, a low level is generated through the flip-flop, the low level turns off the first high-voltage driving device through the second driving circuit, and simultaneously the low level signal turns on the second high-voltage driving device through the low-voltage domain logic NOT gate and the first driving circuit, at this time, the signal vrst_hs at the first node is pulled down, the first high-voltage domain logic NOT gate outputs a high logic, and after being delayed by the first rising signal edge delay module, the signal is input to the reset terminal R of the RS flip-flop, the Q terminal of the RS flip-flop U1 outputs a logic low, and the third driving circuit outputs pwm_hs_out low logic.

In one embodiment of the present invention, the high logic level pulse time output by the first high-domain logic NOT gate is greater than the delay time of the first rising signal edge delay module.

Another embodiment of the present invention provides a floating gate driving circuit including:

the high-side driving circuit is used for driving the high-side power tube; and

a low-side driving circuit for driving the low-side power tube,

wherein the high-side drive circuit includes a high-side level shift circuit.

In another embodiment of the present invention, for the high-low side driving circuit with the complementary signal input, when the low side driving tube is turned on, the high side ground is pulled low, the low side power supply charges the bootstrap capacitor through the bootstrap diode, and the low side power supply simultaneously uses the bootstrap diode, the second resistor, the second high voltage driving device and the current mirror maintenance signal vrst_hs as low logic when the high side power tube is turned off.

Drawings

To further clarify the advantages and features present in various embodiments of the present invention, a more particular description of various embodiments of the present invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, for clarity, the same or corresponding parts will be designated by the same or similar reference numerals.

Fig. 1 shows a schematic diagram of a high voltage floating gate drive circuit according to one embodiment of the invention.

Fig. 2 shows a schematic diagram of a high-side level shift circuit according to one embodiment of the invention.

Detailed Description

It should be noted that the components in the figures may be shown exaggerated for illustrative purposes and are not necessarily to scale. In the drawings, identical or functionally identical components are provided with the same reference numerals.

In the present invention, unless specifically indicated otherwise, "disposed on …", "disposed over …" and "disposed over …" do not preclude the presence of an intermediate therebetween. Furthermore, "disposed on or above" … merely indicates the relative positional relationship between the two components, but may also be converted to "disposed under or below" …, and vice versa, under certain circumstances, such as after reversing the product direction.

In the present invention, the embodiments are merely intended to illustrate the scheme of the present invention, and should not be construed as limiting.

In the present invention, the adjectives "a" and "an" do not exclude a scenario of a plurality of elements, unless specifically indicated.

It should also be noted herein that in embodiments of the present invention, only a portion of the components or assemblies may be shown for clarity and simplicity, but those of ordinary skill in the art will appreciate that the components or assemblies may be added as needed for a particular scenario under the teachings of the present invention. In addition, features of different embodiments of the invention may be combined with each other, unless otherwise specified. For example, a feature of the second embodiment may be substituted for a corresponding feature of the first embodiment, or may have the same or similar function, and the resulting embodiment would fall within the disclosure or scope of the disclosure.

It should also be noted herein that, within the scope of the present invention, the terms "identical", "equal" and the like do not mean that the two values are absolutely equal, but rather allow for some reasonable error, that is, the terms also encompass "substantially identical", "substantially equal". By analogy, in the present invention, the term "perpendicular", "parallel" and the like in the table direction also covers the meaning of "substantially perpendicular", "substantially parallel".

The numbers of the steps of the respective methods of the present invention are not limited to the order of execution of the steps of the methods. The method steps may be performed in a different order unless otherwise indicated.

The invention is further elucidated below in connection with the embodiments with reference to the drawings.

In the prior art, the high-voltage floating gate driving architecture adopts an electric pulse mode to realize high-side level conversion, and has weak anti-interference capability.

Aiming at the problems in the prior art, the invention provides a high-side level conversion circuit with high anti-interference capability, which not only meets the requirement of the level conversion circuit on power consumption, but also realizes the high anti-interference capability, thereby greatly improving the reliability of a chip.

The floating gate drive circuit architecture shown in fig. 1 operates as follows:

when the circuit works normally, HIN/LIN is a low-voltage domain input signal, the signal is two paths of signals complementary in phase, and the input stage protection circuit is shaped first. Namely, after the high-side low-voltage domain input signal HIN is shaped by the high-side shaping circuit 110, an shaped low-voltage domain high-side driving signal pwm_hs is obtained; the low-side low-voltage domain input signal LIN is shaped by the low-side shaping circuit 120 to obtain the shaped low-voltage domain low-side driving signal pwm_ls. The output signal of the low-side drive signal pwm_ls after passing through the low-side level conversion circuit 121 and the output signal of the low-side under-voltage protection circuit 123 pass through the logic circuit 124, and then are output to the low-side drive stage 125 to drive the low-side power tube 125; the low-voltage domain high-side driving signal pwm_hs is output to the latch circuit 112 after passing through the high-side level conversion circuit 111, and the output signal of the latch circuit 112 and the output signal of the high-side undervoltage protection circuit 113 are output to the high-side driving stage 115 to drive the high-side power transistor 116 after passing through the logic circuit 114. In order to prevent interference caused by noise in the chip, the power Ground (GND) 117 and the signal ground (COM) 127 are typically separated in the chip, so two signals with dead time must pass through the GND/VCOM level conversion circuit at the same time to convert the signal ground into the power ground.

The high-side level conversion circuit converts the turn-off and turn-on edges of the low-voltage domain input PWM signal into a pulse signal, converts the pulse signal into a high-voltage domain, restores the pulse signal into a high-voltage domain PWM signal through the latch circuit, and finally drives the power tube through the driving circuit. Similarly, the low-side signal is sent to the low-side output driving circuit through a high-low level conversion circuit to be changed into a low-side driving signal output meeting the requirement. And a high-low side power supply voltage undervoltage protection circuit is added to protect the driven power device.

The high voltage floating gate drive also includes a bootstrap circuit. The high-side power supply supplies power to the high-voltage circuit by a bootstrap method, and the bootstrap circuit is composed of a diode D1 and a bootstrap capacitor CBS. Bootstrap diode D1 is connected between low-side power supply VP and bootstrap capacitor CBS, which is connected between bootstrap diode and high-side ground SW. When the low side power tube 126 is on and the high side power tube 116 is off, the high side ground SW is pulled low and the low side power source VP is charged by the bootstrap diode.

The high-side signal converts the pulse signal into a floating pulse signal with the high-side ground SW as a reference through the level conversion circuit, thereby realizing the conversion of the input signal from the low-voltage domain to the high-voltage domain. After passing through the level conversion circuit, the driving signal is output from the drain electrodes of the LDMOS devices NMH5 and NMH6 in fig. 2, and is sent to the high-end output driving circuit, so that the signal is changed into a high-end driving signal output meeting the requirement.

Fig. 2 shows a schematic diagram of a high-side level shift circuit according to one embodiment of the invention. The input of the high-side level conversion circuit is an integrated low-voltage domain high-side driving signal PWM_HS, and the output is a signal PWM_HS_OUT, and the signal PWM_HS_OUT is connected to the high-voltage domain latch circuit. The bootstrap power supply is arranged between the voltage node VBST and the high-side ground SW node. The bootstrap circuit includes a diode D1 and a bootstrap capacitor CBS. The diode D1 has an anode connected to the low-side power supply VP and a cathode connected to the voltage node VBST. The bootstrap capacitor CBS has a first electrode connected to the voltage node VBST and a second electrode connected to the high-side ground SW.

As shown in fig. 2, the high-side level conversion circuit includes a low-voltage domain logic not gate U61, a first driving circuit U62, a second driving circuit U63, a flip-flop TPD1, a bias current source IB1, a current mirror formed by first to third transistors NM5 to NM7, a first high-voltage driving device NMH5, a second high-voltage driving device NMH6, a first zener diode DZ5, a second zener diode DZ6, a first resistor R5, a second resistor R6, a first high-voltage domain logic not gate U70, a second high-voltage domain logic not gate U71, a first rising signal edge delay module TD7, a second rising signal edge delay module TD6, a high-voltage domain RS flip-flop U1, and a third driving circuit U73.

In one embodiment of the invention, flip-flop TPD1 implements a fixed time high logic pulse signal triggered by a rising signal edge. The bias current source IB1 is generated in the low voltage power supply domain VDD. The first to third driving circuits U62 to U63, U73 are Buffer buffers. The logical not gates U61, U70-U71 may also be referred to as inverters INV. The first and second high voltage driving devices NMH5-NMH6 may be NMOS transistors.

An input terminal of the high-side level conversion circuit receives the low-voltage domain high-side driving signal pwm_hs and is connected to the low-voltage domain logic not gate U61 and an input terminal of the flip-flop TPD 1.

The output of the low voltage domain logic not gate U61 is connected to the input of the first drive circuit U62. An output terminal of the first driving circuit U62 is connected to a gate of the second high voltage driving device NMH 6. The source of the second high voltage driving device NMH6 is connected to the current mirror and the drain is connected to the first node.

An output terminal of the flip-flop TPD1 is connected to an input terminal of the second driving circuit U63. An output terminal of the second driving circuit U63 is connected to a gate of the first high voltage driving device NMH 5. The source of the first high voltage driving device NMH5 is connected to the current mirror and the drain is connected to the second node.

The first zener diode DZ5 and the first resistor R5 are connected in parallel between the voltage node VBST and the second node. The positive pole of the first zener diode DZ5 is connected to the second node, and the negative pole is connected to the voltage node VBST.

The second zener diode DZ6 and the second resistor R6 are connected in parallel between the voltage node VBST and the first node. The positive electrode of the second zener diode DZ6 is connected to the first node, and the negative electrode is connected to the voltage node VBST.

The input of the first high-voltage domain logic not gate U70 is connected to the first node and the output is connected to the input of the first rising signal edge delay module TD 7. The output terminal of the first rising signal edge delay module TD7 is connected to the reset terminal R of the RS flip-flop U1.

The input terminal of the second high-voltage domain logic not gate U71 is connected to the second node, and the output terminal is connected to the input terminal of the second rising signal edge delay module TD 6. The output terminal of the second rising signal edge delay module TD6 is connected to the set terminal S of the RS flip-flop U1.

The Q terminal of the RS flip-flop U1 is connected to the input terminal of the third driving circuit U73. The output terminal of the third driving circuit U73 is the output terminal of the high-side level shifter.

The current mirror includes first to third transistors NM5 to NM7, and the gate and drain of the first transistor NM5 are connected to the current source IB1. The gates of the second transistor NM6 and the third transistor NM7 are both connected to the gate of the first transistor NM 5. The drain of the second transistor NM6 is connected to the source of the first high voltage driving device NMH 5. The drain of the third transistor NM7 is connected to the source of the second high voltage driving device NMH 6. The sources of the first to third transistors NM5 to NM7 are all grounded GND.

In the operation of the high-side level conversion circuit shown in fig. 2, when the low-voltage domain high-side driving signal pwm_hs at the input end changes from low level to high level, the high-level signal turns off the second high-voltage driving device NMH6 through the low-voltage domain logic not gate U61 and the first driving circuit U62; meanwhile, a high-level pulse is generated through the trigger TPD1, the pulse turns on the first high-voltage driving device NMH5 through the second driving circuit U63, at this time, the signal vset_hs at the second node is pulled down in the level pulse, the second high-voltage domain logic not gate U71 outputs a rising edge pulse, and after being delayed by the second rising signal edge delay module TP6, the rising edge pulse is input to the set end S of the RS trigger U1, and the Q end of the RS trigger U1 outputs logic high. The third driving circuit U73 outputs pwm_hs_out high logic to drive the power transistor to be turned on, wherein the high level pulse time generated by the flip-flop TPD1 is longer than the delay time of the second rising signal edge delay module TP 6.

When the low-voltage domain high-side driving signal pwm_hs is changed from high level to low level, the low level is generated through the flip-flop TPD1, the first high-voltage driving device NMH5 is turned off by the second driving circuit U63, and the low-level signal is simultaneously turned on by the second high-voltage driving device NMH6 through the low-voltage domain logic not gate U61 and the first driving circuit U62, at this time, the signal vrst_hs at the first node is pulled down, the first high-voltage domain logic not gate U70 outputs a high logic, and after being delayed by the first rising signal edge delay module TP7, the signal is input to the reset terminal R of the RS flip-flop U1, and the Q terminal of the RS flip-flop U1 outputs a logic low, wherein the pulse time of the high logic level output by the first high-voltage domain logic not gate U70 is longer than the delay time of the first rising signal edge delay module TP 7. The third driving circuit U73 outputs PWM_HS_OUT low logic to drive the power tube to be turned off. For the high-low side driving circuit with the complementary input signals, at this time, the low side driving tube is turned on, the SW node is pulled low (see fig. 1), the low side power supply VP charges the capacitor CBS through the bootstrap diode D1, and the low side power supply VP maintains the vrst_hs signal to be low logic when the high side driving tube is turned off through the bootstrap diode D1, the resistor R6, the high voltage driving tube NMH6, and the current mirror NM 7.

The high-side level conversion circuit combines the pulse signal generated by the trigger TPD1 with the logic level signal generated by the logic NOT gate U61 in the low voltage domain, thereby solving the problem that the shorter driving pulse signal is easy to be interfered by other signals. In practical circuit application, the high-side level conversion circuit provided by the invention has strong anti-interference capability on high-frequency interference signals.

The high-side level conversion and driving circuit with strong anti-interference disclosed by the invention can be applied to a high-voltage floating gate driving architecture, so that the performance and the reliability of a chip are improved.

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications, and variations can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention as disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A high-side level shifter circuit, comprising: a low voltage domain logic NOT gate, a first driving circuit, a second driving circuit, a trigger, a bias current source, a current mirror, a first high voltage driving device, a second high voltage driving device, a first zener diode, a second zener diode, a first resistor, a second resistor, a first high voltage domain logic NOT gate, a second high voltage domain logic NOT gate, a first rising signal edge delay module, a second rising signal edge delay module, a high voltage domain RS trigger and a third driving circuit,

2. The high-side level shift circuit of claim 1, wherein the current mirror comprises first through third transistors, the gate and drain of the first transistor are connected to a current source, the gates of the second and third transistors are each connected to the gate of the first transistor, the drain of the second transistor is connected to the source of the first high-voltage drive device, the drain of the third transistor is connected to the source of the second high-voltage drive device, and the sources of the first through third transistors are each grounded.

3. The high-side level shifter circuit of claim 1, wherein the flip-flop implements a fixed-time high logic pulse signal triggered by a rising signal edge; and/or

The first to third driving circuits are buffers; and/or

The first and second high voltage driving devices are NMOS transistors.

4. The high-side level shifter circuit of claim 1, further comprising a bootstrap circuit including a bootstrap diode and a bootstrap capacitor,

5. The high-side level shift circuit of claim 1, wherein when the low-voltage domain high-side driving signal pwm_hs at the input terminal changes from low level to high level, the high-level signal turns off the second high-voltage driving device via the low-voltage domain logic not gate and the first driving circuit; meanwhile, a high-level pulse is generated through the trigger, the first high-voltage driving device is conducted through the second driving circuit, at the moment, a signal VSET_HS at the second node is pulled down in the high-level pulse, a rising edge pulse is output by the second high-voltage domain logic NOT gate, the rising edge pulse is delayed through the second rising signal edge delay module and then is input to a set end S of the RS trigger, a logic high is output at a Q end of the RS trigger U1, and a PWM_HS_OUT high logic is output through the third driving circuit.

6. The high-side level shift circuit of claim 5, wherein the high-level pulse time generated by the flip-flop is greater than the delay time of the second rising signal edge delay module.

7. The high-side level shift circuit of claim 1, wherein when the low-voltage domain high-side driving signal pwm_hs is changed from a high level to a low level, the low level turns off the first high-voltage driving device through the second driving circuit, and the low level signal turns on the second high-voltage driving device through the low-voltage domain logic not gate and the first driving circuit, at the moment, the signal vrst_hs at the first node is pulled down, the first high-voltage domain logic not gate outputs a high logic, the first rising signal is delayed by the first rising signal edge delay module and then is input to the reset terminal R of the RS flip-flop, the Q terminal of the RS flip-flop U1 outputs a logic low, and the third driving circuit outputs the pwm_hs_out low logic.

8. The high-side level shifter circuit of claim 7, wherein the high logic level pulse time output by the first high-domain logic not gate is greater than the delay time of the first rising signal edge delay module.

9. A floating gate drive circuit, comprising:

the high-side driving circuit is used for driving the high-side power tube; and

a low-side driving circuit for driving the low-side power tube,

wherein the high-side drive circuit comprises the high-side level shift circuit of any one of claims 1 to 8.

10. The floating gate drive circuit of claim 9, wherein for a high-low side drive circuit with complementary inputs, when the low side drive transistor is turned on, the high side ground is pulled low, the low side power supply charges the bootstrap capacitor through the bootstrap diode, and the low side power supply simultaneously goes low logic through the bootstrap diode, the second resistor, the second high voltage drive device, and the current mirror sustain signal vrst_hs when the high side power transistor is turned off.