CN210431216U

CN210431216U - Drive circuit and inverter power supply

Info

Publication number: CN210431216U
Application number: CN201921477542.2U
Authority: CN
Inventors: 不公告发明人
Original assignee: Shanghai Hugong Electric Group Co Ltd
Current assignee: Shanghai Hugong Electric Group Co Ltd
Priority date: 2019-09-03
Filing date: 2019-09-03
Publication date: 2020-04-28
Anticipated expiration: 2029-09-03

Abstract

The utility model discloses a drive circuit and invertion power supply, this drive circuit includes: the pulse width control module and the main driving module; the pulse width signal input end of the pulse width control module is electrically connected with the first pulse signal input end of the main drive module and is used for receiving a first pulse signal; the pulse width signal output end of the pulse width control module is electrically connected with the second pulse width signal input end of the main drive module, and the pulse width control module converts the first pulse signal into a second pulse signal and outputs the second pulse signal to the main drive module; the main driving module is used for generating a third pulse signal according to the first pulse signal and the second pulse signal, and the third pulse signal is output by the output end of the main driving module; the pulse width of the third pulse signal is determined by the first pulse signal and the second pulse signal. The embodiment of the utility model provides a technical scheme can make drive circuit to the drive signal (be the third pulse signal) that the BOOST major loop provided and the working frequency adaptation of BOOST major loop.

Description

Drive circuit and inverter power supply

Technical Field

The embodiment of the utility model provides a contravariant welding and cutting power control technical field especially relate to a drive circuit and inverter.

Background

With the wide application of the inverter type welding and cutting Power supply, the problem of current distortion of the Power grid caused by the inverter Power supply is more prominent, and the active Power Factor Correction (PFC) technology is one of the most effective solutions.

Typically, under high input grid voltage conditions (single or three phase grid voltage such as 575 Vac), a standard BOOST main loop output voltage can be designed to be up to a + BUS voltage output above 950V. At the moment, the pressure of a power tube in the BOOST main loop is required to be more than 1200V; or a complex topological structure is adopted to reduce the voltage-resistant requirement of the power tube so as to achieve the purpose of selecting the MOSFET tube or the high-speed IGBT tube with the voltage resistance of about 600V. Here, an Insulated Gate Bipolar Transistor (IGBT) having a high voltage and a high power may be used as the power Transistor. However, the turn-off time of the high-voltage high-power IGBT is longer, and the working frequency is lower; when the active PFC technology is integrated into an inverter power supply, the working frequency of a standard BOOST main loop (also called a BOOST chopper) is difficult to match with the high pulse duty ratio of a standard active PFC chip.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a drive circuit and invertion power supply to IGBT's turn-off time phase-match in drive circuit's pulse width and the BOOST major loop is favorable to setting up standard BOOST major loop and the integration of standard active PFC chip in invertion power supply.

An embodiment of the utility model provides a drive circuit, this drive includes: the pulse width control module and the main driving module;

the pulse width control module comprises a pulse width signal input end and a pulse width signal output end, and the main driving module comprises a first pulse signal input end, a second pulse signal input end and an output end;

the pulse width signal input end of the pulse width control module is electrically connected with the first pulse signal input end of the main drive module and is used for receiving a first pulse signal;

the pulse width control module converts the first pulse signal into a second pulse signal and outputs the second pulse signal to the main drive module;

the main driving module is used for generating a third pulse signal according to the first pulse signal and the second pulse signal, and the third pulse signal is output by an output end of the main driving module;

the first pulse signal comprises a first level signal and a second level signal which alternate in sequence, the second pulse signal comprises a third level signal and a fourth level signal which alternate in sequence, and the third pulse signal comprises a fifth level signal and a sixth level signal which alternate in sequence; the fifth level signal is an enable signal output by the driving circuit, the duration of the fifth level signal is the time for which the first level signal is covered by the third level signal, and the duration of the sixth level signal is at least the duration of the fourth level signal.

Further, the pulse width control module comprises a time base integrated chip.

Further, the model of the time-base integrated chip is an NE555 chip;

the pulse width control module further comprises a first resistor and a first capacitor;

the first end of the first resistor, the first end of the first capacitor, the sixth pin and the seventh pin of the NE555 chip are all electrically connected; the second end of the first resistor and the eighth pin of the NE555 chip are both electrically connected with a first power supply; the second end of the first capacitor is grounded.

Furthermore, the pulse width control module further comprises a second capacitor, a third capacitor, a fourth capacitor, a second resistor and a third resistor;

a fifth pin of the NE555 chip is grounded through the second capacitor, and the first power supply is grounded through the third capacitor;

a first pin of the NE555 chip is grounded;

the second pin of the NE555 chip, the first end of the fourth capacitor and the first end of the third resistor are electrically connected, the second end of the third resistor and the fourth pin of the NE555 chip are electrically connected to a second power supply, the second end of the fourth capacitor is electrically connected with the first end of the second resistor, and the second end of the second resistor is electrically connected with the pulse signal input end of the pulse width control module.

Further, the main driving module comprises a light driving submodule.

Further, the light driving submodule comprises a driving optocoupler;

the main driving module further comprises a first switch tube;

the input end of the first switch tube and the second pin of the driving optocoupler are electrically connected with the first pulse signal input end of the main driving module, the control end of the first switch tube is electrically connected with the second pulse signal input end of the main driving module, and the output end of the first switch tube and the third pin of the driving optocoupler are grounded;

the driving optocoupler is only switched on when the first pulse signal is the first level signal and the second pulse signal is the third level signal.

Further, the main driving module further comprises a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a second switching tube and a third switching tube;

a first end of the fourth resistor is electrically connected with a first pulse signal input end of the main driving module, and a second end of the fourth resistor is electrically connected with an input end of the first switching tube and a second pin of the driving optocoupler;

a first end of the fifth resistor is electrically connected with a second pulse signal input end of the main driving module, and a second end of the fifth resistor is electrically connected with a control end of the first switching tube;

a first end of the sixth resistor is electrically connected with a sixth pin and a seventh pin of the driving optocoupler, and a second end of the sixth resistor is electrically connected with a control end of the second switching tube and a control end of the third switching tube;

the eighth pin of the driving optocoupler and the input end of the second switching tube are electrically connected to a third power supply, and the fifth pin of the driving optocoupler and the output end of the third switching tube are electrically connected to a fourth power supply; wherein the voltage of the fourth power supply is less than 0V;

the output end of the second switching tube and the input end of the third switching tube are both electrically connected with the first end of the seventh resistor, and the second end of the seventh resistor is electrically connected to the output end of the main driving module.

Further, the first switch tube, the second switch tube and the third switch tube are all triodes or thin film transistors.

The embodiment of the utility model provides a still provide an inverter, this inverter includes the drive circuit that any above-mentioned embodiment provided.

Furthermore, the inverter power supply also comprises a power factor correction control chip and a boost chopper main loop;

the power factor correction control chip is used for generating a first pulse signal; the output end of the power factor correction control chip is electrically connected with the first pulse signal input end of the main driving module and the pulse width signal input end of the pulse width control module;

and the boost chopper main loop is used for converting an input voltage signal into an output voltage signal according to the third pulse signal.

The embodiment of the utility model provides a drive circuit includes: the pulse width control module and the main driving module; the pulse width signal input end of the pulse width control module is electrically connected with the first pulse signal input end of the main drive module and is used for receiving a first pulse signal; the pulse width signal output end of the pulse width control module is electrically connected with the second pulse width signal input end of the main drive module, and the pulse width control module converts the first pulse signal into a second pulse signal and outputs the second pulse signal to the main drive module; the main driving module is used for generating a third pulse signal according to the first pulse signal and the second pulse signal, and the third pulse signal is output by the output end of the main driving module; the first pulse signal comprises a first level signal and a second level signal which are sequentially alternated, the second pulse signal comprises a third level signal and a fourth level signal which are sequentially alternated, and the third pulse signal comprises a fifth level signal and a sixth level signal which are sequentially alternated; the fifth level signal is an enable signal output by the driving circuit, the duration of the fifth level signal is the time when the first level signal is covered by the third level signal, and the duration of the sixth level signal is at least the duration of the fourth level signal. Therefore, the output of the first level signal in the first pulse signal can be limited through the fourth level signal of the second pulse signal, so that the time of the sixth level signal can be increased, namely the dead time of the driving pulse signal output by the driving circuit is prolonged, the frequency of the fifth level signal in the third pulse signal is limited, the IGBT driving circuit can be adapted to the working frequency of the IGBT in the standard BOOST main loop, and the size and the cost of the standard BOOST main loop inductor are reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a driving circuit according to an embodiment of the present invention;

fig. 2 is a schematic timing diagram of a pulse signal when the driving circuit according to an embodiment of the present invention works;

fig. 3 is a schematic structural diagram of another driving circuit provided in an embodiment of the present invention;

fig. 4 is a schematic structural diagram of an inverter according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Illustratively, referring to fig. 1, the driving circuit 10 includes: a pulse width control module 110 and a main drive module 120; the pulse width control module 110 includes a pulse width signal input terminal and a pulse width signal output terminal, and the main driving module 120 includes a first pulse signal input terminal, a second pulse signal input terminal and an output terminal; a pulse width signal input end of the pulse width control module 110 is electrically connected with a first pulse signal input end of the main drive module and is used for receiving a first pulse signal MC 1; the pulse width signal output end of the pulse width control module 110 is electrically connected with the second pulse width signal input end of the main drive module, and the pulse width control module converts the first pulse signal into a second pulse signal MC2 and outputs the second pulse signal MC2 to the main drive module; the main driving module 120 is configured to generate a third pulse signal MC3 according to the first pulse signal MC1 and the second pulse signal MC2, wherein the third pulse signal MC3 is output from an output terminal of the main driving module 120. For example, referring to fig. 2, the first pulse signal MC1 includes a first level signal D1 and a second level signal D2 which are sequentially alternated, the second pulse signal MC2 includes a third level signal D3 and a fourth level signal D4 which are sequentially alternated, and the third pulse signal MC3 includes a fifth level signal D5 and a sixth level signal D6 which are sequentially alternated; the fifth level signal D5 is an enable signal outputted from the driving circuit, the fifth level signal D5 lasts for a period of time when the first level signal D1 is covered by the third level signal D3, the sixth level signal D6 lasts for a period of time when at least the fourth level signal D4 lasts, and at least a part of the first level signal D1 is covered by the fourth level signal D4.

For example, the pulse width control module 110 may also be referred to as a pulse-triggered fixed pulse width circuit, and the main driving module 120 may be referred to as an IGBT driving circuit; the first pulse signal MC1 can also be referred to as a PFC driving pulse of the driving circuit, the second pulse signal MC2 can be referred to as a fixed pulse width pulse, and the third pulse signal MC3 can be referred to as a PFC power tube driving pulse.

The PFC driving pulse triggers the pulse width control module 110 to operate, and generates a pulse with a fixed pulse width; the pulse width of the fixed-width pulse is set to tw, and the duration of the third level signal D3 is exemplary set to tw. The pulse with the fixed pulse width and the PFC driving pulse together drive the main driving module 120 to operate, and the main driving module 120 outputs the enable signal of the driving pulse of the PFC power tube only in a time when the enable signal of the PFC driving pulse overlaps with the enable signal of the pulse with the fixed pulse width, and does not output the enable signal in other times. Illustratively, other times except for the enable signal of the driving pulse of the PFC power tube are called dead time; thus, the dead time of the driving pulse of the PFC power tube is limited to be not less than tw. Therefore, the driving circuit 10 can adapt to the turn-off time of the high-voltage high-power IGBT, and therefore the size and the cost of the BOOST main loop inductor are favorably reduced.

Illustratively, the first level signal D1, the third level signal D3, and the fifth level signal D5 are all low level signals, and the second level signal D2, the fourth level signal D4, and the sixth level signal D6 are all high level signals. It is understood that the level signals in each pulse signal are relative, and the absolute magnitude of the level signals in different pulse signals is not necessarily related. In other embodiments, the relative level of each level signal may also be set according to the actual requirement of the driving circuit 10, which is not limited by the embodiment of the present invention.

For example, in the first pulse signal MC1, the duration of each first level signal D1 may be the same or different; the duration of each second level signal D2 may be the same, and may be different, and is determined by the front-end pfc control chip, which is not limited in the embodiment of the present invention; in the second pulse signal MC2, the duration of each third level signal D3 is the same, the duration of each fourth level signal D4 is the same, the duration of a single third level signal corresponds to an enable pulse width, and the pulse width of the second pulse signal MC2 can be set according to the actual requirement of the driving circuit 10, and is related to the internal structure of the pulse width control module 110, which is described in detail below. In the third pulse signal MC3, the duration of the fifth level signal D5 and the sixth level signal D6 is determined by the first pulse signal MC1 and the second pulse signal MC2, and is changed according to the change of the duration of the high and low levels in the two signals.

Optionally, referring to fig. 3, the pulse width control module 110 includes a time base integrated chip U21.

Thus, by using the integrated chip, the overall integration level of the driving circuit 10 is improved, and the overall size of the driving circuit 10 is reduced.

Optionally, with continued reference to fig. 3, the model of the time-base integrated chip U21 is an NE555 chip; the pulse width control module 110 further includes a first resistor R26 and a first capacitor C22; the first end of the first resistor R26, the first end of the first capacitor C22, the sixth pin and the seventh pin of the NE555 chip are all electrically connected; the second end of the first resistor R26 and the eighth pin of the NE555 chip are both electrically connected with a first power supply; the second terminal of the first capacitor C22 is connected to ground.

Illustratively, the NE555 chip is not a general type of integrated circuit. In this embodiment, the NE555 chip, the first resistor R26 and the first capacitor C22 form a monostable circuit, and a constant pulse width pulse determined by the resistance of the first resistor R26 and the capacitance of the first capacitor C22 and required by the main driving module 120 is generated.

Illustratively, the NE555 chip is an 8-pin time base integrated chip, and its pins are shown by arabic numerals 1-8 in fig. 3. The first pin (GND) is grounded; a second pin (TRIG) as a trigger input to enable it to start its time period; the third pin (OUT) is a pulse signal output end and is used for outputting a second pulse signal MC 2; the fourth pin (RESET) is a RESET pin; the fifth pin (CONTROL) is a CONTROL terminal that permits the trigger and gate voltages to be changed by external voltages. This input can be used to change or adjust the output frequency when the timer is operating in a stable or oscillatory mode of operation; the sixth pin (THRES) is the reset lock and brings the output to a low state; a seventh pin (DISCH) is a discharge end and is used for conducting or cutting off to the ground; the eighth pin (VCC) is a positive power supply voltage terminal for connecting a + 4.5V- +16V power supply.

Illustratively, the power supply voltage of the NE555 chip in fig. 3 is + 15V. In other embodiments, the power voltage may be set to other voltage values according to the actual requirement of the driving circuit 10, which is not limited by the embodiment of the present invention.

It should be noted that, in other embodiments, other types of time-base integrated chips U21 may be used, and may be electrically connected to other electrical components in a manner known to those skilled in the art to form a monostable circuit in a fixed pulse width circuit, which is not limited by the embodiments of the present invention.

Optionally, with continued reference to fig. 3, the pulse width control module 110 further includes a second capacitor C21, a third capacitor C23, a fourth capacitor C20, a second resistor R21, and a third resistor R22; the fifth pin of the NE555 chip is grounded through a second capacitor C21, and the first power supply is grounded through a third capacitor C23; a first pin of the NE555 chip is grounded; a second pin of the NE555 chip and a first end of the fourth capacitor C20 are electrically connected to a first end of the third resistor R22, a second end of the third resistor R22 and a fourth pin of the NE555 chip are electrically connected to the second power supply, a second end of the fourth capacitor C20 is electrically connected to a first end of the second resistor R21, and a second end of the second resistor R21 is electrically connected to a pulse signal input end of the pulse width control module 110.

The PFC driving pulse generates a pulse falling edge trigger pulse through the second resistor R21, the fourth capacitor C20, and the third resistor R22, and triggers a monostable circuit composed of an NE555 chip, the first resistor R26, and the first capacitor C22. The monostable generates a constant pulse width pulse determined by the values of the first resistor R26 and the first capacitor C22.

Wherein the second capacitor C21 and the third capacitor C23 are used to prevent introduction of interference. In other embodiments, the pulse width control module 110 may further include other electrical components known to those skilled in the art to optimize the pulse width control performance of the module, which is not limited by the embodiments of the present invention.

Optionally, with continued reference to fig. 3, the main drive module 120 includes a light drive submodule U20.

The optical drive submodule U20 uses an optical drive principle to isolate a subsequent control circuit from the drive circuit 10 (which may also be understood as a charge/discharge circuit) in this embodiment, thereby enhancing the reliability of a hardware circuit.

Illustratively, the light driving submodule U20 may include an optical coupler or other types of optically controlled electric driving elements capable of performing "electric-to-optical-to-electric" conversion as would be known to those skilled in the art, and the embodiments of the present invention are not limited thereto.

Optionally, with continued reference to fig. 2 and 3, light driving submodule U20 includes a driving optocoupler; the main driving module 120 further includes a first switching tube Q20; the input end of the first switching tube Q20 and the second pin of the driving optocoupler U20 are both electrically connected with the first pulse signal input end of the main driving module 120, the control end of the first switching tube Q20 is electrically connected with the second pulse signal input end of the main driving module 120, and the output end of the first switching tube Q20 and the third pin of the driving optocoupler U20 are both grounded; the driving optocoupler U20 is turned on only when the first pulse signal MC1 is the first level signal D1 and the second pulse signal MC2 is the third level signal D3. The main driving module 120 further includes a fourth resistor R20, a fifth resistor R23, a sixth resistor R24, a seventh resistor R25, a second switching tube Q21 and a third switching tube Q22; a first end of the fourth resistor R20 is electrically connected to a first pulse signal input end of the main driving module 120, and a second end of the fourth resistor R20 is electrically connected to an input end of the first switching tube Q20 and a second pin of the driving optocoupler U20; a first end of the fifth resistor R23 is electrically connected to the second pulse signal input end of the main driving module 120, and a second end of the fifth resistor R23 is electrically connected to the control end of the first switching tube Q20; a first end of the sixth resistor R24 is electrically connected with a sixth pin and a seventh pin of the driving optocoupler U20, and a second end of the sixth resistor R24 is electrically connected with a control end of the second switching tube Q21 and a control end of the third switching tube Q22; the eighth pin of the driving optocoupler U20 and the input end of the second switching tube Q21 are electrically connected to a third power supply, and the fifth pin of the driving optocoupler U20 and the output end of the third switching tube Q22 are electrically connected to a fourth power supply; wherein the voltage of the fourth power supply is less than 0V; the output terminal of the second switch transistor Q21 and the input terminal of the third switch transistor Q22 are both electrically connected to the first terminal of the seventh resistor R25, and the second terminal of the seventh resistor R25 is electrically connected to the output terminal of the main driving module 120.

Illustratively, the fixed-pulse-width pulse generated by the pulse-width control module 110 drives the first switching tube Q20 to turn off the PFC driving pulse acting on the U20 driving optocoupler through the fifth resistor R23, i.e. blocks the PFC power tube driving pulse from outputting a high level. Thus, the dead time of the driving pulse of the PFC power tube is limited to be not less than tw. The second switching tube Q21 and the third switching tube Q22 can realize the expansion (i.e. amplification) of the driving current.

Illustratively, the high level signal of the third pulse signal MC3 may be the voltage of the third power supply (illustratively, +15V), and the low level signal may be the voltage of the fourth power supply (illustratively, -5V), so that the driving circuit 10 may provide negative voltage turn-off driving, and may drive the high-voltage high-power IGBT device more effectively and reliably.

Illustratively, the fourth resistor R20, the sixth resistor R24, and the seventh resistor R25 are used for current limiting.

Illustratively, the driving circuit is applied to a wide input voltage range, such as a range from 85Vac to 575 Vac.

Optionally, the first switching tube Q20, the second switching tube Q21, and the third switching tube Q22 are all triodes or thin film transistors.

The embodiment of the utility model provides a drive circuit 10 can adapt the turn-off time of high-pressure high-power IGBT by limiting the dead time of PFC power tube drive pulse, and work at higher operating frequency (such as 35KHz) in order to reduce the volume and the cost of standard BOOST major loop inductance; the second switching tube Q21 and the third switching tube Q22 can realize expansion of driving current, provide negative pressure turn-off driving, and more effectively and reliably drive high-voltage high-power IGBT devices.

It is to be understood that the increased dead time results in increased ac zero crossing distortion, but a reasonable balance of performance and economy may be achieved in welding and cutting inverter power applications.

On the basis of the above embodiment, the embodiment of the present invention further provides an inverter power supply, which includes the driving circuit provided by any of the above embodiments, and therefore, the inverter power supply also has the technical effects of the driving circuit provided by the above embodiments, which can be understood with reference to the above, and is not repeated herein.

Optionally, referring to fig. 2 to 4, the inverter 30 further includes a power factor correction control chip 310 and a boost chopper main loop 320; the pfc chip 310 is configured to generate a first pulse signal MC 1; the output end of the pfc control chip 310 is electrically connected to the first pulse signal input end of the main driving module 120 and the pulse width signal input end of the pulse width control module 120; the boost chopper main circuit 320 is configured to convert the input voltage signal into an output voltage signal according to the third pulse signal MC 3.

Illustratively, the boost chopper main loop 320 includes IGBT devices. The PFC control chip 310 may be any type of PFC chip known to those skilled in the art.

The embodiment of the utility model provides an inverter 30 adopts ordinary PFC control chip, under wide input voltage range of application, when using IGBT power device in the standard BOOST major loop, through drive circuit control dead time, can make PFC control chip and BOOST major loop adaptation, provides the negative pressure simultaneously and turns off the drive, is favorable to more effectively driving the BOOST major loop reliably.

It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the scope of the present invention.

Claims

1. A driver circuit, comprising: the pulse width control module and the main driving module;

2. The driving circuit of claim 1, wherein the pulse width control module comprises a time base integrated chip.

3. The driving circuit according to claim 2, wherein the model of the time base integrated chip is NE555 chip;

4. The driving circuit of claim 3, wherein the pulse width control module further comprises a second capacitor, a third capacitor, a fourth capacitor, a second resistor, and a third resistor;

a first pin of the NE555 chip is grounded;

5. The driver circuit of claim 1, wherein the main drive module comprises an optical drive sub-module.

6. The drive circuit of claim 5, wherein the light drive submodule comprises a drive optocoupler;

the main driving module further comprises a first switch tube;

7. The driving circuit according to claim 6, wherein the main driving module further comprises a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a second switching tube and a third switching tube;

8. The driving circuit according to claim 7, wherein the first switching tube, the second switching tube and the third switching tube are all transistors or thin film transistors.

9. An inverter power supply comprising the drive circuit according to any one of claims 1 to 8.

10. The inverter power supply according to claim 9, further comprising a power factor correction control chip and a boost chopper main loop;