CN114089014B

CN114089014B - Drain-source voltage detection circuit and drain-source voltage detection method

Info

Publication number: CN114089014B
Application number: CN202210074273.5A
Authority: CN
Inventors: 蜜林德·古普塔
Original assignee: Guangdong Xidi Microelectronics Co ltd
Current assignee: Xidi Microelectronics Group Co ltd
Priority date: 2022-01-21
Filing date: 2022-01-21
Publication date: 2022-04-12
Anticipated expiration: 2042-01-21
Also published as: CN114089014A

Abstract

The invention relates to the field of voltage detection, and discloses a drain-source voltage detection circuit and a drain-source voltage detection method. Therefore, the drain-source voltage of the main switching tube is directly coupled to the clamping circuit through the grid-drain capacitor to form a first coupling signal, and the first controller detects the drain voltage of the main switching tube according to the first coupling signal. The detection circuit does not need to additionally arrange an external component for sensing the voltage of the drain electrode, thereby reducing noise coupling, improving detection accuracy, simplifying circuit structure and reducing circuit cost.

Description

Drain-source voltage detection circuit and drain-source voltage detection method

Technical Field

The present invention relates to the field of voltage detection, and in particular, to a drain-source voltage detection circuit and a drain-source voltage detection method.

Background

In various converters, soft switching techniques are generally used to control the conduction and the turn-off of the main switching tube, i.e. it is necessary to detect when the inductor current becomes zero so that another energy transfer cycle can start, and the inductor forms a resonance with the capacitance on the drain of the main switching tube, and it is necessary to detect the bottom of the resonance valley so that the main switching tube is controlled to conduct when the drain voltage reaches the bottom of the resonance waveform, thereby maximizing efficiency.

Generally, a drain-source voltage detection circuit is adopted to detect when the inductive current and the drain voltage reach the bottom of a resonance valley, but in the current traditional drain-source voltage detection technology, a resistor voltage divider or a capacitor or an auxiliary winding is generally used to sense the drain voltage of a main switching tube, but the traditional drain-source voltage detection technology needs to add an external component to realize the detection of the drain voltage of the main switching tube, and since the sensing needs to be performed in a noisy PCB environment, the external component may be easily coupled with other wires in normal switching time to generate noise, thereby reducing the accuracy of the detection, and the external component is additionally added, so that the whole circuit structure is complex, and the circuit cost is increased.

Disclosure of Invention

The present invention solves at least one of the above-mentioned problems to a certain extent, and therefore the present invention provides a drain-source voltage detection circuit and a drain-source voltage detection method, which do not require an additional external component for sensing a drain voltage, thereby reducing noise coupling, improving detection accuracy, simplifying a circuit structure, and reducing circuit cost.

In one aspect, the present invention provides a drain-source voltage detection circuit, which is applied to a switching converter, where the switching converter includes a main switching tube, an inductor, and a gate-drain capacitor of the main switching tube, and the drain-source voltage detection circuit includes:

the clamping circuit is electrically connected with the grid electrode of the main switching tube and used for limiting the grid electrode voltage of the main switching tube within a positive clamping voltage and a negative clamping voltage when the main switching tube is switched off, wherein the positive clamping voltage is less than the conduction threshold voltage of the main switching tube; and

and the first controller is electrically connected with the clamping circuit and used for acquiring a first coupling signal, detecting the drain voltage of the main switching tube according to the first coupling signal to determine whether the inductive current is reduced to zero, and determining whether the drain voltage enters a resonance valley after the inductive current is reduced to zero, wherein the first coupling signal is a signal that the drain-source voltage of the main switching tube is coupled to the clamping circuit through the gate-drain capacitor.

Optionally, the clamping circuit includes a first clamping circuit and a second clamping circuit, the first clamping circuit is electrically connected to the second clamping circuit, the first controller and the gate of the main switching tube, respectively, and is configured to clamp the gate voltage of the main switching tube to the negative clamping voltage when the main switching tube is turned off, and the second clamping circuit is electrically connected to the first clamping circuit, the first controller and the gate of the main switching tube, respectively, and is configured to clamp the gate voltage of the main switching tube to the positive clamping voltage when the main switching tube is turned off.

Optionally, the first clamping circuit includes a first diode, a cathode of the first diode is electrically connected to the second clamping circuit, the first controller, and a gate of the main switching tube, respectively, and an anode of the first diode is grounded.

Optionally, the second clamping circuit includes a second diode, an anode of the second diode is electrically connected to the first clamping circuit, the first controller, and a gate of the main switching tube, respectively, and a cathode of the second diode is grounded.

Optionally, the first clamping circuit includes a first transistor, a collector of the first transistor is grounded, a base of the first transistor is electrically connected to the first controller, and an emitter of the first transistor is electrically connected to the first controller, the second clamping circuit, and a gate of the main switching tube, respectively.

Optionally, the second clamping circuit includes a second transistor and a first switch, an emitter of the second transistor is electrically connected to one end of the first switch, another end of the first switch is grounded, a base of the second transistor is electrically connected to the first controller, and a collector of the second transistor is electrically connected to the first controller, the first clamping circuit, and a gate of the main switching tube, respectively.

Optionally, the drain-source voltage detection circuit further includes a first current mirror circuit and a second current mirror circuit, one end of the first current mirror circuit is electrically connected to the first controller, the other end of the first current mirror circuit is electrically connected to the first clamping circuit and the gate of the main switching tube, one end of the second current mirror circuit is electrically connected to the first controller, the other end of the second current mirror circuit is electrically connected to the second clamping circuit and the gate of the main switching tube, and the first current mirror circuit and the second current mirror circuit are configured to mirror the first coupling signal and transmit the first coupling signal to the first controller.

Optionally, the first current mirror circuit includes a third transistor, the second current mirror circuit includes a fourth transistor, a base of the third transistor is grounded together with one end of the first clamping circuit, a collector of the third transistor is electrically connected to the first controller, and an emitter of the third transistor is electrically connected to a gate of the main switching tube;

the base electrode of the fourth triode is electrically connected with the grid electrode of the main switching tube and the second clamping circuit respectively, the collector electrode of the fourth triode is electrically connected with the first controller, and the emitter electrode of the fourth triode and the other end of the second clamping circuit are grounded together.

Optionally, the drain-source voltage detection circuit further includes a first processing circuit and a second processing circuit;

the first processing circuit is electrically connected to the first controller and the first current mirror circuit, respectively, and configured to process the first coupling signal mirrored by the first current mirror circuit;

the second processing circuit is electrically connected to the first controller and the second current mirror circuit, respectively, and is configured to process the first coupling signal mirrored by the second current mirror circuit.

Optionally, the first processing circuit comprises a first current source, a first hysteresis comparator, a first inverter, a first flip-flop, and a second inverter;

one end of the first current source is electrically connected with a first direct current power supply, and the other end of the first current source is respectively electrically connected with the first current mirror circuit and the input end of the first hysteresis comparator and used for providing a first preset threshold;

the output end of the first hysteresis comparator is electrically connected with the input end of the first inverter, and the output end of the first inverter is electrically connected with the clock end of the first trigger;

a data input end of the first trigger is electrically connected with the first direct current power supply, a reset end of the first trigger is electrically connected with an output end of the second inverter, an output end of the first trigger is used for outputting a first signal, and the first signal represents whether the inductive current is reduced to zero or not;

the input end of the second phase inverter is used for receiving a first driving signal, and the first driving signal is a driving signal of the main switching tube.

Optionally, the second processing circuit includes a second current source, a second hysteresis comparator, a second flip-flop, a third inverter, and a first and gate;

one end of the second current source is electrically connected with the first direct current power supply, and the other end of the second current source is electrically connected with the second current mirror circuit and the input end of the second hysteresis comparator respectively and used for providing a second preset threshold;

the output end of the second hysteresis comparator is electrically connected with the reset end of the second trigger;

the clock end of the second trigger is electrically connected with the output end of the first inverter, the data input end of the second trigger is electrically connected with the first direct current power supply, and the output end of the second trigger is electrically connected with the first input end of the first AND gate;

the second input end of the first AND gate is electrically connected with the output end of the first hysteresis comparator, the third input end of the first AND gate is electrically connected with the output end of the third inverter, the output end of the first AND gate outputs a second signal, and the second signal is used for representing whether the drain voltage is positioned at the bottom of a resonance valley or not;

the input end of the third inverter is used for receiving a second driving signal, and the second driving signal is generated by a single-trigger circuit through the inverted signal of the first driving signal of the main switching tube.

Optionally, the first clamping circuit comprises a first field effect transistor, a first comparator and a third current source;

the drain of the first field effect transistor is electrically connected with the second clamping circuit, the first controller, the grid of the main switch tube and the inverting input end of the first comparator respectively, the grid of the first field effect transistor is electrically connected with the output end of the first comparator, and the source of the first field effect transistor is grounded;

the non-inverting input end of the first comparator is used for being connected with the negative clamping voltage, and the inverting input end of the first comparator is electrically connected with the third current source.

Optionally, the second clamp circuit includes a second field effect transistor, a second comparator;

the drain of the second field effect transistor is electrically connected with the first clamping circuit, the first controller, the grid of the main switching tube and the non-inverting input end of the second comparator respectively, the grid of the second field effect transistor is electrically connected with the output end of the second comparator, and the source of the second field effect transistor is grounded;

and the inverting input end of the second comparator is used for connecting the forward clamping voltage.

In a second aspect, an embodiment of the present invention provides a drain-source voltage detection method, which is applied to the drain-source voltage detection circuit described above, where the method includes:

acquiring a first current, wherein the first current is a current flowing through the first clamping circuit, and determining whether the inductive current is reduced to zero according to the first current and a first preset threshold;

after determining that the inductor current has dropped to zero, determining whether the drain voltage has entered a resonant valley based on the first current and the first preset threshold.

Optionally, the determining whether the inductor current drops to zero according to the first current and a first preset threshold includes:

when the first current is larger than the first preset threshold value, the inductive current is determined to be reduced to zero.

Optionally, the determining whether the drain voltage enters a resonance valley according to the first current and the first preset threshold includes:

when the first current is less than or equal to the first preset threshold, determining that the drain voltage enters a resonance valley.

Optionally, the method further comprises:

acquiring a second current, wherein the second current is a current flowing through the second clamping circuit;

and determining whether the drain voltage leaves the bottom of the resonance valley according to the second current and a second preset threshold value.

Optionally, the determining whether the drain voltage leaves the resonance valley according to the second current and a second preset threshold includes:

determining that the drain voltage leaves a resonant valley when the second current is greater than the second preset threshold.

In a third aspect, an embodiment of the present invention provides a drain-source voltage detection circuit, which is applied to a switching converter, where the switching converter includes a main switching tube, an inductor, a gate-drain capacitor of the main switching tube, and a driving circuit of the main switching tube, a driving end of the driving circuit is electrically connected to a gate of the main switching tube, and the drain-source voltage detection circuit includes: a third current mirror circuit and a second controller;

one end of the third current mirror circuit is electrically connected with the driving end of the driving circuit and the grid electrode of the main switch respectively, the other end of the third current mirror circuit is electrically connected with the second controller, and the third current mirror circuit is used for mirroring a second coupling signal when the driving circuit outputs a low level signal to turn off the main switch tube, wherein the second coupling signal is a signal that the drain voltage of the main switch tube is coupled to the grid electrode of the main switch tube through the grid-drain capacitor, and the second coupling signal is transmitted to the second controller;

the second controller is configured to obtain the second coupling signal, detect the drain voltage according to the second coupling signal, determine whether the inductor current drops to zero, and determine whether the drain voltage enters a resonant valley after the inductor current drops to zero.

Compared with the prior art, the invention at least has the following beneficial effects: the drain-source voltage detection circuit comprises a clamping circuit and a first controller, wherein the clamping circuit is electrically connected with the grid electrode of a main switching tube, the first controller is electrically connected with the clamping circuit, when the main switch tube is turned off, the clamp circuit limits the grid voltage of the main switch tube within the positive clamp voltage or the negative clamp voltage, wherein the forward clamping voltage is less than the turn-on threshold voltage of the main switching tube, so that the main switching tube is not turned on, the drain-source voltage of the main switching tube is coupled to the clamping circuit through the grid-drain capacitor to form a first coupling signal, the first controller detects the drain voltage of the main switching tube according to the first coupling signal to determine whether the inductive current is reduced to zero or not, and determining whether the drain voltage enters a resonant valley after the inductor current drops to zero. Therefore, the drain-source voltage detection circuit directly couples the drain-source voltage to the clamping circuit through the gate-drain capacitor of the main switch, so that the first controller carries out corresponding detection, an external component for sensing the drain voltage is not required to be additionally arranged, noise coupling is reduced, detection accuracy is improved, a circuit structure is simplified, and circuit cost is reduced.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.

Fig. 1 is a schematic structural diagram of a drain-source voltage detection circuit according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a drain-source voltage detection circuit according to another embodiment of the present invention;

fig. 3 is a schematic structural diagram of a drain-source voltage detection circuit according to another embodiment of the present invention;

fig. 4 is a schematic circuit structure diagram of a drain-source voltage detection circuit according to an embodiment of the present invention;

fig. 5 is a schematic circuit diagram of a drain-source voltage detection circuit according to another embodiment of the present invention;

FIG. 6 is a schematic diagram of a signal waveform provided by an embodiment of the present invention;

fig. 7 is a schematic circuit diagram of a drain-source voltage detection circuit according to another embodiment of the present invention;

FIG. 8 is a flowchart of a drain-source voltage detection method according to an embodiment of the present invention;

FIG. 9 is a flowchart of a drain-source voltage detection method according to another embodiment of the present invention;

fig. 10 is a schematic structural diagram of a control device according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of a first controller according to an embodiment of the present invention;

fig. 12 is a schematic circuit diagram of a drain-source voltage detection circuit according to another embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.

It should be noted that, if not conflicted, the various features of the embodiments of the invention may be combined with each other within the scope of protection of the invention. Additionally, while functional block divisions are performed in apparatus schematics, with logical sequences shown in flowcharts, in some cases, steps shown or described may be performed in sequences other than block divisions in apparatus or flowcharts. The terms "first", "second", "third", and the like used in the present invention do not limit data and execution order, but distinguish the same items or similar items having substantially the same function and action.

Referring to fig. 1, fig. 1 is a schematic diagram of a drain-source voltage detection circuit 100 according to an embodiment of the present invention, as shown in fig. 1, the drain-source voltage detection circuit 100 is applied to a switching converter, the switching converter includes a main switching tube QM, an inductor L1, and a gate-drain capacitor Cgd of the main switching tube QM, and a common connection point of the inductor L1, the gate-drain capacitor Cgd, and a drain of the main switching tube QM is an LX node. The drain-source voltage detection circuit 100 provided by the embodiment of the present invention will detect the voltage of the LX node and the current flowing through the inductor L1 by using the gate-drain capacitor Cgd.

The drain-source voltage detection circuit 100 includes a clamping circuit 10 and a first controller 20, the clamping circuit 10 is electrically connected to the GATE of the main switching tube QM, the connection point is a GATE node, the first controller 20 and the clamping circuit 10 are electrically connected to the GATE node, when the main switching tube QM is turned on, a current flows from a dc power source VIN through an inductor L1 and the main switching tube QM, and accumulates electric energy on an inductor L1. At this time, the LX node is grounded due to conduction of the main switching tube QM, and the voltage is 0. When the main switching tube QM is turned off, since the current in the inductor L1 cannot abruptly change, the voltage at the LX node rises rapidly until it is limited to a certain output voltage by the subsequent circuit (e.g., load) connected to the LX node, while the inductor L1 supplies current to the subsequent circuit. As the accumulated power in the inductor L1 decreases, the current in the inductor L1 also gradually decreases until the voltage at the LX node begins to drop as the current decreases to zero. Meanwhile, when the current on the inductor L1 drops to zero and enters resonance, the GATE-drain capacitor Cgd couples the voltage of the LX node to the GATE node terminal, the voltage of the GATE node decreases as the voltage of the LX node decreases, and then the clamp circuit 10 limits the GATE voltage of the main switching tube QM to within a positive clamp voltage and a negative clamp voltage, which are small and smaller than the turn-on threshold voltage of the main switching tube QM, so that the main switching tube QM is not turned on, and since the GATE voltage is clamped to a value very close to zero by the clamp circuit 10, the voltage on the GATE-drain capacitor Cgd is substantially the same as the voltage of the LX node, and the GATE-drain capacitor Cgd is connected to the clamp circuit 10, so that the voltage of the LX node can be detected by detecting the voltage or current on the clamp circuit 10, the voltage of the LX node, namely the drain voltage of the main switching tube, is also the drain-source voltage of the main switching tube.

Specifically, the drain-source voltage of the main switching tube QM is coupled to the clamping circuit 10 through the gate-drain capacitor Cgd to form a first coupling signal, and the first controller 20 detects the drain voltage of the main switching tube according to the first coupling signal to determine whether the current of the inductor L1 drops to zero, and after the current of the inductor L1 drops to zero, determines whether the drain voltage enters the bottom of the resonance.

The first coupling signal may be a current signal flowing through the clamping circuit 10, a voltage signal at a common connection point between the clamping circuit 10 and the GATE of the main switching tube QM, i.e., at a GATE node, or other detectable electrical signals at the clamping circuit 10.

If the first coupled signal is a current signal flowing through the clamp circuit 10, the current is given by:

（1）

where I is a current flowing through the clamp circuit 10 and V_LXIs the voltage of LX node, C_GDThe capacitance value of the gate-drain capacitance Cgd.

Therefore, the current is a differential value of the LX node voltage, and to detect the start of the LX node voltage drop, it can be realized by detecting when the current I becomes a positive value. To detect when the LX node voltage is at the bottom of the valley, it is only necessary to detect the time period between the time the current I drops to zero and the time it goes positive from zero.

Therefore, the drain-source voltage detection circuit directly couples the drain-source voltage to the clamping circuit through the gate-drain capacitor of the main switch, so that the first controller carries out corresponding detection, an external component for sensing the drain voltage is not required to be additionally arranged, noise coupling is reduced, detection accuracy is improved, a circuit structure is simplified, and circuit cost is reduced.

The drain-source voltage detection circuit 100 is suitable for all circuits or devices requiring soft switching technology, such as buck converters, motor drivers, boost converters, flyback converters, and many other different products.

Referring to fig. 2, fig. 2 is a drain-source voltage detection circuit according to an embodiment of the present invention, as shown in fig. 2, the clamping circuit 10 includes a first clamping circuit 11 and a second clamping circuit 12, the first clamping circuit 11 is electrically connected to the GATE node of the second clamping circuit 12, the first controller 20, and the main switching tube QM, respectively, and is configured to clamp the GATE voltage of the main switching tube QM to the clamping voltage when the main switching tube QM is turned off, and the second clamping circuit 12 is electrically connected to the first clamping circuit 11, the first controller 20, and the GATE of the main switching tube QM, respectively, and is configured to clamp the GATE voltage of the main switching tube QM to the positive clamping voltage when the main switching tube QM is turned off.

When the voltage at the LX node drops, e.g., the inductor L1 current becomes zero and enters resonance, the gate-drain capacitance Cgd will lower the gate voltage of the main switching tube QM, which is clamped to the negative clamping voltage by the first clamping circuit 11, and as the voltage at the LX node further drops, the gate-drain capacitance Cgd discharges through the first clamping circuit 11, and the voltage at the gate-drain capacitance Cgd is approximately the same as the voltage at the LX node since the gate voltage is clamped to a value very close to zero by the first clamping circuit 11.

Similarly, as the LX node voltage rises away from the valley due to the resonance of the inductor L1, the gate potential is clamped to a forward clamp voltage by the second clamp 12 and the gate-drain capacitance Cgd is charged, and the voltage across the gate-drain capacitance Cgd remains substantially the same as the LX node voltage since the gate voltage is clamped to a value very close to zero by the second clamp 12.

Therefore, the embodiment of the present invention can obtain the LX node voltage variation by detecting the voltage across the gate-drain capacitance Cgd or the current flowing through the first clamp circuit 11/through the second clamp circuit 12.

In some embodiments, referring to fig. 3, the drain-source voltage detection circuit 100 further includes a first current mirror circuit 30 and a second current mirror circuit 40, one end of the first current mirror circuit 30 is electrically connected to the first controller 20, the other end of the first current mirror circuit 30 is electrically connected to the first clamping circuit 11 and the gate of the main switching tube QM, respectively, one end of the second current mirror circuit 40 is electrically connected to the first controller 20, the other end of the second current mirror circuit 40 is electrically connected to the second clamping circuit 12 and the gate of the main switching tube QM, respectively, and the first current mirror circuit 30 and the second current mirror circuit 40 are configured to mirror the first coupling signal and transmit the first coupling signal to the first controller 20.

The first current mirror circuit 30 and the second current mirror circuit 40 may also mirror the first coupling signal by a ratio, and the ratio may be set according to needs. The ratio mirror processing of the first coupling signal by the first current mirror circuit 30 and the second current mirror circuit 40 can perform corresponding amplification processing on the first coupling signal, so that the first controller 20 can better process the first coupling signal, and the accuracy of the processing result is improved.

In some embodiments, referring to fig. 3, the drain-source voltage detection circuit 100 further includes a first processing circuit 50 and a second processing circuit 60, the first processing circuit 50 is electrically connected to the first controller 20 and the first current mirror circuit 30 respectively for processing the first coupling signal mirrored by the first current mirror circuit 30, and the second processing circuit 60 is electrically connected to the first controller 20 and the second current mirror circuit 40 respectively for processing the first coupling signal mirrored by the second current mirror circuit 40.

The first processing circuit 50 and the second processing circuit 60 can respectively perform amplification, filtering, inversion, comparison and other processes on the first coupled signal, and the processed first coupled signal is analyzed by the first controller 20. The function of the signal analyzing part can also be completed by the first processing circuit 50 and the second processing circuit 60, and the first controller 20 can determine the current state of the inductor L1 only by simply judging the signals processed by the first processing circuit 50 and the second processing circuit 60.

Referring to fig. 4, fig. 4 is a schematic circuit structure diagram of a drain-source voltage detection circuit 100 according to an embodiment of the present invention, as shown in fig. 4, the first clamping circuit 11 includes a first diode D1, a cathode of the first diode D1 is electrically connected to the second clamping circuit 12, the first controller 20, and a gate of the main switching tube QM, respectively, and an anode of the first diode D1 is grounded.

The second clamping circuit 12 includes a second diode D2, an anode of the second diode D2 is electrically connected to the first clamping circuit 11, the first controller 20 and the gate of the main switching tube QM, specifically, an anode of the second diode D2 is connected to a cathode of the first diode D1, and a cathode of the second diode D2 is grounded.

When the LX node voltage drops, for example, when the inductor L1 current drops to zero and enters resonance, the GATE-drain capacitance Cgd will lower the voltage at the GATE terminal GATE of the main switching tube QM, which is clamped by the first diode D1, and as the LX node voltage further drops, the current flowing through the first diode D1 discharges the GATE-drain capacitance Cgd. Since the voltage at the gate terminal of the main switching tube QM is fixed by the first diode D1, the difference between the voltage at the gate-drain capacitor Cgd and the voltage at the LX node is the conduction voltage drop of the diode, and the voltage at the gate-drain capacitor Cgd is approximately equal to the voltage at the LX node because the conduction voltage drop of the diode is small.

The current flowing through the first diode D1 is given by:

（2）

wherein, C_GDIs the capacitance value of the gate-drain capacitance Cgd, V_LXIs the LX node voltage.

Therefore, the current flowing through the first diode D1 is a differential value of the LX node voltage, and similarly, the voltage of the GATE terminal GATE of the main switching tube QM changes from negative voltage to positive voltage along with the resonance of the LX node voltage until being forward-clamped by the second diode D2, and the current Isns2 flowing through the second diode D2 is also a differential value of the LX node voltage, only in a different direction. To detect the start of the fall of the LX node voltage, it is only necessary to detect when the current flowing through the first diode D1 becomes a positive value, and to detect the time period when the LX node voltage is at the bottom of the resonance, it is only necessary to detect the time period between the time when the current Isns1 flowing through the first diode D1 falls to zero and the time when the current Isns2 flowing through the second diode D2 changes from zero to positive. The first controller 20 can obtain the voltage state of the inductor L1 by analyzing the currents flowing through the first diode D1 and the second diode D2, and then determine whether the inductor L1 current is reduced to zero, and after the inductor L1 current is reduced to zero, determine whether the drain voltage enters the bottom of the resonant valley.

In addition, compared with a scheme of additionally arranging the gate-drain capacitor Cgd between the main switching tubes QM to sense the drain voltage, the embodiment of the invention can reduce the switching loss without influencing the switching performance and the switching speed.

In conclusion, the drain-source voltage detection circuit directly couples the drain-source voltage to the clamping circuit through the gate-drain capacitor of the main switch, so that the first controller performs corresponding detection without additionally arranging an external component for sensing the drain voltage, thereby reducing noise coupling, improving detection accuracy, simplifying circuit structure and reducing circuit cost.

Referring to fig. 5, fig. 5 is a schematic circuit structure diagram of a drain-source voltage detection circuit according to an embodiment of the present invention, as shown in fig. 5, the first clamping circuit 11 includes a first transistor Q1, a collector of the first transistor Q1 is grounded, a base of the first transistor Q1 is grounded, and an emitter of the first transistor Q1 is connected to a gate of the main switching tube QM.

The second clamping circuit 12 includes a second transistor Q2 and a first switch SW1, an emitter of the second transistor Q2 is electrically connected to one end of the first switch SW1, the other end of the first switch SW1 is grounded, a base of the second transistor Q2 is connected to a gate of the main switch tube QM, and a collector of the second transistor Q2 is electrically connected to an emitter of the first transistor Q1 and the gate of the main switch tube QM, respectively. Specifically, the collector of the second transistor Q2 is connected to the GATE node with the emitter of the first transistor Q1 and the GATE of the main switch tube QM, respectively.

When the main switch tube QM is turned off, the first transistor Q1 clamps the gate of the main switch to a negative clamping voltage, and the second transistor Q2 clamps the gate of the main switch to a positive clamping voltage. In the embodiment of the present invention, the first transistor Q1 and the second transistor Q2 are both NPN transistors.

The main switching tube QM is turned on and off by a driving circuit, the driving circuit 200 includes a high-side switch HSW and a low-side switch LSW, and driving signals are applied to the high-side switch HSW and the low-side switch LSW for controlling the operating states of the high-side switch HSW and the low-side switch LSW, so as to pull up or pull down the voltage at the gate of the main switching tube QM.

In the conventional driving circuit 200, the high-side switch HSW and the low-side switch LSW are driven in a complementary manner, but in the embodiment of the present invention, when it is required to turn on the main switching tube QM, the low-side switch LSW is driven to be turned off, the high-side switch HSW is driven to be turned on, the GATE node is driven to be pulled high, when it is required to turn off the main switching tube QM, the high-side switch HSW is driven to be turned off, the low-side switch LSW is driven to be turned on first, the GATE node is pulled low, the main switching tube QM is turned off, and then the low-side switch LSW is driven to be turned off, so that the GATE node is not connected to any voltage node and is in a floating state. After the low-side switch LSW is turned off and the GATE node is floating, only the GATE-drain capacitance Cgd can drive the GATE of the main switching tube QM, i.e., the GATE node. It can be seen that the signals driving the high-side switch HSW and the low-side switch LSW are no longer complementary signals. The control signal of the low-side switch LSW has a narrower pulse width. In the embodiment of the invention in fig. 5, the high-side switch HSW is driven by a first drive signal (ON), the low-side switch LSW is driven by a second drive signal, the second drive signal being the inverse of the high-side switch HSW drive signal (ON) (ON)

) The second driving signal is a pulse driving signal with a fixed pulse width generated by the one-shot circuit 500, so as to drive the low-side switch LSW.

In addition, when the main switch tube QM needs to be controlled to be turned on, the high-side switch HSW is driven to be turned on, and then the GATE node is pulled up, but at the same time, the first switch SW1 needs to be turned off, the GATE node can be pulled up, if the first switch SW1 is not turned off, the emitter junction voltage VBE of the second triode Q2 clamps the GATE node to a diode conduction voltage drop, and the main switch tube QM cannot be turned on, so that when the main switch tube QM needs to be turned on, the first switch SW1 needs to be turned off, the GATE node needs to be pulled up, and then the main switch tube QM is turned on.

With continued reference to fig. 5, the first current mirror circuit 30 includes a third transistor Q3, the second current mirror circuit 40 includes a fourth transistor Q4, the base of the third transistor Q3 and the base of the first transistor Q1 are commonly grounded, the collector of the third transistor Q3 is electrically connected to the first processing circuit 50, the emitter of the third transistor Q3 is electrically connected to the gate of the main switch Q QM through a first resistor R1, the base of the fourth transistor Q4 is electrically connected to the gate of the main switch Q QM and the base of the second transistor Q2, respectively, the collector of the fourth transistor Q4 is electrically connected to the second processing circuit 60, and the emitter of the fourth transistor Q4 is connected to the emitter of the second transistor Q2 and the first switch SW1 through a second resistor R2.

The mirror ratio of the first current mirror circuit 30 is 1: m, which can be realized by adjusting the value of the first resistor R1, the mirror ratio of the second current mirror circuit 40 is 1: n, may be achieved by adjusting the value of the second resistor R2.

The third transistor Q3 switches the current signal through the first transistor Q1 in a ratio of 1: the ratio of M is mirrored to the third transistor Q3, and then processed by the subsequent first processing circuit 50 and second processing circuit 60, and the fourth transistor Q4 divides the current signal through the second transistor Q2 by 1: the ratio of N is mirrored to the second transistor Q2 for processing by the subsequent second processing circuit 60.

In some embodiments, the mirror ratio 1: m and 1: n may be the same or different and is set according to the frequency of resonance and the desired location of the valley window.

The first processing circuit 50 includes a first current source 501, a first hysteresis comparator 502, a first inverter 503, a first flip-flop 504, and a second inverter 505, one end of the first current source 501 is electrically connected to a first dc power source VDD, the other end of the first current source 501 is electrically connected to the third transistor Q3 and the input end of the first hysteresis comparator 502, the common connection point is a node N2, the first current source 501 is configured to provide a first preset threshold, the output end of the first hysteresis comparator 502 is electrically connected to the input end of the first inverter 503, the output end of the first inverter 503 is electrically connected to the clock end of the first flip-flop 504, the data input end of the first flip-flop 504 is electrically connected to the first dc power source VDD, and the reset end of the first flip-flop 504 is electrically connected to the output end of the second inverter 505, the output terminal of the first flip-flop 504 is configured to output a first signal indicating whether the current of the inductor L1 drops to zero, and the input terminal of the second inverter 505 is configured to receive a first driving signal, which is a driving signal of the main switching tube QM and is also a driving signal of the high-side switch HSW.

The second processing circuit 60 includes a second current source 601, a second hysteresis comparator 602, a second flip-flop 603, a third inverter 605 and a first and gate 604, one end of the second current source 601 is electrically connected to the first dc power VDD, the other end of the second current source 601 is electrically connected to the collector of the fourth transistor Q4 and the input end of the second hysteresis comparator 602, the common connection point is a node N1, the second current source 601 is configured to provide a second preset threshold, the output end of the second hysteresis comparator 602 is electrically connected to the reset end of the second flip-flop 603, the clock end of the second flip-flop 603 is electrically connected to the output end of the first inverter 503, the data input end of the second flip-flop 603 is electrically connected to the first dc power VDD, the output end of the second flip-flop 603 is electrically connected to the first input end of the first and gate 604, a second input terminal of the first and gate 604 is electrically connected to an output terminal of the first hysteresis comparator 502, a third input terminal of the first and gate 604 is electrically connected to an output terminal of the third inverter 605, an output terminal of the first and gate 604 outputs a second signal, the second signal is used for representing whether the drain voltage is located at the bottom of the resonant valley, an input terminal of the third inverter 605 is used for receiving a second driving signal, which is a driving signal of the low side switch LSWA second drive signal which is an inverted signal of the high side switch HSW drive signal (ON) ((R))

) A fixed pulse width pulsed drive signal is generated by the one shot circuit 500. The drive signals for the high-side switch HSW and the low-side switch LSW are shown as signals in fig. 5.

The current ITH1 of the first current source 501 has a value of a first preset threshold, and the current ITH2 of the second current source 601 has a value of a second preset threshold, and the specific values of the two current values can be set as required.

Referring to fig. 6, fig. 6 is a schematic diagram of voltages of a related device and signal waveforms of related nodes according to an embodiment of the present invention, in which a S1 curve represents a voltage at an LX node, a S2 curve represents a driving signal ON at a high-side switch HSW, i.e., a first driving signal, a S3 curve represents a driving signal at a low-side switch LSW, i.e., a second driving signal, a S4 curve represents a signal at a GATE node, a S5 curve represents a current signal flowing through a second transistor Q2, a S6 curve represents a current signal flowing through a first transistor Q1, a S7 curve represents a signal at a node N2, a S8 represents a signal at a node N1, a S9 represents an output signal of a second flip-flop 603, a S10 represents an output signal of a first flip-flop 504, and a S11 represents an output signal of a first and GATE 604.

With reference to fig. 5, the operation of the drain-source voltage detection circuit 100 can be described as follows:

before time t0, the high-side switch HSW is turned ON by the first driving signal ON, the GATE assumes a high level, the main switch tube QM is turned ON, and the LX node voltage is 0. At time t0, the high-side switch HSW is turned off by the first driving signal ON, the main switching tube QM is turned off, and the LX node voltage is rapidly increased and maintains the high voltage to power the subsequent circuits because the current ON the inductor L1 cannot abruptly change. At the same time, the first switch SW1 is turned on, so that the emitter of the second transistor Q2 is grounded. Also at time t0, the low-side switch LSW is briefly turned on by the second driving signal to achieve a brief grounding of the GATE terminal, and then the low-side switch LSW is controlled by the second driving signal to turn off, so that the GATE terminal is floating. Between times t0 and t1, the current on inductor L1 gradually decreases until time t1 decreases to zero. At this point the voltage at the LX node begins to drop and the voltage at the GATE node is pulled down due to the coupling of Cgd until the first transistor Q1 clamps the GATE node below the diode turn-on voltage (i.e., the negative clamp voltage) and the current in the first transistor Q1 is scaled by 1: the ratio of M mirrors. In addition, the first resistor R1 attenuates the current flowing in the third transistor Q3. Comparing the current flowing through the third transistor Q3 with the current ITH1 of the first current source 501, when the current in the third transistor Q3 is greater than the current ITH1 of the first current source 501, the voltage at the node N2 is pulled low, which causes the output end of the first flip-flop 504 to output a high level signal, and after the first controller 20 receives the high level signal, it determines that the current in the inductor L1 is reduced to zero;

at the same time, the voltage at node N2 also sets the second flip-flop 603 to prepare valley detection. After time t1, the current in the first transistor Q1 rises to peak when the voltage at the LX node falls the fastest. As the voltage at the LX node continues to slowly drop, the current in the first transistor Q1 drops again. At time t2, when the voltage at the LX node goes to the valley, before the current flowing through the third transistor Q3 drops to zero (i.e., the current flowing through the first transistor Q1 drops to zero), the current is smaller than the current ITH1 of the first current source 501, the voltage at the node N2 is pulled high, the output signal of the first and gate 604 becomes a high signal, and after the first controller 20 receives the high signal, it is determined that the valley region has started, i.e., it is determined that the drain voltage V is at V_LXEntering the bottom of the resonance valley.

The GATE node is clamped to one diode drop negative by the first transistor Q1 between t1 and t2 until the voltage at the LX node reaches the bottom of the resonance, and then the voltage at the LX node will rise again, which will pull the GATE node high and cause the first transistor Q1 to turn off, and the GATE node will rise again until it is clamped to one diode drop negative by the second transistor Q2 near time t 3. Similarly, at this time, the current flowing through the second transistor Q2 is divided into two parts, namely, 1: n is mirrored in the fourth transistor Q4, and the mirror ratio can be adjusted by the second resistor R2, the mirrored current flows through the fourth transistor Q4, when the current flowing through the fourth transistor Q4 is larger than the current ITH2 of the second current source 601, the potential of the node N1 is pulled down, so as to reset the second flip-flop 603, and the output of the first and gate 604 is a low level signal, and after the first controller 20 receives the low level signal, it is determined that the valley region has ended, i.e., it is determined that the drain voltage leaves the bottom of the resonant valley.

Thus, embodiments of the present invention utilize voltage differentials to detect the valley of the drain voltage resonance waveform, and since the differential of the valley bottom has the highest rate of change, the first and gate 604 will react faster at its input with a faster ramp rate, making it easier to detect the valley bottom region.

Moreover, if the high-side switch HSW and the low-side switch LSW are integrated in the first controller 20, so that the driving pins are connected to the GATE node, and the first current mirror circuit 30, the second current mirror circuit 40, the first processing circuit 50, and the second processing circuit 60 are all integrated in the first controller 20, the current flowing through the first transistor Q1 or the second transistor Q2 can be obtained by using the driving pins, that is, the driving pins are configured to sense the drain voltage, thereby eliminating the need to provide a separate pin for drain voltage sensing on the first controller 20, realizing pin multiplexing, simplifying the circuit structure, and saving the circuit cost.

In addition, when used in some voltage conversion circuits requiring break-before-make, embodiments of the present invention can avoid the use of any high voltage equipment needed to transmit signals between the high voltage domain and the low voltage domain, and adaptively achieve break-before-make rather than relying on fixed dead time.

Meanwhile, when the drain-source voltage is detected in a clamping mode, the low-side switch LSW is in a turn-off state, so that the voltage at the LX node is coupled to the voltage fluctuation at the gate of the main switching tube QM through the gate-drain capacitor Cgd and can generate current and be detected only if the voltage fluctuation is larger than the conduction threshold voltage of the triode, and the detection is accurate and has wider applicability.

To sum up, the drain-source voltage detection circuit directly couples the drain-source voltage to the clamping circuit through the gate-drain capacitor of the main switch, so that the first controller performs corresponding detection without additionally arranging an external component for sensing the drain voltage, thereby reducing noise coupling, improving detection accuracy, simplifying circuit structure and reducing circuit cost.

In some embodiments, the first controller 20 may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a single chip, an arm (acorn RISC machine) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. Also, the first controller 20 may be any conventional processor, controller, microcontroller, or state machine. The first controller 20 may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.

In some embodiments, the first flip-flop 504 and the second flip-flop 603 are schmitt flip-flops, and the first and gate 604 is a comparator.

In some embodiments, the voltages at node N1 and node N2 may not be allowed to swing all the way to the supply voltage to speed up the sensing speed, and high speed comparators may be used to create digital signals representing the states of nodes N1 and N2. The current of the third transistor Q3/the current of the first current source 501 and the current of the fourth transistor Q4/the current of the second current source 601 may be input stages of such a high-speed comparator.

In some embodiments, the time for the gate to become high impedance after the main switching tube QM is turned off may be adjusted according to the time for the first controller 20 to be ready to sense the drain voltage, rather than just a fixed value, which may be adjusted by controlling the state of the low-side switch LSW.

In some embodiments, the current scaling from the clamp circuit 10 to the mirror transistor may be done using a different mirroring scheme, or the current through the clamp circuit 10 may be sensed using other means, such as a series resistor or sensing the voltage drop across a switch in series with the clamp circuit 10.

In some embodiments, the first resistor R1 and the second resistor R2 may be adaptively tuned by looking at the pulse width of the valley signal. Adding the first resistor R1 and the second resistor R2 will increase the valley pulse width because it will provide more attenuation to the current in the third transistor Q3 and the fourth transistor Q4.

In some embodiments, the first clamping circuit 11 and the second clamping circuit 12 can be implemented in various ways, and specifically, referring to fig. 7, fig. 7 is a schematic circuit structure diagram of a drain-source voltage detection circuit according to an embodiment of the present invention, as shown in fig. 7, the first clamping circuit 11 includes a first fet Q5, a first comparator U1, and a third current source 111, a drain of the first fet Q5 is electrically connected to the second clamping circuit 12, the first controller 20, a gate of the main switch QM, and an inverting input of the first comparator U1, a gate of the first fet Q5 is electrically connected to an output of the first comparator U1, a source of the first fet Q5 is grounded, a non-inverting input of the first comparator U1 is used for accessing the negative-clamping voltage-REF, the inverting input terminal of the first comparator U1 is further electrically connected to the third current source 111.

In some embodiments, the first clamp circuit 11 further includes a third resistor R3, the third resistor R3 being connected in series between the inverting input terminal of the first comparator U1 and the drain of the first fet Q5.

The second clamping circuit 12 includes a second fet Q6 and a second comparator U2, a drain of the second fet Q6 is electrically connected to a drain of the first fet Q5, the first controller 20, a gate of the main switch QM and a non-inverting input of the second comparator U2, a gate of the second fet Q6 is electrically connected to an output of the second comparator U2, a source of the second fet Q6 is grounded, and an inverting input of the second comparator U2 is used for receiving the positive clamping voltage + REF.

In an embodiment of the present invention, the positive clamp voltage + REF and the negative clamp voltage-REF have the same value. The current of the third current source 111 is set as desired.

Referring to fig. 8, a schematic flow chart of a drain-source voltage detection method according to an embodiment of the present invention is applied to a drain-source voltage detection circuit including a first clamp circuit and a second clamp circuit in any of the above embodiments, and as shown in fig. 8, the drain-source voltage detection method includes:

s81, acquiring a first current, wherein the first current is a current flowing through the first clamping circuit, and determining whether the inductive current is reduced to zero according to the first current and a first preset threshold;

the first current is generated by coupling the voltage on the inductor to a first clamping circuit through a gate-drain capacitor of the main switching tube, the first current is compared with a first preset threshold value, and whether the inductor current is reduced to zero or not is determined according to the comparison result. In some embodiments, it is determined that the inductor current has dropped to zero when the first current is greater than the first preset threshold. And after the inductive current is determined to be reduced to zero, detecting the resonance valley bottom area of the drain voltage.

And S82, after the inductor current is determined to be reduced to zero, determining whether the drain voltage enters a resonance valley according to the first current and the first preset threshold value.

And when the LX node voltage starts to fall after being clamped to the output voltage, the inductance current becomes zero, meanwhile, the LX node voltage enters resonance, and when the first current is smaller than or equal to the first preset threshold value, the drain voltage is determined to enter the bottom of the resonance valley.

In summary, in the drain-source voltage detection method, the drain-source voltage of the main switching tube can be coupled to the clamp circuit through the gate-drain capacitor, and whether the inductor current is reduced to zero or not is determined by detecting the current on the clamp circuit, and after the inductor current is reduced to zero, whether the drain voltage enters the bottom of the resonant valley or not is determined. An external component for sensing the drain voltage is not required to be additionally arranged, so that the noise coupling is reduced, the detection accuracy is improved, the circuit structure is simplified, and the circuit cost is reduced.

Referring to fig. 9, fig. 9 is a flowchart of a drain-source voltage detection method according to an embodiment of the present invention, and as shown in fig. 8, the drain-source voltage detection method further includes:

s83, acquiring a second current, wherein the second current is a current flowing through the second clamping circuit;

and S84, determining whether the drain voltage leaves the bottom of the resonance valley according to the second current and a second preset threshold value.

After determining that the inductor current has dropped to zero, the voltage at the gate of the main switching transistor is clamped by a second clamping circuit to a forward clamping voltage, such as a diode conduction voltage drop that is positive in the above embodiment, or + REF.

At the moment, the drain voltage is coupled to the second clamping circuit through the grid-drain capacitor to generate a second current, and whether the drain voltage leaves the bottom of the resonance valley is determined through the second current and a second preset threshold value. Specifically, when the second current is greater than the second preset threshold, it is determined that the drain voltage leaves the resonant valley, and the valley region is characterized to be over.

In summary, in the drain-source voltage detection method, the drain-source voltage of the main switching tube can be coupled to the clamping circuit through the gate-drain capacitor, and whether the inductive current is reduced to zero or not is determined by detecting the current on the clamping circuit, and after the inductive current is reduced to zero, whether the drain voltage enters the bottom of the resonance valley or not is determined. An external component for sensing the drain voltage is not required to be additionally arranged, so that the noise coupling is reduced, the detection accuracy is improved, the circuit structure is simplified, and the circuit cost is reduced.

It should be noted that, in the foregoing embodiments, a certain order does not necessarily exist between the foregoing steps, and it can be understood by those skilled in the art from the description of the embodiments of the present invention that, in different embodiments, the foregoing steps may have different execution orders, that is, may be executed in parallel, may also be executed in an exchange manner, and the like.

As another aspect of the embodiments of the present invention, the embodiments of the present invention provide a control apparatus. The control device may be a software module, where the software module includes a plurality of instructions, and the instructions are stored in a memory in the electronic tilt, and the processor may access the memory and call the instructions to execute the instructions, so as to complete the drain-source voltage detection method described in each of the above embodiments.

In some embodiments, the control device may also be built by hardware devices, for example, the control device may be built by one or more than two chips, and the chips may work in coordination with each other to complete the drain-source voltage detection method described in the above embodiments. For another example, the control device may be constructed by various types of logic devices, such as a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a single chip, an arm (acorn RISC machine) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components.

Referring to fig. 10, fig. 10 shows a control device 300 according to an embodiment of the present invention, which includes a first determining module 31 and a second determining module 32.

The first determining module 31 is configured to obtain a first current, where the first current is a current flowing through the first clamping circuit, and determine whether the inductor current decreases to zero according to the first current and a first preset threshold;

the second determining module 32 is configured to determine whether the drain voltage enters a resonant valley according to the first current and the first preset threshold after determining that the inductor current drops to zero.

Therefore, the control device can couple the drain-source voltage of the main switching tube to the clamping circuit through the grid-drain capacitor, determine whether the inductive current is reduced to zero through the current detection on the clamping circuit, and determine whether the drain voltage enters the bottom of the resonance valley after the inductive current is reduced to zero. An external component for sensing the drain voltage is not required to be additionally arranged, so that the noise coupling is reduced, the detection accuracy is improved, the circuit structure is simplified, and the circuit cost is reduced.

In some embodiments, the first determining module 31 is specifically configured to determine that the inductor current decreases to zero when the first current is greater than the first preset threshold.

In some embodiments, the second determining module 32 is specifically configured to determine that the drain voltage enters a resonance valley when the first current is less than or equal to the first preset threshold.

In some embodiments, the control device 300 further includes an obtaining module 33 and a third determining module 34.

The obtaining module 33 is configured to obtain a second current, where the second current is a current flowing through the second clamping circuit;

the third determining module 34 is configured to determine whether the drain voltage is away from the bottom of the resonant valley according to the second current and a second preset threshold.

It should be noted that the control device can execute the drain-source voltage detection method provided by the embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method. For details of the drain-source voltage detection method provided in the embodiments of the present invention, reference may be made to the following description.

Referring to fig. 11, fig. 11 is a schematic structural diagram of a first controller according to an embodiment of the present disclosure. As shown in fig. 11, the first controller 20 includes one or more processors 21 and a memory 22. In fig. 11, one processor 21 is taken as an example.

The processor 21 and the memory 22 may be connected by a bus or other means, and fig. 11 illustrates the connection by a bus as an example.

The memory 22, which is a non-volatile computer-readable storage medium, may be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the drain-source voltage detection method in the embodiments of the present invention. The processor 21 executes various functional applications and data processing of the control device by running the nonvolatile software program, instructions and modules stored in the memory 22, that is, the functions of the drain-source voltage detection method provided by the above method embodiment and the various modules or units of the above device embodiment are realized.

The memory 22 may include high speed random access memory and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, the memory 22 may optionally include memory located remotely from the processor 21, and these remote memories may be connected to the processor 21 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The program instructions/modules are stored in the memory 22 and, when executed by the one or more processors 21, perform the drain-source voltage detection method of any of the method embodiments described above.

Embodiments also provide a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions that, when executed by an electronic device, cause the electronic device to perform any one of the drain-source voltage detection methods.

In summary, the control device may couple the drain-source voltage of the main switching tube to the clamp circuit through the gate-drain capacitor, determine whether the inductor current is reduced to zero by detecting the current on the clamp circuit, and determine whether the drain voltage enters the resonant valley after the inductor current is reduced to zero. An external component for sensing the drain voltage is not required to be additionally arranged, so that the noise coupling is reduced, the detection accuracy is improved, the circuit structure is simplified, and the circuit cost is reduced.

The above-described embodiments of the apparatus or device are merely illustrative, wherein the unit modules described as separate parts may or may not be physically separate, and the parts displayed as module units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network module units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a general hardware platform, and certainly can also be implemented by hardware. Based on such understanding, the above technical solutions substantially or contributing to the related art may be embodied in the form of a software product, which may be stored in a computer-readable storage medium, such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method according to the embodiments or some parts of the embodiments.

In some embodiments, the drain-source voltage detection circuit 100 may completely remove the clamp circuit 10 and directly connect across the low side switch LSW of the driver circuit 200 to sense the inductor L1 current, and the low side switch LSW transistor is never turned off to make the gate high impedance. For the main switching tube QM with large gate-drain capacitance Cgd or with very high resonant frequency, which may result in a large current flowing out of the gate-drain capacitance Cgd, the solution provided by the embodiment of the present invention is more suitable.

Referring to fig. 12, fig. 12 is a drain-source voltage detection circuit for a switching converter, the switching converter includes a main switching tube QM, an inductor L1, a GATE-drain capacitor Cgd of the main switching tube QM, and a driving circuit 200 of the main switching tube QM, a driving end of the driving circuit 200 is electrically connected to a GATE of the main switching tube QM, as shown in fig. 12, the drain-source voltage detection circuit 400 includes a third current mirror circuit 401 and a second controller 402, wherein one end of the third current mirror circuit 401 is electrically connected to a GATE node with the driving end of the driving circuit 400 and the GATE of the main switching tube QM, respectively, and the other end of the third current mirror circuit 401 is electrically connected to the second controller 402.

The driving circuit 200 may output a high level signal to drive the main switching tube QM to be turned on, and may also output a low level signal to drive the main switching tube QM to be turned off, and the driving circuit 200 may be composed of a high-side switch HSW and a low-side switch LSW, where a common connection point of the high-side switch HSW and the low-side switch LSW is a driving end of the driving circuit 200, i.e., a GATE node. The driving signals are applied to the high-side switch HSW and the low-side switch LSW to control the operating states of the high-side switch HSW and the low-side switch LSW, so as to drive the main switching tube QM. As shown in fig. 12, the GATE of the main switching tube QM is a GATE node, the source of the high-side switch HSW is connected to the first dc power source VDD, the drain of the high-side switch HSW is connected to the GATE node, and the GATE of the high-side switch HSW is used for receiving the driving signal. The drain of the low side switch LSW is connected to the GATE node, the source of the low side switch LSW is grounded, the GATE of the low side switch LSW is used for receiving the driving signal, and the GATE of the low side switch LSW is also connected to one end of the third current mirror circuit 401. When the drain-source voltage detection is performed, the low-side switch LSW is kept in a conducting state.

The circuit composition and connection relationship of the third current mirror circuit 401 are as shown in fig. 12, the third current mirror circuit 401 includes a fourth current source IB, a fifth transistor Q7, a sixth transistor Q8 and a third field effect transistor Q9, one end of the fourth current source IB is connected to the first direct current power supply VDD, the other end is connected to the collector of the fifth transistor Q7, the base of the fifth transistor Q7 is respectively connected to the collector of the fifth transistor Q7 and the base of the sixth transistor Q8, and the emitter of the fifth transistor Q7 is connected to the GATE node. The collector of the sixth transistor Q8 is connected to the second controller 402, the emitter of the sixth transistor Q8 is connected to the drain of the third fet Q9, the source of the third fet Q9 is grounded, and the gate of the third fet Q9 is connected to the gate of the low side switch LSW.

The current from the fourth current source IB provides a bias current to the sixth transistor Q8, turning on the sixth transistor Q8, mirroring the current at the drain of the low side switch LSW, where the mirrored current Isns is the current flowing through the sixth transistor Q8 and the third fet Q9, and similarly, the mirrored current Isns is received and processed by the second controller 402, the second controller 402 determines whether the inductor L1 current has dropped to zero based on the mirrored current Isns, and determines whether the drain voltage has entered a resonant valley after the inductor L1 current has dropped to zero.

In the embodiment of the present invention, in the state where the low-side switch LSW is kept on, the voltage at the LX node is coupled to the gates of the low-side switch LSW and the main switching tube QM through the gate-drain capacitor Cgd, and then it is determined whether the current in the inductor L1 has dropped to zero by detecting the current flowing through the low-side switch LSW, so as to determine whether the drain voltage has entered the bottom of the resonance after the current in the inductor L1 has dropped to zero. Because the on-resistance of the low-side switch LSW when turned on is very small, a very large gate voltage fluctuation is required to generate a relatively obvious current difference, and the sensitivity requirement of the third current mirror circuit 401 is high, this scheme is suitable for the situation that the amplitude of the signal on the inductor L1 is relatively large and the signal coupled to the gate of the main switch tube QM through the gate-drain capacitor Cgd is relatively strong, and further simplifies the circuit structure and reduces the circuit cost.

In summary, the drain-source voltage detection circuit directly couples the drain-source voltage of the main switching tube to the clamping circuit through the gate-drain capacitor, determines whether the inductor current is reduced to zero by detecting the current on the clamping circuit, and determines whether the drain voltage enters the bottom of the resonant valley after the inductor current is reduced to zero. An external component for sensing the drain voltage is not required to be additionally arranged, so that the noise coupling is reduced, the detection accuracy is improved, the circuit structure is simplified, and the circuit cost is reduced.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; within the idea of the invention, also technical features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. The utility model provides a drain-source voltage detection circuit, is applied to the switching converter, the switching converter include main switch tube, inductance and the grid leakage electric capacity of main switch tube, its characterized in that, drain-source voltage detection circuit includes:

the clamping circuit is electrically connected with the grid electrode of the main switching tube and used for limiting the grid electrode voltage of the main switching tube within a positive clamping voltage and a negative clamping voltage when the main switching tube is switched off, wherein the positive clamping voltage is less than the conduction threshold voltage of the main switching tube;

2. The drain-source voltage detection circuit of claim 1, wherein the clamping circuit comprises a first clamping circuit and a second clamping circuit, the first clamping circuit is electrically connected to the second clamping circuit, the first controller and the gate of the main switch transistor respectively, and is configured to clamp the gate voltage of the main switch transistor to the negative clamping voltage when the main switch transistor is turned off, and the second clamping circuit is electrically connected to the first clamping circuit, the first controller and the gate of the main switch transistor respectively, and is configured to clamp the gate voltage of the main switch transistor to the positive clamping voltage when the main switch transistor is turned off.

3. The drain-source voltage detecting circuit of claim 2, wherein the first clamping circuit comprises a first diode, a cathode of the first diode is electrically connected to the second clamping circuit, the first controller and a gate of the main switch tube, respectively, and an anode of the first diode is grounded.

4. The drain-source voltage detection circuit of claim 2, wherein the second clamping circuit comprises a second diode, an anode of the second diode is electrically connected to the first clamping circuit, the first controller and the gate of the main switch tube, respectively, and a cathode of the second diode is grounded.

5. The drain-source voltage detection circuit of claim 2, wherein the first clamp circuit comprises a first transistor, a collector of the first transistor is grounded, a base of the first transistor is electrically connected to the first controller, and an emitter of the first transistor is electrically connected to the first controller, the second clamp circuit, and a gate of the main switch.

6. The drain-source voltage detection circuit according to claim 2, wherein the second clamping circuit comprises a second transistor and a first switch, an emitter of the second transistor is electrically connected to one end of the first switch, the other end of the first switch is grounded, a base of the second transistor is electrically connected to the first controller, and a collector of the second transistor is electrically connected to the first controller, the first clamping circuit, and a gate of the main switch transistor, respectively.

7. The drain-source voltage detection circuit according to any one of claims 2 to 6, further comprising a first current mirror circuit and a second current mirror circuit, wherein one end of the first current mirror circuit is electrically connected to the first controller, the other end of the first current mirror circuit is electrically connected to the gates of the first clamp circuit and the main switch transistor, respectively, one end of the second current mirror circuit is electrically connected to the first controller, the other end of the second current mirror circuit is electrically connected to the gates of the second clamp circuit and the main switch transistor, respectively, and the first current mirror circuit and the second current mirror circuit are configured to mirror the first coupling signal and transmit the first coupling signal to the first controller.

8. The drain-source voltage detection circuit according to claim 7, wherein the first current mirror circuit includes a third transistor, the second current mirror circuit includes a fourth transistor, a base of the third transistor is commonly grounded to one end of the first clamping circuit, a collector of the third transistor is electrically connected to the first controller, and an emitter of the third transistor is electrically connected to a gate of the main switching tube;

the base electrode of the fourth triode is electrically connected with the grid electrode of the main switching tube and one end of the second clamping circuit respectively, the collector electrode of the fourth triode is electrically connected with the first controller, and the emitter electrode of the fourth triode and the other end of the second clamping circuit are grounded together.

9. The drain-source voltage detection circuit of claim 7, wherein the drain-source voltage detection circuit further comprises a first processing circuit and a second processing circuit;

10. The drain-source voltage detection circuit of claim 9, wherein the first processing circuit comprises a first current source, a first hysteresis comparator, a first inverter, a first flip-flop, and a second inverter;

11. The drain-source voltage detection circuit of claim 10, wherein the second processing circuit comprises a second current source, a second hysteresis comparator, a second flip-flop, a third inverter, and a first and gate;

the input end of the third inverter is used for receiving a second driving signal, and the second driving signal is generated by a single-trigger circuit through the inverted signal of the first driving signal.

12. The drain-source voltage detection circuit of claim 2, wherein the first clamp circuit comprises a first field effect transistor, a first comparator, and a third current source;

13. The drain-source voltage detection circuit according to claim 2 or 12, wherein the second clamp circuit comprises a second field effect transistor, a second comparator;

14. A drain-source voltage detection method applied to the drain-source voltage detection circuit according to any one of claims 2 to 13, the method comprising:

15. The method of claim 14, wherein determining whether the inductor current has dropped to zero based on the first current and a first predetermined threshold comprises:

16. The method of claim 14, wherein determining whether the drain voltage enters a resonant valley based on the first current and the first preset threshold comprises:

17. The method according to any one of claims 14-16, further comprising:

18. The method of claim 17, wherein determining whether the drain voltage is off a resonant valley based on the second current and a second preset threshold comprises:

19. The utility model provides a drain-source voltage detection circuit, is applied to the switching converter, the switching converter includes main switch tube, inductance, the grid leakage electric capacity of main switch tube and the drive circuit of main switch tube, drive circuit's drive end with the grid electric connection of main switch tube, its characterized in that, drain-source voltage detection circuit includes: a third current mirror circuit and a second controller;