JP2010200560A - Gate driver circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To switch a semiconductor switching element for a power at a high speed by preventing the delay of a switching with the charge and discharge of the input capacity of a gate terminal. <P>SOLUTION: A first charge-discharge capacitor C1 is charged when an IGBT1 is at off, and an input capacity Ci at a gate terminal 1g for the IGBT1 is turned on quickly by an instantaneous initial charge by a high voltage in the forward direction synthesizing a power-supply voltage through a positive terminal P and the charging voltage of the first charge-discharge capacitor C1 in series when the IGBT1 is switched from off to on. A second charge-discharge capacitor C2 is charged when the IGBT1 is off, and the input capacity Ci is turned off quickly by an instantaneous initial discharge by the high voltage in the reverse direction synthesizing the power-supply voltage through a negative terminal N and the charging voltage of the second charge-discharge capacitor C2 in series when the IGBT1 is switched from on to off quickly. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a gate drive circuit that controls a gate voltage of a voltage-controlled power semiconductor switching element, and more particularly to improvement of switching characteristics.

  2. Description of the Related Art Conventionally, voltage-controlled power semiconductor switching elements such as IGBTs and FETs are used for motor-driven main circuits (power supply bridge circuits and the like) of electric vehicles and the like, and control circuits (PWM control circuits and the like).

  This type of power semiconductor switching element has a non-negligible input capacitance (gate capacitance) at the gate terminal (control terminal). This input capacitance is charged / discharged by switching the power semiconductor switching element from off to on and vice versa. Then, due to charging / discharging of the input capacitance, power loss occurs or switching delay occurs, and the switching characteristics of the power semiconductor switching element deteriorate.

  Therefore, in the FET which is an example of this type of power semiconductor switching element, when the FET is turned off, a part of the electric charge charged in the input capacitance (gate capacitance) of the gate terminal is accumulated in the capacitor, and the FET It is proposed to reduce the power loss associated with the discharge of the input capacitor by using the charge accumulated in the capacitor for the on-control of the input capacitor (see, for example, Patent Document 1 (abstract, See claim 1, paragraphs [0020]-[0029], FIGS. 1-5, etc.).

JP 2005-12972 A

  As in the invention described in Patent Document 1, a part of the electric charge charged in the input capacitance of the gate terminal is accumulated in the capacitor during the off control, and the electric charge accumulated in the capacitor is stored in the input capacitance during the on control. Even if this is used for charging, it is impossible to prevent the switching delay of this type of power semiconductor switching element such as FET due to charging / discharging of the input capacitance.

  FIG. 7 shows an IGBT 100 as an example of this kind of power semiconductor switching element, and the IGBT 100 has a gate terminal 100g as a control terminal, a collector terminal 100c as an output terminal, and an emitter terminal 100e. The gate terminal 100g is connected to the positive terminal P of the DC gate power supply through the emitter and collector of the transistor Qa, and is connected to the grounded negative terminal N of the gate power supply through the collector and emitter of the transistor Qb. ing.

  When the IGBT 100 is turned on (opened), the transistors Qa and Qb are controlled so that the transistor Qa is turned on and the transistor Qb is turned off, and the gate voltage Vg of the positive terminal P, for example, + 5V or + 10V rectangular wave is applied to the gate terminal. Applied to 100 g, the IGBT 100 is turned on. When the IGBT 100 is turned off (opened), the transistor Qa is turned off and the transistor Qb is turned on, and the gate voltage Vg disappears and the IGBT 100 is turned off.

  The IGBT 100 is generally switched at a frequency of about 20 KHz or less by the switching of the transistors Qa and Qb in opposite phases. In the case of FIG. 7, the power supply from the battery 200 of the electric vehicle to the driving motor 300 is interrupted by switching of the IGBT 100, for example.

  The input terminal (gate capacity) Ci described above is parasitic on the gate terminal 100g of the IGBT 100, and switching of the IGBT 100 is delayed by charging / discharging of the input capacity Ci based on the gate voltage Vg.

  FIG. 8 is a waveform diagram showing a switching delay based on the input capacitance Ci of the IGBT 100. When the 5V or 10V rectangular wave gate voltage Vg in FIG. 8A is applied to the gate 100g, the gate voltage Vg At the rising edge, the input capacitor Ci is charged and then the IGBT 100 is turned on. At the falling edge of the gate voltage Vg, the input capacitor Ci is discharged and then the IGBT 100 is turned off. Therefore, the rise and fall of the voltage (gate-source voltage) at the gate terminal 100g is delayed, and the switching of the IGBT 100 is delayed from the change in the gate voltage Vg. At this time, the voltage between the collector and the emitter of the IGBT 100 changes from a low level (L) to a high level (H), and vice versa, as shown in FIG. The collector-emitter current (output current) of the IGBT 100 also changes with a constant time constant as shown in FIG. For this reason, when switching is performed, a large power loss occurs in the shaded portion of FIG.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a novel gate drive circuit that prevents switching delay associated with charging / discharging of an input capacitance of a gate terminal and switches a power semiconductor switching element at high speed.

  In order to achieve the above object, a gate driving circuit of the present invention is a gate driving circuit for controlling a gate voltage of a voltage-controlled power semiconductor switching element, and includes one power supply terminal and the power semiconductor switching element. An on-control semiconductor switching element that opens and closes between the gate terminals of the first and second gates, an off-control semiconductor switching element that switches reversely to the on-control semiconductor switching elements and opens and closes between the gate and the other power supply terminal, A first charge that initially charges the first charge / discharge capacitor with a current flowing through the off-control semiconductor switching element when the second charge / discharge capacitor and the power semiconductor switching element are off. And the power semiconductor switching element switches from off to on. A forward voltage obtained by synthesizing the voltage of the one power supply terminal via the semiconductor switching element and the charge voltage of the first charge / discharge capacitor in series is applied to the gate terminal to initially set the input capacitance of the gate terminal. A gate charging semiconductor switching element to be charged, and a second charge for charging the second charge / discharge capacitor by a current flowing through the on-control semiconductor switching element when the power semiconductor switching element is on. And when the power semiconductor switching element switches from on to off, the voltage of the other power supply terminal via the off control semiconductor switching element and the charging voltage of the second charge / discharge capacitor are connected in series. A gate discharge semiconductor that initially discharges the input capacitance by applying a reverse voltage synthesized to the gate terminal Is characterized in that a switching device (claim 1).

  In the case of the gate drive circuit according to the first aspect of the present invention, the first charging path means generates a first charge based on the current flowing through the off-control semiconductor switching element when the power semiconductor switching element is off. Charge the charge / discharge capacitor. When the power semiconductor switching element switches from off to on, the gate charging semiconductor switching element is turned on, and the power supply voltage via one power supply terminal and the charge voltage of the first charge / discharge capacitor are combined in series. The input capacitance at the gate terminal of the power semiconductor switching element is initially charged by the forward high voltage. When the on-control semiconductor switching element is turned on based on this initial charge, the forward voltage of one power supply terminal applied to the gate terminal of the power semiconductor switching element via the on-control semiconductor switching element causes the input capacitance to Without waiting for charging, the power semiconductor switching element is quickly switched on from off to on.

  Further, when the power semiconductor switching element is turned on, the second charge path means charges the second charge / discharge capacitor based on the current flowing through the on-control semiconductor switching element. When the power semiconductor switching element switches from on to off, the gate discharge semiconductor switching element is turned on, and the power supply voltage via the other power supply terminal and the charge voltage of the second charge / discharge capacitor are combined in series. The input voltage at the gate terminal of the power semiconductor switching element is instantaneously discharged by the high voltage in the reverse direction. When the off-control semiconductor switching element is turned on based on this initial discharge, the reverse power (or ground level) voltage of the other power supply terminal applied to the gate terminal of the power semiconductor switching element via the off-control semiconductor switching element. The power semiconductor switching element is quickly switched from on to off without waiting for the discharge of the input capacitance.

  Therefore, it is possible to provide a novel gate driving circuit capable of preventing the switching delay associated with charging / discharging of the input capacitance of the gate terminal and switching the power semiconductor switching element at high speed.

It is a connection diagram of the gate drive circuit of the 1st Embodiment of this invention. It is a connection diagram of the gate drive circuit of the 2nd Embodiment of this invention. It is a connection diagram of the gate drive circuit of the 3rd Embodiment of this invention. It is a connection diagram of the gate drive circuit of the 4th Embodiment of this invention. It is a connection diagram of the gate drive circuit of the 5th Embodiment of this invention. It is a connection diagram of the gate drive circuit of the 6th Embodiment of this invention. It is explanatory drawing of the general gate drive of IGBT. It is a wave form diagram explaining the delay of switching of IGBT of FIG.

  Next, in order to describe the present invention in more detail, embodiments will be described in detail with reference to FIGS.

(First embodiment)
A first embodiment in which the power semiconductor switching element is an IGBT and its input capacitance is charged and discharged with a double voltage will be described with reference to FIG.

(Constitution)
FIG. 1 shows the connection of the gate drive circuit of this embodiment. Reference numeral 1 in FIG. 1 denotes an IGBT (voltage-controlled power semiconductor switching element of the present invention) corresponding to the IGBT 100 of FIG. 7, and is input to the gate terminal 1g. Capacitance (gate capacitance) Ci is parasitic. Reference numerals 2 and 3 denote motors and batteries corresponding to the motor 200 and the battery 300 in FIG. In addition, 1c and 1e are the collector terminal and emitter terminal of IGBT1.

  Q1 is a PNP transistor as an on-control semiconductor switching element of the present invention, and opens and closes between the positive terminal (one power supply terminal of the present invention) P and the gate terminal 1g of the IGBT1. Q2 is an NPN transistor serving as an off-control semiconductor switching element of the present invention, and switches reversely to the transistor Q1 to open and close between the gate 1g and the negative terminal (the other power supply terminal of the present invention) N. The collector of the transistor Q1 is connected to the gate terminal 1g via the anode and cathode of the diode D1 for preventing backflow. The collector of the transistor Q2 is connected to the gate terminal 1g via the cathode and anode of the backflow preventing diode D2. Further, the transistors Q1 and Q2 are switched in opposite directions by a reverse-phase switching pulse from a gate control unit (not shown).

  C1 is a first charge / discharge capacitor, one end (+ side) of which is connected to the positive terminal P via the cathode and anode of the backflow prevention diode D3, and the other end (− side) of the backflow prevention diode D4. Are connected to the collector of the transistor Q1 through the cathode and anode of the transistor Q1. C2 is a second charging / discharging capacitor, one end (+ side) of which is connected to the cathode of the diode D4, and is connected to the collector of the transistor Q2 via the anode and cathode of the backflow preventing diode D5, and the other end ( The negative side is connected to the negative terminal N through the anode and cathode of the backflow preventing diode D6. The charge / discharge capacitors C1 and C2 have a maximum capacity determined by the ratio of the gate breakdown voltage of the IGBT 1 that is a power semiconductor switching element (control target) and the gate power supply voltage between the terminals P and N. When the gate breakdown voltage and the gate power supply voltage are equal, the maximum capacities of the charge / discharge capacitors C1 and C2 are equal to or less than the input capacity Ci of the gate terminal 1g of the IGBT1. When the gate breakdown voltage is 1 to 2 times the gate power supply voltage, the maximum capacity of the charge / discharge capacitors C1 and C2 is less than or equal to the input capacity Ci × (square of y), where y is the ratio of the gate breakdown voltage to the gate power supply voltage. is there. Furthermore, when the gate breakdown voltage is twice or more the gate power supply voltage, the charge / discharge capacitors C1 and C2 are not limited in maximum capacity.

  Q3 is a PNP transistor as a semiconductor switching element for gate charging according to the present invention, the base is connected to the positive terminal P via the resistor R1, the emitter is connected to one end of the first charge / discharge capacitor C1, and the collector is It is connected to the gate terminal 1g. The transistor Q3 gates a forward voltage obtained by combining the voltage of the positive terminal P via the transistor Q1 and the charging voltage of the first charging / discharging capacitor C1 in series when the IGBT 1 switches from OFF to ON. Applying to the terminal 1g, the input capacitor Ci is initially charged.

  Q4 is an NPN transistor as a semiconductor switching element for gate discharge of the present invention, the base is connected to the negative terminal N via the resistor R2, the collector is connected to the gate terminal 1g, and the emitter is the first charge / discharge capacitor. It is connected to one end of C1. Then, when the IGBT 1 switches from on to off, the transistor Q4 has a gate terminal with a reverse voltage obtained by combining the voltage of the negative terminal N via the transistor Q2 and the charging voltage of the second charge / discharge capacitor C2 in series. Applied to 1 g, the input capacitor Ci is initially discharged.

  When the IGBT 1 is turned off by the path of the positive terminal P, the diode D3, the first charging / discharging capacitor C1, the diode D5, the transistor Q2, and the negative terminal N, the first charging / discharging is performed by the current flowing through the transistor Q2. First charging path means for initially charging the capacitor C1 is formed. Further, when the IGBT 1 is turned on by the path of the positive terminal P, the transistor Q1, the diode D4, the second charge / discharge capacitor C2, the diode D6, and the negative terminal N, the second current is caused by the current flowing through the transistor Q1. Second charging path means for charging the charging / discharging capacitor C2 is formed.

(Operation)
(1) When IGBT1 is off Transistor Q1 is off and transistor Q2 is on. The first charge / discharge capacitor C1 is initially charged to the voltage of the gate power supply in the direction shown in the figure by the current flowing through the transistor Q2 of the first charging path means. Since the diode D3 is turned on, the transistor Q3 is reverse-biased and turned off. Since the transistors Q1 and Q3 are turned off, the input capacitance Ci of the gate terminal 1g is in a discharged state.

(2) When IGBT1 switches from OFF to ON Transistor Q1 switches from OFF to ON, and transistor Q2 switches from ON to OFF. At this time, the voltage of the gate power supply at the positive terminal P is serially combined in the forward direction with the charge voltage of the first charge / discharge capacitor C1 via the transistor Q1 and the diode D4, and a voltage (double voltage) twice that of the gate power supply is obtained. It is formed. The diode D3 is biased in the reverse direction and turned off, and the transistor Q3 is biased in the forward direction by the double voltage and turned on. Further, the double voltage is applied to the gate terminal 1g via the transistor Q3, and the input capacitance Ci is instantly charged with the double voltage instantaneously. The transistors Q1 to Q4 are small signal transistors having a very small base input capacitance, and a switching delay due to the input capacitance can be ignored.

  When the transistor Q1 is turned on by the initial charging of the input capacitance Ci to the voltage of the gate power supply, the voltage of the gate power supply at the positive terminal P via the transistor Q1 is almost unchanged without charging the input capacitance Ci. A voltage is applied to the gate of the IGBT 1 and the IGBT 1 is quickly switched on without delay. When the input capacitor Ci is initially charged to the voltage of the gate power supply, the charge stored in the first charge / discharge capacitor C1 is consumed, the transistor Q3 cannot be forward biased, and the transistor Q3 is turned off. It becomes a state. After this, the charge necessary for charging the gate terminal 1g of the IGBT 1 is supplied through the diode D1.

(3) When IGBT1 is on Transistor Q1 is on and transistor Q2 is off. The second charge / discharge capacitor C2 is initially charged to the gate power supply voltage in the direction shown in the figure by the current flowing through the transistor Q1 of the second charge path means. Since the transistor Q1 is on, the input capacitance Ci of the gate terminal 1g is maintained in a charged state. Since the diode D6 is turned on, the transistor Q4 is reverse-biased and turned off.

(4) When IGBT1 switches from on to off Transistor Q1 switches from on to off, and transistor Q2 switches from off to on. At this time, the charged second charge / discharge capacitor C2 is forwardly connected to the negative terminal N via the diode D5 and the transistor Q2, and the voltage of the gate power supply and the charge voltage of the charge / discharge capacitor C2 are combined in series. A voltage doubler in the reverse direction is formed. The diode D6 is biased in the reverse direction and turned off, and the transistor Q4 is biased in the forward direction and turned on by the double voltage in the reverse direction. This double voltage in the reverse direction is applied to the gate terminal 1g via the transistor Q4, and the input capacitance Ci is instantaneously discharged instantaneously.

  When the input capacitor Ci is initially discharged, without waiting for the discharge of the input capacitor Ci, the gate terminal 1g immediately becomes the ground voltage of the negative terminal N through the diode D2 and the transistor Q2, and when the transistor Q2 is turned on, the IGBT1 Will switch off quickly without delay.

  By repeating the above operations (1) to (4), the switching of the IGBT 1 can be prevented at high speed by preventing the switching delay associated with the charging / discharging of the input capacitance Ci of the gate terminal 1g. It is possible to reduce the power loss accompanying the switching delay. In addition, since the switching time of on / off of the IGBT 1 is shortened, the surge absorption circuit can be reduced, and the operating frequency range is expanded. Furthermore, since power loss is reduced, the IGBT 1 and its radiator can be downsized. Note that a double voltage is applied to the gate terminal 1g at the moment when the energy of the input capacitance Ci is discharged, but the first charge / discharge capacitor C1 and the second charge / discharge capacitor C2 have only energy corresponding to the input capacitance Ci. Since it is not stored and is offset by the resistance of each component wiring, the insulation of the gate terminal 1g is not broken by the application of the double voltage. Further, the time during which the double voltage is applied to the gate terminal 1g varies depending on the capacitances of the first and second charge / discharge capacitors C1 and C2. As the capacity of the first and second charge / discharge capacitors C1 and C2 decreases, the time during which the double voltage is applied to the gate terminal 1g is shortened, and the effect of charging the input capacity Ci is reduced (weak). For this reason, the capacities of the first and second charge / discharge capacitors C1 and C2 are set so that the charging effect of the input capacitor Ci is enhanced and the switching delay of the IGBT 1 due to the charge / discharge of the input capacitor Ci is prevented as much as possible. It is desirable to do.

(Second Embodiment)
A second embodiment in which the power semiconductor switching element is an FET and its input capacitance is charged and discharged at a double voltage will be described with reference to FIG.

  FIG. 2 shows the connection of the gate drive circuit of this embodiment, and the same reference numerals as those in FIG. 1 denote the same or corresponding elements.

  1 differs from FIG. 1 in that first, the IGBT 1 in FIG. 1 is an enhancement-type n-channel MOSFET (the voltage-controlled power semiconductor switching element of the present invention, hereinafter the FET to be controlled). This is a point replaced with 10. Second, the transistor Q1 in FIG. 1 is replaced with an enhancement type p-channel MOSFET (on-control semiconductor switching element of the present invention, hereinafter referred to as an on-control FET) 11, and the transistor Q2 in FIG. The n-channel MOSFET (the off-control semiconductor switching element of the present invention, hereinafter referred to as an off-control FET) 12 is replaced.

  In addition, 10d, 10s, and 10g of FIG. 2 are the drain terminal of the control object FET10, a source terminal, and a gate terminal. The configurations of the motor 2 and the battery 3 in FIG. 1 connected to the drain terminal 10d are not shown. The ON control FET 11 has a source terminal connected to the positive terminal P, and the OFF control FET 12 has a source terminal connected to the negative terminal N. The on control FET 11 and the off control FET 12 are also small-signal FETs having extremely small gate input capacitances, and switching delays due to the input capacitances can be ignored.

  Then, the first and second charge / discharge capacitors C1 and C2 are charged and discharged by switching of the on control FET 11 and the off control FET 12, so that the operation of this embodiment is the same as that of the first embodiment.

(1) When the control target FET 10 is off The on control FET 11 is off and the off control FET 12 is on. The first charge / discharge capacitor C1 is initially charged to the voltage of the gate power supply in the direction shown in the figure by the current flowing through the off control FET 12 of the first charge path means.

(2) When the control target FET 10 switches from off to on The on control FET 11 switches from off to on, and the off control FET 12 switches from on to off. At this time, the voltage of the gate power supply at the positive terminal P is serially combined in the forward direction with the charge voltage of the first charge / discharge capacitor C1 via the on-control FET 11 and the diode D4, and is twice the voltage (double voltage) of the gate power supply. Formed. Since this double voltage (high voltage) is applied to the gate terminal 1g via the transistor Q3 and the input capacitance Ci is instantaneously charged with the double voltage, when the on-control FET 11 is turned on, the control target FET 10 is quickly and without delay. Switch on.

(3) When the control target FET 10 is on The on control FET 11 is on and the off control FET 12 is off. Then, the second charge / discharge capacitor C2 is initially charged to the voltage of the gate power supply in the direction shown in the figure by the current flowing through the ON control FET 11 of the second charge path means.

(4) When the control target FET 10 switches from on to off The on control FET 11 switches from on to off, and the off control FET 12 switches from off to on. At this time, the charged second charging / discharging capacitor C2 is connected to the negative terminal N in the forward direction via the OFF control FET 12, and the reverse direction in which the voltage of the gate power supply and the charging voltage of the charging / discharging capacitor C2 are combined in series. Is applied to the gate terminal 1b, and the input capacitance Ci is instantaneously initially discharged. Therefore, when the off control FET 12 is turned on, the controlled FET 10 is quickly switched and turned off without delay.

  By repeating the operations (1) to (4) described above, it is possible to prevent the switching delay associated with charging / discharging of the input capacitance Ci of the gate terminal 1g and to switch the control target FET 10 at high speed. The same effect as in the first embodiment can be obtained.

(Third embodiment)
A third embodiment as an application example of the second embodiment in which the input capacitance Ci of the control target FET 10 is charged and discharged at a triple voltage will be described with reference to FIG.

  FIG. 3 shows the connection of the gate drive circuit of this embodiment, and the same reference numerals as those in FIG. 2 denote the same or corresponding components.

  3 differs from FIG. 2 in the first place, as shown in the part surrounded by the broken lines α1 and β1 in FIG. 3, the first charge / discharge capacitor C1, the transistor Q3, and the backflow prevention The on-side configuration of the diode D3 and resistor R1 and the off-side configuration of the second charge / discharge capacitor C2, transistor Q4, backflow prevention diode D6, and resistor R2 in FIG. Is a point. Second, in order to charge the two first charging / discharging capacitors C1 simultaneously, a backflow prevention diode Dα is added to the first charging path means, and the two second charging / discharging capacitors C2 are simultaneously connected. In order to charge, the backflow prevention diode Dβ is added to the second charging path means.

  In the case of this embodiment, when the control target FET 10 is turned off, the two first charge / discharge capacitors C1 are gated in the direction shown in the figure by the current flowing through the off control FET 12 of the first charging path means. Initially charged to the voltage of the power supply. When the control target FET 10 switches from OFF to ON, the voltage of the gate power supply at the positive terminal P is serially combined in the forward direction with the charge voltage of the first charge / discharge capacitor C1 via the ON control FET 11 and the diode D4. Further, the voltage synthesized in series is serially synthesized in the forward direction with the charging voltage of the other first charging / discharging capacitor C1 via the transistor Q3, and a voltage three times that of the gate power supply (three times the voltage) is formed. The This triple voltage (high voltage) is applied to the gate terminal 1g via the transistor Q3, and the input capacitor Ci is initially charged more rapidly. Therefore, when the on-control FET 11 is turned on, the control target FET 10 is switched on more rapidly and turned on.

  In addition, when the control target FET 10 is on, the two second charge / discharge capacitors C2 become the voltage of the gate power supply in the direction shown in the figure by the current flowing through the on control FET 11 of the second charge path means. Initial charging. When the control target FET 10 is switched from on to off, a reverse triple voltage obtained by combining the voltage of the gate power supply and the charging voltages of the two second charge / discharge capacitors C2 in series is input via the input capacitance Ci. Is applied to the gate terminal 1b, and the input capacitor Ci is initially discharged more rapidly. Therefore, when the off control FET 12 is turned on, the control target FET 10 is switched more quickly and turned off.

(Fourth embodiment)
A fourth embodiment in which the input capacitance Ci of the control target FET 10 is charged and discharged with a quadruple voltage will be described with reference to FIG.

  FIG. 4 shows the connection of the gate drive circuit of this embodiment, and the same reference numerals as those in FIG. 3 indicate the same or corresponding components.

  4 differs from FIG. 3 in the first place, as shown in the part surrounded by the broken lines α2 and β2 in FIG. 4, the first charge / discharge capacitor C1, the transistor Q3, and the backflow prevention The on-side configuration of the diode D3 and the resistor R1 and the off-side configuration of the second charge / discharge capacitor C2, the transistor Q4, the backflow prevention diode D6, and the resistor R2 in FIG. Is a point. Second, in order to charge the three first charging / discharging capacitors C1 simultaneously, backflow prevention diodes Dα1 and Dα2 corresponding to the diode Dα of FIG. In order to charge the second charging / discharging capacitor C2 simultaneously, backflow prevention diodes Dβ1 and β2 corresponding to the diode Dβ of FIG. 3 are added to the second charging path means.

  In the case of this embodiment, when the control target FET 10 is turned off, the three first charge / discharge capacitors C1 are gated in the direction shown in the figure by the current flowing through the off control FET 12 of the first charging path means. Initially charged to the voltage of the power supply. When the control target FET 10 switches from OFF to ON, the voltage of the gate power supply at the positive terminal P is serially connected in series with the charge voltage of the first first charge / discharge capacitor C1 via the ON control FET 11 and the diode D4. Further, the combined voltage is further combined in series in the forward direction with the charging voltage of the second and third first charge / discharge capacitors C1 via the first and second transistors Q3, and the gate power supply A quadruple voltage (fourfold voltage) is formed. This quadruple voltage (high voltage) is applied to the gate terminal 1g via the third transistor Q3, and the input capacitor Ci is initially charged more rapidly. Therefore, when the on-control FET 11 is turned on, the control target FET 10 is switched on more rapidly and turned on.

  In addition, when the control target FET 10 is on, the current flowing through the on control FET 11 of the second charging path means causes the three second charge / discharge capacitors C2 to be at the voltage of the gate power supply in the direction shown in the figure. Initial charging. When the control target FET 10 switches from on to off, a reverse quadruple voltage obtained by combining the voltage of the gate power supply and the charge voltages of the three second charge / discharge capacitors C2 in series is input via the input capacitance Ci. Is applied to the gate terminal 1b, and the input capacitor Ci is initially discharged more rapidly. Therefore, when the off control FET 12 is turned on, the control target FET 10 is switched more quickly and turned off.

(Fifth embodiment)
A fifth embodiment in which the input capacitance Ci of the control target FET 10 is charged and discharged with a fivefold voltage will be described with reference to FIG.

  FIG. 5 shows the connection of the gate drive circuit of this embodiment, and the same reference numerals as those in FIG. 4 indicate the same or corresponding components.

  5 is different from FIG. 4 in the first place, as shown in the portion surrounded by the broken lines α3 and β3 in FIG. 5, the first charge / discharge capacitor C1, the transistor Q3, and the backflow prevention The on-side configuration of the diode D3 and the resistor R1 and the off-side configuration of the second charge / discharge capacitor C2, the transistor Q4, the backflow prevention diode D6, and the resistor R2 in FIG. Is a point. Second, in order to charge the four first charge / discharge capacitors C1 simultaneously, a backflow prevention diode Dα3 is further added to the first charge path means, and the four second charge / discharge capacitors C2 are connected. In order to charge at the same time, a diode Dβ3 for preventing backflow is further added to the second charging path means.

  In the case of this embodiment, when the control target FET 10 is turned off, the four first charge / discharge capacitors C1 are gated in the direction shown in the drawing by the current flowing through the off control FET 12 of the first charging path means. Initially charged to the voltage of the power supply. When the control target FET 10 is switched from OFF to ON, the voltage of the gate power supply at the positive terminal P is serially combined in the forward direction with the charge voltage of the four charge / discharge capacitors C1, and the voltage (5 times the gate power supply) Double voltage) is formed. The quadruple voltage (high voltage) is applied to the gate terminal 1g via the fourth transistor Q3, whereby the input capacitor Ci is initially charged more rapidly. Therefore, when the on-control FET 11 is turned on, the control target FET 10 is switched on more rapidly and turned on.

  Further, when the control target FET 10 is on, the four second charge / discharge capacitors C2 are set to the voltage of the gate power supply in the direction shown in the figure by the current flowing through the on control FET 11 of the second charge path means. Initial charging. When the control target FET 10 switches from on to off, a reverse five-fold voltage obtained by combining the voltage of the gate power supply and the charging voltages of the four second charging / discharging capacitors C2 in series is input via the input capacitance Ci. Is applied to the gate terminal 1b, and the input capacitor Ci is initially discharged more rapidly. Therefore, when the off control FET 12 is turned on, the control target FET 10 is switched more quickly and turned off.

(Sixth embodiment)
A sixth embodiment in which the input capacitance Ci of the control target FET 10 is charged and discharged with a 6-fold voltage will be described with reference to FIG.

  FIG. 6 shows the connection of the gate drive circuit of this embodiment, and the same reference numerals as those in FIG. 5 denote the same or corresponding components.

  The configuration of FIG. 6 differs from that of FIG. 5 in the first place, as shown in the portion surrounded by the broken lines α4 and β4 in FIG. 6, the first charge / discharge capacitor C1, the transistor Q3, and the backflow prevention The on-side configuration of the diode D3 and the resistor R1 and the off-side configuration of the second charge / discharge capacitor C2, the transistor Q4, the backflow preventing diode D6, and the resistor R2 in FIG. Is a point. Secondly, in order to charge the five first charge / discharge capacitors C1 simultaneously, a backflow prevention diode Dα4 is further added to the first charge path means, and the five second charge / discharge capacitors C2 are connected. In order to charge at the same time, a diode Dβ4 for preventing backflow is further added to the second charging path means.

  In the case of this embodiment, when the control target FET 10 is turned off, the five first charge / discharge capacitors C1 are gated in the direction shown in the figure by the current flowing through the off control FET 12 of the first charging path means. Initially charged to the voltage of the power supply. When the control target FET 10 switches from OFF to ON, the voltage of the gate power supply at the positive terminal P is serially combined in the forward direction with the charge voltage of the five charge / discharge capacitors C1 to obtain a voltage six times that of the gate power supply (6 Double voltage) is formed. By applying this 6-fold voltage (high voltage) to the gate terminal 1g via the fifth transistor Q3, the input capacitor Ci is initially charged more rapidly. Therefore, when the on-control FET 11 is turned on, the control target FET 10 is switched on more rapidly and turned on.

  Further, when the control target FET 10 is on, the five second charge / discharge capacitors C2 are set to the voltage of the gate power supply in the direction shown in the figure by the current flowing through the on control FET 11 of the second charge path means. Initial charging. When the control target FET 10 is switched from on to off, a reverse six-fold voltage obtained by combining the voltage of the gate power supply and the charging voltages of the five second charge / discharge capacitors C2 in series is input via the input capacitance Ci. Is applied to the gate terminal 1b, and the input capacitor Ci is initially discharged more rapidly. Therefore, when the off control FET 12 is turned on, the control target FET 10 is switched more quickly and turned off.

  The present invention is not limited to the above-described embodiments, and various modifications other than those described above can be made without departing from the spirit thereof. For example, the power semiconductor switching element is A semiconductor switching element having any characteristics may be used. In addition, the polarity of the other power supply terminal may be opposite to that of each embodiment. In this case, depending on the polarity of both power supply terminals, the on-control semiconductor switching element, the off-control semiconductor switching element, etc. are npn, pnp (Or n channel, p channel), and the directions of the diodes D1 to D6 and Dα1 to Dβ may be determined. Furthermore, it goes without saying that the transistors Q3 and Q4 of each embodiment may be formed of FETs.

  Next, as is apparent from the configurations of the third to sixth embodiments, the gate drive circuit of the present invention is configured to charge / discharge the input capacitance Ci of the control target FET 10 with a high voltage of 7 times or more, for example. Of course, as the number of voltage doublers increases, the number of components increases, resulting in an increase in size and cost. Therefore, in practice, it is preferable to configure the voltage to 6 times the voltage (5 levels) or less.

  The present invention can be applied to gate drive circuits for voltage-controlled power semiconductor switching elements for various applications.

1 IGBT
1g Gate terminal 10 FET to be controlled
11 ON control FET
12 OFF control FET
C1 First charge / discharge capacitor C2 Second charge / discharge capacitor Ci Input capacitances D1 to D6, Dα1 to Dβ Diodes Q1 to Q4 Transistor P Positive terminal N Negative terminal

Claims (1)

A gate drive circuit for controlling a gate voltage of a voltage-controlled power semiconductor switching element,
An on-control semiconductor switching element that opens and closes between one power supply terminal and the gate terminal of the power semiconductor switching element;
An off-control semiconductor switching element that switches reversely to the on-control semiconductor switching element to open and close between the gate and the other power supply terminal;
First and second charge / discharge capacitors;
First charging path means for initially charging the first charging / discharging capacitor with a current flowing through the off-control semiconductor switching element when the power semiconductor switching element is off;
When the power semiconductor switching element switches from off to on, the voltage of the one power supply terminal via the on control semiconductor switching element and the charge voltage of the first charge / discharge capacitor are combined in series. Applying a voltage in the direction to the gate terminal to initially charge the input capacitance of the gate terminal;
Second charging path means for charging the second charging / discharging capacitor with a current flowing through the on-control semiconductor switching element when the power semiconductor switching element is on;
When the power semiconductor switching element switches from on to off, the reverse of the voltage of the other power supply terminal and the charging voltage of the second charge / discharge capacitor that are combined in series via the off control semiconductor switching element. A gate driving circuit comprising: a gate switching semiconductor switching element that applies initial voltage to the gate terminal to initially discharge the input capacitance.

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