CN216751537U - Direct circuit applied to buck converter - Google Patents
Direct circuit applied to buck converter Download PDFInfo
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- CN216751537U CN216751537U CN202121237146.XU CN202121237146U CN216751537U CN 216751537 U CN216751537 U CN 216751537U CN 202121237146 U CN202121237146 U CN 202121237146U CN 216751537 U CN216751537 U CN 216751537U
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Abstract
The utility model provides a through circuit applied to a buck converter, which comprises: a first subcircuit; a second subcircuit connected to the first subcircuit. The first sub-circuit includes: a logic controller; the input end of the first buffer is connected to the first output end of the logic controller; and the input end of the second buffer is connected to the second output end of the logic controller. According to the NMOS through circuit and the structure applied to the BUCK converter, the BST voltage of the BUCK is used as the starting voltage required by the charge pump to maintain the NMOS through tube, the NMOS through power tube can be driven, the common PMOS through power tube is replaced, and the production cost of the through circuit is reduced.
Description
Technical Field
The utility model relates to the field of circuits, in particular to a direct-through circuit applied to a buck converter.
Background
Most of the existing buck converters with the direct-current function are realized by driving a PMOS (P-channel metal oxide semiconductor) tube, as shown in FIG. 1, when a CT (current transformer) signal is enabled, a QP (quantum dots) is opened through level shift and driving, so that VIN energy is directly transmitted to VOUT through the QP, and the driving of the QP is based on a floating voltage rail between floating _ GND and VIN; the PMOS through circuit is relatively easy to realize, and the PMOS power tube is relatively expensive compared with the NMOS power tube, so that the problem of high production cost exists.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a direct circuit applied to a buck converter.
The utility model aims to solve the problem of high production cost of a direct-through circuit of the conventional buck converter.
Compared with the prior art, the technical scheme and the beneficial effects of the utility model are as follows:
a pass-through circuit for use in a buck converter, comprising: a first subcircuit; a second subcircuit connected to the first subcircuit. The first sub-circuit includes: a logic controller; the input end of the first buffer is connected to the first output end of the logic controller; and the input end of the second buffer is connected to the second output end of the logic controller.
As a further improvement, the first subcircuit further includes: the anode of the first diode is connected to the working voltage end, and the cathode of the first diode is connected to the first end of the first buffer; the drain electrode of the first MOS tube is connected to an input voltage end, the grid electrode of the first MOS tube is connected to the output end of the first buffer, and the source electrode of the first MOS tube is connected to the second end of the first buffer; the drain electrode of the second MOS tube is connected to the source electrode of the first MOS tube, the grid electrode of the second MOS tube is connected to the output end of the second buffer, the source electrode of the second MOS tube is connected to the second end of the second buffer, and the first end of the second buffer is connected to the working voltage end.
As a further improvement, the first sub-circuit further includes: one end of the first capacitor is connected to the cathode of the first diode, and the other end of the first capacitor is connected to the source electrode of the first MOS tube; one end of the inductor is connected to the source electrode of the first MOS tube, and the other end of the inductor is connected to the output voltage end; one end of the second capacitor is connected to the other end of the inductor, and the other end of the second capacitor is connected to the source electrode of the second MOS transistor; the first resistor is connected in parallel to the second capacitor.
As a further improvement, the input end of the logic controller is connected with the CT signal end.
As a further improvement, the second shunt circuit includes: one end of the first switch is connected to the cathode of the first diode, and the control end of the first switch is connected to the CT signal end; a cathode of the second diode is connected to the other end of the first switch, and an anode of the second diode is connected to the other end of the inductor; and the grid electrode of the third MOS tube is connected to the cathode of the second diode, the source electrode of the third MOS tube is connected to the anode of the second diode, and the drain electrode of the third MOS tube is connected to the input voltage end.
As a further improvement, the second shunt circuit further includes: the input end of the inverter is connected to the CT signal end; one end of the second switch is connected to the cathode of the second diode, the other end of the second switch is connected to the anode of the second diode, and the control end of the second switch is connected to the output end of the phase inverter; a third capacitor connected in parallel to the second diode; and the anode of the third diode is connected to the cathode of the first diode, and the cathode of the third diode is connected to one end of the first switch.
As a further improvement, the second shunt circuit further includes: the input end of the inverter is connected to the CT signal end; one end of the second switch is connected to the cathode of the second diode, the other end of the second switch is connected to the anode of the second diode, and the control end of the second switch is connected to the output end of the phase inverter; the anode of the third diode is connected to the cathode of the first diode, and the cathode of the third diode is connected to one end of the first switch; and one end of the third capacitor is connected to the cathode of the third diode, and the other end of the third capacitor is grounded.
As a further improvement, the second shunt circuit further includes: the input end of the inverter is connected to the CT signal end; one end of the second switch is connected to the cathode of the second diode, the other end of the second switch is connected to the anode of the second diode, and the control end of the second switch is connected to the output end of the phase inverter; the anode of the third diode is connected to the other end of the first switch, and the cathode of the third diode is connected to one end of the second switch; a third capacitor connected in parallel to the second diode.
As a further improvement, the second shunt circuit further includes: the input end of the inverter is connected to the CT signal end; one end of the second switch is connected to the cathode of the second diode, the other end of the second switch is connected to the anode of the second diode, and the control end of the second switch is connected to the output end of the phase inverter; the anode of the third diode is connected to the other end of the first switch, and the cathode of the third diode is connected to one end of the second switch; and one end of the third capacitor is connected to the cathode of the third diode, and the other end of the third capacitor is grounded.
As a further improvement, the second shunt circuit further includes: a third capacitor connected in parallel to the second diode; the second resistor is connected in parallel with the third capacitor; and the anode of the third diode is connected to the cathode of the first diode, and the cathode of the third diode is connected to one end of the first switch.
The utility model has the beneficial effects that:
according to the NMOS through circuit and the structure applied to the BUCK converter, the BST voltage of the BUCK is used as the starting voltage required by the charge pump to maintain the NMOS through tube, the NMOS through power tube can be driven, the common PMOS through power tube is replaced, and the production cost of the through circuit is reduced.
Drawings
Fig. 1 is a circuit diagram provided in the background of the utility model.
Fig. 2 is a schematic diagram of a through circuit applied to a buck converter according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a node waveform when CT _ ON is turned ON according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a through circuit applied to a buck converter according to a second embodiment of the present invention.
Fig. 5 is a schematic diagram of a through circuit applied to a buck converter according to a third embodiment of the present invention.
Fig. 6 is a schematic diagram of a through circuit applied to a buck converter according to a fourth embodiment of the present invention.
Fig. 7 is a schematic diagram of a through circuit applied to a buck converter according to a fifth embodiment of the present invention.
In the figure:
1. first subcircuit 11, logic controller 12, first buffer
13. Second buffer QTN: first MOS pipe QBN: second MOS transistor
D1: first diode Cbst: first capacitance Cout: second capacitor
L: inductance Rload: first resistor 2. second shunt circuit
21: inverter S1: first switch S2: the second switch
QN: a third MOS tube DZ: second diode D2: third diode
CH: third capacitance RG: second resistance
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings of the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the utility model, as claimed, but is merely representative of selected embodiments of the utility model. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
Example one
Referring to fig. 2, a through circuit applied to a buck converter includes: a first subcircuit 1; and a second sub circuit 2, wherein the second sub circuit 2 is connected to the first sub circuit 1. The first sub-circuit 1 includes: a logic controller 11; a first buffer 12, an input terminal of the first buffer 12 is connected to a first output terminal of the logic controller 11; a second buffer 13, wherein an input terminal of the second buffer 13 is connected to a second output terminal of the logic controller 11. According to the NMOS through circuit and the structure applied to the BUCK converter, the BST voltage of the BUCK is used as the starting voltage required by the charge pump to maintain the NMOS through tube, the NMOS through power tube can be driven, the common PMOS through power tube is replaced, and the production cost of the through circuit is reduced.
The first sub-circuit 1 further comprises: a first diode D1, the anode of the first diode D1 is connected to the working voltage end, and the cathode of the first diode D1 is connected to the first end of the first buffer 12; a first MOS transistor QTN, wherein a drain of the first MOS transistor QTN is connected to an input voltage terminal, a gate of the first MOS transistor QTN is connected to an output terminal of the first buffer 12, and a source of the first MOS transistor QTN is connected to a second terminal of the first buffer 12; a second MOS transistor QBN, a drain of the second MOS transistor QBN being connected to the source of the first MOS transistor QTN, a gate of the second MOS transistor QBN being connected to the output of the second buffer 13, a source of the second MOS transistor QBN being connected to the second end of the second buffer 13, and a first end of the second buffer 13 being connected to the working voltage end.
The first sub-circuit 1 further includes: one end of the first capacitor Cbst is connected to the cathode of the first diode D1, and the other end of the first capacitor Cbst is connected to the source of the first MOS transistor QTN; one end of the inductor L is connected to the source of the first MOS transistor QTN, and the other end of the inductor L is connected to the output voltage end; one end of the second capacitor Cout is connected to the other end of the inductor L, and the other end of the second capacitor Cout is connected to the source electrode of the second MOS transistor QBN; the first resistor Rload is connected in parallel to the second capacitor Cout.
The input end of the logic controller 11 is connected to the CT signal end.
The second shunt circuit 2 includes: a first switch S1, wherein one end of the first switch S1 is connected to the negative electrode of the first diode D1, and the control end of the first switch S1 is connected to the CT signal end; a second diode DZ, a cathode of the second diode DZ is connected to the other end of the first switch S1, and an anode of the second diode DZ is connected to the other end of the inductor L; and a gate of the third MOS transistor QN is connected to the cathode of the second diode DZ, a source of the third MOS transistor QN is connected to the anode of the second diode DZ, and a drain of the third MOS transistor QN is connected to the input voltage terminal.
The second shunt circuit 2 further comprises: the input end of the inverter 21 is connected to the CT signal end; a second switch S2, one end of the second switch S2 is connected to the cathode of the second diode DZ, the other end of the second switch S2 is connected to the anode of the second diode DZ, and the control end of the second switch S2 is connected to the output end of the inverter 21; a third capacitor CH connected in parallel to the second diode DZ; a third diode D2, wherein an anode of the third diode D2 is connected to a cathode of the first diode D1, and a cathode of the third diode D2 is connected to one end of the first switch S1.
The principle of the through circuit applied to the buck converter provided by the utility model is as follows:
when the BUCK increases the duty ratio until the maximum duty ratio can not meet the VOUT/VIN ratio, the CT _ ON controls the through NMOS tube to be opened, and meanwhile, the BUCK is controlled to keep a certain duty ratio and a certain frequency to work, because the voltage when the BST is opened at QTN is approximately equal to the voltage of VIN + VDD-VD1, energy can be supplied to CH through D2, and VG can always maintain a normal opening voltage, namely VIN + VDD-VD1-VD 2;
the whole system utilizes the BST voltage of the BUCK as a charge pump to provide starting voltage for the NMOS direct power tube, the whole circuit is simple in structure, and meanwhile, the cost is low;
in the stage of controlling the turn-ON of the QN POWER NMOS by CT _ ON, the BUCK can reduce the frequency and operate at the maximum duty ratio so as to reduce the switching loss of the BUCK operation and improve the overall system efficiency;
referring to fig. 3, when CT _ ON is enabled, BST is lowered in frequency to operate at the maximum duty cycle, and meanwhile VG is gradually raised, the NMOS transistor is gradually turned ON, and VOUT is raised to VIN voltage.
Example two
Referring to fig. 4, the present embodiment is different from the above embodiments in that the third capacitor DH is at a different position; the second shunt circuit 2 further comprises: the input end of the inverter 21 is connected to the CT signal end; a second switch S2, one end of the second switch S2 is connected to the cathode of the second diode DZ, the other end of the second switch S2 is connected to the anode of the second diode DZ, and the control end of the second switch S2 is connected to the output end of the inverter 21; a third diode D2, an anode of the third diode D2 being connected to a cathode of the first diode D1, a cathode of the third diode D2 being connected to one end of the first switch S1; and one end of the third capacitor CH is connected to the cathode of the third diode D2, and the other end of the third capacitor CH is grounded.
EXAMPLE III
Referring to fig. 5, the present embodiment is different from the above-described embodiments in that the first switch S1 is in a different position; the second shunt circuit 2 further comprises: the input end of the inverter 21 is connected to the CT signal end; a second switch S2, one end of the second switch S2 is connected to the cathode of the second diode DZ, the other end of the second switch S2 is connected to the anode of the second diode DZ, and the control end of the second switch S2 is connected to the output end of the inverter 21; a third diode D2, wherein an anode of the third diode D2 is connected to the other end of the first switch S1, and a cathode of the third diode D2 is connected to one end of the second switch S2; and a third capacitor CH connected in parallel to the second diode DZ.
Example four
Referring to fig. 6, the present embodiment is different from the above embodiments in that the first switch S1 and the third capacitor CH are at different positions; the second shunt circuit 2 further comprises: the input end of the inverter 21 is connected to the CT signal end; a second switch S2, one end of the second switch S2 is connected to the cathode of the second diode DZ, the other end of the second switch S2 is connected to the anode of the second diode DZ, and the control end of the second switch S2 is connected to the output end of the inverter 21; a third diode D2, wherein an anode of the third diode D2 is connected to the other end of the first switch S1, and a cathode of the third diode D2 is connected to one end of the second switch S2; and one end of the third capacitor CH is connected to the cathode of the third diode D2, and the other end of the third capacitor CH is grounded.
EXAMPLE five
Referring to fig. 7, the present embodiment is different from the above-described embodiments in that the second switch S2 is replaced with a second resistor RG; the second shunt circuit 2 further comprises: a third capacitor CH connected in parallel to the second diode DZ; a second resistor RG connected in parallel to the third capacitor CH; a third diode D2, wherein an anode of the third diode D2 is connected to a cathode of the first diode D1, and a cathode of the third diode D2 is connected to one end of the first switch S1.
The working principle, working process and the like of the present embodiment can refer to the corresponding contents of the foregoing embodiments.
The above examples are only for illustrating the technical solutions of the present invention and not for limiting the same. It will be understood by those skilled in the art that any modifications and equivalents may be made thereto without departing from the spirit and scope of the present invention as set forth in the appended claims.
Claims (10)
1. A pass-through circuit for use in a buck converter, comprising:
a first subcircuit, the first subcircuit comprising:
a logic controller;
the input end of the first buffer is connected to the first output end of the logic controller;
the input end of the second buffer is connected to the second output end of the logic controller;
a second subcircuit connected to the first subcircuit.
2. The pass-through circuit for a buck converter according to claim 1, wherein the first subcircuit further comprises:
the anode of the first diode is connected to the working voltage end, and the cathode of the first diode is connected to the first end of the first buffer;
the drain electrode of the first MOS tube is connected to an input voltage end, the grid electrode of the first MOS tube is connected to the output end of the first buffer, and the source electrode of the first MOS tube is connected to the second end of the first buffer;
the drain electrode of the second MOS tube is connected to the source electrode of the first MOS tube, the grid electrode of the second MOS tube is connected to the output end of the second buffer, the source electrode of the second MOS tube is connected to the second end of the second buffer, and the first end of the second buffer is connected to the working voltage end.
3. The pass-through circuit for a buck converter according to claim 2, wherein the first subcircuit further comprises:
one end of the first capacitor is connected to the cathode of the first diode, and the other end of the first capacitor is connected to the source electrode of the first MOS tube;
one end of the inductor is connected to the source electrode of the first MOS tube, and the other end of the inductor is connected to an output voltage end;
one end of the second capacitor is connected to the other end of the inductor, and the other end of the second capacitor is connected to the source electrode of the second MOS transistor;
the first resistor is connected in parallel to the second capacitor.
4. The pass-through circuit for a buck converter according to claim 1, wherein the input of the logic controller is connected to the CT signal terminal.
5. The pass-through circuit for a buck converter according to claim 3, wherein the second subcircuit comprises:
one end of the first switch is connected to the cathode of the first diode, and the control end of the first switch is connected to the CT signal end;
a cathode of the second diode is connected to the other end of the first switch, and an anode of the second diode is connected to the other end of the inductor;
and the grid electrode of the third MOS tube is connected to the cathode of the second diode, the source electrode of the third MOS tube is connected to the anode of the second diode, and the drain electrode of the third MOS tube is connected to the input voltage end.
6. The pass-through circuit for a buck converter according to claim 5, wherein the second subcircuit further comprises:
the input end of the inverter is connected to the CT signal end;
one end of the second switch is connected to the cathode of the second diode, the other end of the second switch is connected to the anode of the second diode, and the control end of the second switch is connected to the output end of the phase inverter;
a third capacitor connected in parallel to the second diode;
and the anode of the third diode is connected to the cathode of the first diode, and the cathode of the third diode is connected to one end of the first switch.
7. The pass-through circuit for a buck converter according to claim 5, wherein the second sub-circuit further includes:
the input end of the inverter is connected to the CT signal end;
one end of the second switch is connected to the cathode of the second diode, the other end of the second switch is connected to the anode of the second diode, and the control end of the second switch is connected to the output end of the phase inverter;
the anode of the third diode is connected to the cathode of the first diode, and the cathode of the third diode is connected to one end of the first switch;
and one end of the third capacitor is connected to the cathode of the third diode, and the other end of the third capacitor is grounded.
8. The pass-through circuit for a buck converter according to claim 5, wherein the second subcircuit further comprises:
the input end of the inverter is connected with the CT signal end;
one end of the second switch is connected to the cathode of the second diode, the other end of the second switch is connected to the anode of the second diode, and the control end of the second switch is connected to the output end of the phase inverter;
the anode of the third diode is connected to the other end of the first switch, and the cathode of the third diode is connected to one end of the second switch;
a third capacitor connected in parallel to the second diode.
9. The pass-through circuit for a buck converter according to claim 5, wherein the second subcircuit further comprises:
the input end of the inverter is connected to the CT signal end;
one end of the second switch is connected to the cathode of the second diode, the other end of the second switch is connected to the anode of the second diode, and the control end of the second switch is connected to the output end of the phase inverter;
the anode of the third diode is connected to the other end of the first switch, and the cathode of the third diode is connected to one end of the second switch;
and one end of the third capacitor is connected to the cathode of the third diode, and the other end of the third capacitor is grounded.
10. The pass-through circuit for a buck converter according to claim 5, wherein the second subcircuit further comprises:
a third capacitor connected in parallel to the second diode;
the second resistor is connected in parallel with the third capacitor;
and the anode of the third diode is connected to the cathode of the first diode, and the cathode of the third diode is connected to one end of the first switch.
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| CN202121237146.XU CN216751537U (en) | 2021-06-03 | 2021-06-03 | Direct circuit applied to buck converter |
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| CN202121237146.XU CN216751537U (en) | 2021-06-03 | 2021-06-03 | Direct circuit applied to buck converter |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113394978A (en) * | 2021-06-03 | 2021-09-14 | 英麦科（厦门）微电子科技有限公司 | Direct circuit applied to buck converter |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113394978A (en) * | 2021-06-03 | 2021-09-14 | 英麦科（厦门）微电子科技有限公司 | Direct circuit applied to buck converter |
| CN113394978B (en) * | 2021-06-03 | 2024-05-03 | 拓尔微电子股份有限公司 | Through circuit applied to buck converter |
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