JPS6325438B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor circuit, and in particular to a decoder circuit for an electrically writable read-only semiconductor memory device (hereinafter referred to as "EPROM"). be.

[Technical background of the invention]

There are two types of EPROMs: one in which information is written into a predetermined memory cell by applying a high voltage from the outside, and the other in which information is written by generating a high voltage internally. Here, the high voltage for writing information is
The voltage is applied to the gate or drain of the memory cell, but a decoder circuit that applies the voltage only to a specific memory cell is used in dynamic RAM, static RAM, etc.
Unlike RAM, etc., it is necessary to operate in both the voltage ranges of the read system (Vcc system) and the write system (Vpp system), so special measures are required.

A conventional device will be described with reference to FIG. 1 of the accompanying drawings. In addition, in the following description of the drawings, the same elements are indicated by the same reference numerals. FIG. 1 is a circuit diagram of one configuration example. P-channel enhancement MOS transistors (hereinafter referred to as pMOS transistors) 1 whose gate terminals are grounded and which are always in a conductive state input decode input signals RD ₁ to RDn to their respective gate terminals.
n-channel enhancement MOS transistors (hereinafter referred to as "nMOS transistors") 2
₁ to 2n are connected in series to constitute a NAND circuit 10 which is operated by voltage supply power Vcc. The output signal of this NAND circuit 10 is applied to a CMOS inverter 20 consisting of a pMOS transistor 4 and an nMOS transistor 5 via an nMOS transistor 3 serving as a transfer gate. The decoded output signal WL output from this CMOS inverter is applied to the gate terminal of the feedback pMOS transistor 6. Note that the CMOS inverter 20 consisting of the feedback pMOS transistor 6, pMOS transistor 4, and nMOS transistor 5 is supplied with a switching power supply Vpp ^* , which is set to Vcc during reading and Vpp (Vpp>Vcc) during writing. Ru. Further, the Vcc power supply is input to the gate of the nMOS transistor 3, and it is always in a conductive state and plays the role of connecting the Vcc system circuit and the Vpp system circuit.

Next, the reading and writing operations of the configuration example shown in FIG. 1 will be explained.

At the time of reading, the potential of the switching power supply Vpp ^* is set equal to the voltage supply power supply potential Vcc (for example, 5.0V) (Vpp ^* =Vcc). When decode signals RD ₁ to RDn are all high level (hereinafter referred to as "H"),
The output of the NAND circuit 10 is low level (hereinafter referred to as “L”)
) and transfer gate (nMOS).
operated via transistor 3)
The decode output signal WL of the CMOS inverter 20 becomes "H". At this time, decode output signal WL
Since the signal is "H", the feedback pMOS transistor 6 is turned off.

When at least one of the decode signals RD ₁ to RDn is “L”, the output of the NAND circuit 10 is “H”, and this is given to the CMOS inverter 20 via the transfer gate.
The decode output signal WL generated from this becomes "L". Therefore, for feedback
The pMOS transistor 6 is turned on, and the potential at the input point of the CMOS inverter 20 is set to Vcc (for example, 5.0V) by the switching power supply Vpp ^* set to the Vcc potential. The reason why the feedback pMOS transistor 6 is provided in this way is as follows. Now, consider a transient phenomenon when the output of the NAND circuit 10 changes from "L" to "H". The drain of the transistor 3 (the terminal on the left side of the figure) becomes "H" (that is, the potential of V _CC , for example, 5V), and this potential is transmitted to the source of the transistor 3 (the terminal on the right side of the figure). However, in order for this transistor 3 to turn on, it is necessary to satisfy V _G −V _S >V _TH (where V _TH is a threshold voltage), where V _S is the source potential and V _G is the gate voltage. Therefore, even if the drain is 5V, the source is 5V.
It only rises to −V _TH (for example, 3V). When the input voltage of the inverter 20 becomes an intermediate voltage such as 3V, both transistors 4 and 5 are turned on, and the output WL becomes unstable. Also, through these transistors V _PP
^* DC current flows from the ground level to the ground level, which is undesirable from the viewpoint of reducing power consumption.

Therefore, transistor 6 is provided. That is, in the above example, when the input voltage of the inverter 20 rises to an intermediate potential such as 3V, the output
WL decreases from 5V to 0V. This turns on transistor 6 and inverter 2
The 0 input terminal is connected to V _PP ^* and fixed at 5V. Transistor 4 is in the off state, and the output WL
stabilizes at 0V.

During writing, the potential of the switched power supply Vpp ^* is set to the write power supply potential Vpp, which is higher than Vcc (for example, 12.5V). Decode signals RD ₁ to RDn are all “H”
At this time, the decode output signal WL generated from the CMOS inverter 20 becomes "H" (=Vpp). When at least one of the decode signals RD ₁ to RDn is “L”, the CMOS inverter 20
The decode output signal WL emitted from is “L”
(=OV). Decode output signal WL is “L”
When , the pMOS transistor 6 for feedback is turned on, and the input point of the CMOS inverter 20 is set to the Vpp potential by the Vpp ^* power supply.
Although it is made to have Vpp potential, nMOS transistor 3
Since the gate potential of is Vcc, NAND circuit 1
The potential at the 0 output point is never raised to the Vpp potential. In the nMOS transistor 3 forming the transfer gate in this way, when a high potential Vpp is applied to the output point of the NAND circuit 10, current flows from the drain of the pMOS transistor 1 to the substrate.
This prevents malfunctions from occurring.

[Problems with background technology]

However, the conventional device as described above has a problem in that it cannot operate at high speed. That is, as mentioned above, the output WL is not output until transistor 6 is turned on.
is stable, so it takes time to obtain a stable output after the input changes.

Further, in the conventional device as described above, the transistor 6
There is also the problem that unnecessary current flows transiently through the circuit. For example, when all ^of the decode signals RD ₁ to _{RD o} become “H”, transistor 6, transistor 3, and transistor 2 ₁ to 2 _{o are}
Unnecessary transient current will flow through this path. Such a transient current becomes a big problem from the viewpoint of low power consumption.

[Purpose of the invention]

The present invention has been made to overcome the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide a semiconductor circuit that is suitable for high-speed operation and has low transient current consumption.

[Summary of the invention]

In order to achieve the above object, the present invention connects a MOS inverter to the output side of a NAND circuit consisting of a pMOS transistor that inputs a write signal to the gate and an nMOS transistor connected in series to this and inputs a decode signal to the gate, These NAND
The circuit and the MOS inverter are supplied with a switching power supply Vpp ^* , which is the voltage supply potential Vcc during reading and becomes the higher write power supply potential Vpp during writing.
The present invention provides a semiconductor circuit that extracts a decoded output signal from a MOS inverter. Furthermore, the present invention inserts an intrinsic MOS transistor with a small substrate bias effect between the NAND circuit and the MOS inverter, and inputs a switching power supply Vpp ^* to the gate of this transistor to extract a decoded output signal from the MOS inverter. It provides semiconductor circuits.

[Embodiments of the invention]

Hereinafter, some embodiments of the present invention will be described with reference to FIGS. 2 and 3 of the accompanying drawings. FIG. 2 is a circuit diagram of one embodiment. An inverter 8 is connected to the gate of the pMOS transistor 1 so that a write control signal can be applied thereto. The signal has a high potential (Vcc) when reading and a low potential (ground potential) when writing, and when writing (Vpp ^* → Vpp
) suppresses the mutual conductance gm of pMOS transistor 1 (when reading, Vgs = 5V,
Vgs = 7.5V when writing). The output point of the NAND circuit 10 is
It is directly connected to the input point of the CMOS inverter 20, and the NAND circuit 10 and the CMOS inverter 20 are supplied with a switching power supply Vpp ^* .

Next, the operation of the embodiment shown in FIG. 2 will be explained.

When reading, the switching power supply Vpp ^* is set to Vcc. When the decode signals RD ₁ to RDn are all "H", the output of the NAND circuit 10 is "L", so the output of the CMOS inverter 20 is "H".
When at least one of the decode signals RD ₁ to RDn is "L", the output of the NAND circuit 10 is "H", so the output of the CMOS inverter 20 is "L". At this time, in the circuit shown in Figure 2,
Since no transfer gate is inserted between the NAND circuit 10 and the CMOS inverter 20, there is no need to consider the substrate bias effect (the potential at the input point of the CMOS inverter 20 swings from the ground potential to Vcc). There is no need to provide a pMOS transistor for feedback as shown in FIG.

During writing, the switching power supply Vpp ^* is at Vpp potential (e.g.
12.5V). Decode signal RD ₁ ~
When all RDn are "H", the output of the NAND circuit 10 becomes "L", and when any one is "L", the output becomes "H". At this time, NAND circuit 1
Since no transfer gate is inserted between CMOS inverter 20 and CMOS inverter 20, the potential at the input point of CMOS inverter 20 is Vpp from ground potential.
It can swing up to a potential (for example, 12.5V). Therefore,
No direct current flows to the CMOS inverter 20, and no current flows from the drain of the pMOS transistor 1 to the substrate. Also,
During writing, the signal is "L" (ground potential) and the output of the inverter 8 is "H" (=Vcc), so the mutual conductance gm of the pMOS transistor 1 only increases slightly compared to when reading.
The "L" potential of the output of the NAND circuit 10 is almost unchanged from the time of reading.

FIG. 3 is a circuit diagram of another embodiment of the present invention.
An intrinsic nMOS transistor 9 is inserted between the NAND circuit 10 and the CMOS inverter 20, and a pMOS transistor 6 is provided for feeding back the output 20 of the CMOS inverter 20 to the input side.
A switched power supply Vpp ^* is supplied to the pMOS transistor 6, and a switched power supply Vpp ^* is inputted to the gate of the intrinsic type nMOS transistor 9.

Next, the operation of the embodiment shown in FIG. 3 will be explained.

At the time of reading, it operates in the same way as the embodiment shown in FIG.
The potential at the input point of the CMOS inverter 20 swings from the ground potential to the Vcc potential.

At the time of writing, the gate of the pMOS transistor 1 is brought to the Vcc potential by the PGM signal, and the mutual conductance gm increases only slightly compared to the time of reading, so that the potential of "L" becomes approximately the same value at the time of reading. In addition, since the NAND circuit 10 and the CMOS inverter 20 are separated by the transfer gate consisting of the intrinsic nMOS transistor 9, the direct current during writing is
It does not flow to the inverter 20 or the NAND circuit 10.

In the embodiment shown in FIG.
Since the NAND circuit system and the inverter system, through which current does not flow, are separated by a transfer gate, the Vpp of the NAND circuit system ^* between the power supply and the inverter system
By providing a separate Vpp ^* power supply, it is possible to reduce the voltage drop due to the current of the Vpp ^* power supply in the inverter system and obtain a decoded output of the desired voltage.

Note that if the substrate bias effect of the intrinsic nMOS transistor 9 is negligible, then
The pMOS transistor 6 for feedback can be omitted.

〔Effect of the invention〕

As described above, according to the present invention, the output signal of the NAND circuit that inputs the decode signal can be input to the drive inverter without reducing the signal level (eliminating the potential drop due to the substrate bias effect of the transfer gate). Therefore, a semiconductor circuit can be obtained which can increase the switching speed as a decoder circuit and can reduce transient current consumption through the feedback loop. Furthermore, since the transfer gate and feedback MOS transistors can be omitted, the number of elements per circuit can be reduced and the degree of integration can be increased.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one configuration example of a conventional device, FIG. 2 is a circuit diagram of one embodiment of the present invention, and FIG. 3 is a circuit diagram of another embodiment of the present invention. 10...NAND circuit, 20...CMOS inverter,
RD ₁ to RDn...Decode signal, WL...Decode output signal, PGM...Write control signal.

Claims (1)

[Scope of Claims] 1. A p-channel MOS transistor which is always on and which inputs a predetermined write control signal to its gate, and a plurality of p-channel MOS transistors connected in series to the p-channel MOS transistor and which inputs a predetermined decode signal to each gate. A NAND circuit having an n-channel MOS transistor, a MOS inverter that generates a decoded output signal based on the output of the NAND circuit, and a voltage supply potential Vcc set at the time of reading.
A semiconductor circuit comprising a switching power supply Vpp ^* that is set to a higher write power supply potential Vpp during writing, and the switching power supply Vpp ^* is supplied to the p-channel MOS transistor and the MOS inverter. 2. The semiconductor circuit according to claim 1, wherein the predetermined write control signal becomes a voltage supply potential Vcc during writing and becomes a ground potential during reading. 3. It has a p-channel MOS transistor that is always conductive and inputs a predetermined write control signal to its gate, and a plurality of n-channel MOS transistors connected in series to the p-channel MOS transistor and inputs a predetermined decode signal to each gate. A NAND circuit, a MOS inverter that generates a decoded output signal based on the output of the NAND circuit, an intrinsic MOS transistor inserted between the NAND circuit and the MOS inverter, and a voltage supply potential set to Vcc during reading. is,
The p-channel MOS transistor and the MOS inverter are supplied with the switching power supply Vpp ^* , which is set to a higher write power supply potential ^Vpp during writing, and the intrinsic type MOS transistor A semiconductor circuit in which the switching power supply Vpp ^* is inputted to the gate of the semiconductor circuit. 4. The semiconductor circuit according to claim 3, wherein the predetermined write control signal becomes a voltage supply potential Vcc during writing and becomes a ground potential during reading.