JPS6145496A - Decoder circuit - Google Patents

Abstract

PURPOSE:To reduce the number of elements and to attain high integration by using the load of a NAND gate as a constant current source based upon a depression type FET and driving an inverter directly by the output of the NAND gate. CONSTITUTION:The load of the NAND gate using Qn1-Qn3 as a driving FET is used as the depression type n-channel MISFET-Qnd and Vppi is used as a power supply for the NAND gate to drive CMOS inverters (Qp3, Qn5) directly by the output X of the NAND gate. Therefore, Qnd is used as a constant current load and VSS can be precisely obtained by the Qn1-Qn3 having proper size at a selection time. Consequently, layout with narrow pitches can be attained and high integration can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a decoder circuit for a memory that requires high voltage during writing.

[Conventional technology]

In a CMOS (complementary MO3) EFROM (electrically programmable ROM), when writing, it is necessary to set the word line and bit line to a higher voltage than when reading. For this reason, the decoder circuit must also be able to output different selection levels during reading and writing, but must be O. Figure 2 shows a conventional example of this type of word line decoder, in which 6.3-bit addresses 307 bits τ to a2/ax are decoded and one of eight word lines (WL) is selected. There is (a
t/at means ai or ai). All MOS transistors used are enhancement type, and Q
nl ~ Qn5 are n channels, Qpl "'Qp3 is p
Channel. There are two types of power supplies: Vcc is a fixed power supply with a low voltage (for example, 5V), Vppi is a high voltage Vpp (for example, 21■) during writing, and Vcc is a fixed power supply when reading.
This is the power source that switches to c. Vss is ground.

Transistors Qn1 to Qn3 and Qpl constitute a three-power NAND gate, and output X is set to L (low) level only when all three transistors are at H (high) level. The output X of the NAND gate is passed through the transfer gate Qn4 to the transistors Qn5 and Qp that constitute the CMOS inverter.
3, and when X=L, the transistor Q
Turn off n5 and turn on Qp3. Therefore, word line W
The level of L becomes H (selection). Conversely, when X=H, the transistor Qn5 is on and Qp3 is off, so the word line WL becomes L (non-selected).

Ql)2 is a latch pull-up transistor required to stably hold the word line level. In other words,
At the time of writing, Vpp1=Vpp, and the power supply of the NAND gate that supplies the human power X is still Vcc, so for now,
In this case, the operation of the inverter becomes unstable. That is, even if X=H, the voltage applied to the gate of the inverter is only Vac, and this is because the output of the inverter operating at Vpp will not become completely L. So this WL=
By feeding back L to transistor Qp2 and turning it on, high voltage Vpp is applied to the gates of transistor Q n 5 and transistor Glp3, and word line WL is completely turned to L.
(deselected). At this time, it is necessary to prevent the vpp system and the Vce system from shorting, and this is ensured by providing the transistor Q n 4. That is, the gate voltage of the impark of the transistor Qp2 is Vl)I
), transistor Qn4 is cut off. When X=L (selected), WL=H, transistor Qp2 is turned off, and transistor Qp3
is completely turned on and the word line WL becomes vpp. At the time of reading, the basic operation remains unchanged except that Vpp1 becomes VCC.

[Problem that the invention seeks to solve]

The decoder with the circuit configuration described above has a large number of elements and a large number of wiring lines, which hinders high integration.

In other words, a word decoder is provided on each word line, and if this cannot be laid out with a narrow pitch, the pitch of each word line must be widened, and the overall area occupied becomes large, making it impossible to achieve high integration.

Therefore, the present invention aims to improve the configuration of the decoder circuit, reduce the number of elements, and reduce the number of wires, thereby enabling layout in a narrow pinch and meeting the demand for higher integration.

[Selling means to solve problems]

The present invention provides a decoder in which an output CMOS inverter is operated with a power supply that switches to a high voltage during writing and a low voltage during reading, and the inverter is driven by the output of a NAND gate that decodes address input. In the circuit, the power source of the NAND gate is the same as that of the inverter, the load of the NAND gate is a constant current source using a desorption type transistor, and the inverter is directly driven by the output of the NAND gate. .

[Effect]

If the load of the NAND gate is a constant current source using a depletion type transistor, the power source of the NAND gate can be the same as the power source of the impark.

Therefore, the non-selected output of the NAND gate is when writing.

Since the voltage will be high, pull-up transistor Qp2
The wiring L+ thereof can be omitted, and the transistor Q n 4 for preventing short circuits in the power supply is also obviated.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows one embodiment of the present invention, and the same parts as in FIG. 2 are given the same reference numerals. The difference between this example and Fig. 2 is that
First, the load of the NAND gate using Qn+ to Qn3 as driving transistors is replaced with a depletion type n-channel MIS transistor Qnd, secondly, the power supply of the NAND gate is set to Vpp1, and thirdly, the output X of the NAND gate is directly connected to the CMOS transistor. The reason is that the impark is driven.

Therefore, transistor Qp2 . Qn4 is omitted, and feedback wiring 1 is also omitted. Furthermore, p
Only one n-well is required to form the channel transistor (two n-wells are required in FIG. 2).

Instead, one extra ion implantation step is required to form the channel of the depletion type transistor Qnd, but this does not impede the increase in the degree of integration. With this circuit configuration, the pinch (pinch for arranging the decoder circuits), which was 48 μm in the case of FIG. 2, was halved to 24 μm. In addition, the power supply can be made using only the V ppi system.The operation will be explained below. The output X of the NAND gate becomes L when all address inputs are H. This L level is the second
As in the figure, the voltage is VSS during both reading and writing. However, the H level is V CC% when reading and VI) I when writing.
). This is also the power supply of NAND gate V ppi
This is because the load transistor is a depletion type. Therefore, no problem occurs even if a CMOS inverter that operates at the same <Vpp1 is directly driven. In other words, the second
Transistor Qn4 in the figure. Qp2 becomes unnecessary. However, for this purpose, the load of the NOR gate must be a constant current source. This is because if the transistor Qp1 is left as it is as shown in FIG. 2, the current flowing through the transistor becomes too large when Vpp1=Vpp, and even if the current is drawn by the transistors Qn1 to Qn3, the transistor If the size is not too large, change the output
This is because it cannot be lowered to = Vss.

Therefore, in this example, we use an n-channel debris MIS.
A constant current load is configured using the l-transistor Qnd.

In this way, since the current flowing is almost constant whether Vppi is Vl)P or Vcc, it is possible to ensure that X=L is set to Vs with transistors Qnl to Qn3 of a certain size.
can be reduced to s. Of course, the transistors Q n 1 to Q
If even one of n3 turns off, the output X becomes Vpp (during writing) or Vcc (during reading) since the transistor Qnd is a depletion type.

〔Effect of the invention〕

As described above, according to the present invention, a 0MO3 type decoder circuit can be configured with a small number of elements and wires.
This has the advantage of enabling narrow pitch layout and improving the degree of integration.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional decoder circuit. In the figure, Qnl to Qn3, Qnd are transistors forming the Noah gate, Qnl to Qn3, and Q10. Qp3 is a transistor forming a CMOS inverter.

Claims (1)

[Claims] The output CMOS inverter is operated with a power supply that switches to high voltage during writing and low voltage during reading.
Further, in a decoder circuit in which the inverter is driven by the output of a NAND gate that decodes an address input, the power source of the NAND gate is the same as that of the inverter, and the load of the NAND gate is a constant current source using a depletion type transistor. , further comprising a configuration in which the output of the NAND gate directly drives the inverter.