JP2504410B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention is intended to form a plurality of enhancement type transistors connected in series in advance, and to add impurities to a channel region of any one of them according to stored data. Related to a so-called ion implantation mask type NAND-ROM type semiconductor memory device in which ions are implanted into a depletion type one (prior art).
It is configured as shown in the circuit diagram. This ROM is basically composed of m series circuits 50 in which (n + 1) N-channel MOS transistors are connected in series.
Each of these series circuits 50 is provided on the side close to the output node (bit line) 51 and has a decoder circuit (not shown).
Select signal B1 output from to select each series circuit 50
To Bm are supplied, and n word line signals (row address signals) R1 to Rn are supplied to the gates of n memory cell transistors 53. In the manufacturing process, each of the memory cell transistors 53 is initially formed as an enhancement type transistor.After that, impurities are ion-implanted into an arbitrary channel region by ion implantation with an ion implantation mask designed according to stored data. It has been changed to a depletion type.

Further, between the high potential power supply V _DD and the output node 51,
Based on the precharge control signal φP, this output node 51
A load circuit 54 for precharging is inserted. The load circuit 54 is composed of, for example, a P-channel MOS transistor whose gate is supplied with an inverted signal of the precharge control signal φP, or a depletion type MOS transistor.

When data is read from the ROM having such a structure, the output node 51 is precharged to the "1" level by the load circuit 54 during the precharge period. During this precharge period, an arbitrary selection signal Bi (i = 1 to m) is set to "1" level, the selection transistor 52 becomes conductive, and one series circuit 50 is selected. This selected series circuit
At 50, the level of the output data out is determined according to the type of the memory cell transistor 53 to which the activated (“0” level) signal of the n word line signals R1 to Rn is supplied. That is, in the case where the memory cell transistor to which the activated word line signal is supplied is a depletion type, the transistor is rendered conductive and the output node 51 is connected through the n MOS transistors connected in series.
Is discharged to the ground potential V _SS . As a result, the output data out becomes "0" level. On the other hand, when the memory cell transistor to which the activated word line signal is supplied is the enhancement type, this transistor becomes non-conductive and the potential of the output node 51 does not change. In this case, the output data out becomes "1" level.

By the way, power consumption is a problem in the conventional storage device. That is, it does not occur during the read operation of the "1" level data, but a through current flows between V _DD and V _SS during the read operation of the "0" level data. The power consumption due to this through current becomes a value that cannot be ignored as the capacity increases. Further, when the number of memory cell MOS transistors 53 of one series circuit 50 is reduced for the purpose of high-speed operation, the increase in power consumption due to the through current becomes significant, which is a major obstacle to high-speed operation. .

FIG. 6 is a circuit diagram showing another example of the conventional ion implantation mask type NAND-ROM. In the case of this ROM, instead of providing the selection transistor 52, the address signals D1 to D2m before forming the selection signals B1 to Bm are supplied to the gate on the side close to the output node 51 of each series circuit 50. 2m MOS transistors 55 for depletion type or enhancement type decoding are connected in series, and an N channel MOS transistor 56 for discharge control is inserted on the ground potential V _SS side of each series circuit 50. . Here, the inversion signal ▲ ▼ of the precharge control signal φP is supplied in parallel to the gate of the discharge control transistor 56.

In the ROM having such a configuration, the output node 51 is precharged to "1" level by the load circuit 54 during the precharge period. After this, the precharge period ends, and the inversion signal ▲ ▼ of the signal φP is set to the “1” level and the discharge control transistor 56 is in the conductive state. Five
0 is selected, and the level of output data out is determined according to the state of the selected series circuit.

In this ROM, the load circuit 54 causes an output node 51
Since the discharge control transistor 56 is always in the non-conducting state during the precharge period in which the signal is precharged to the "1" level, the shoot-through current as in the case of FIG. 5 does not occur. However, in the case of a large capacity memory, the power required to drive the gate of the discharge control transistor 56 is considerably large,
There is a possibility that the effect of reducing the power consumption achieved by preventing the generation of the through current may be canceled.

Further, in this ROM, in order to select one from the m series circuits 50, 2m MOS transistors 55 for decoding are required in each series circuit. Therefore, the number of elements is larger than that of the ROM of FIG. 5, and there is a drawback that the chip size becomes large when integrated into a circuit. Also, the series circuit 50
Since many transistors are connected in series inside, the sum of resistance components due to the transistors becomes large, and the speed at which the output node 51 is discharged to the "0" level becomes slow and the operation speed also decreases. is there.

(Problems to be Solved by the Invention) As described above, the conventional semiconductor memory device has problems such as high power consumption, a large number of elements, and a low operation speed.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor memory device which consumes less power, has a relatively small number of elements, and has a high operating speed.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor memory device of the present invention includes a first node for outputting read data, a first power supply, and the first node. It is configured by arranging a precharge means for precharging the first node in a precharge period based on the inserted logic signal for precharge and an enhancement type or depletion type transistor based on data to be stored and connecting these in series. A plurality of data storage means each gate of which is driven by each bit signal of an address signal and one end of which is commonly connected to a second power source; a second node coupled to the first node; Based on a control signal inserted between each of the other ends of the data storage means and the second node to select the plurality of data storage means. A plurality of data storage means selecting transistors whose conduction is controlled in a period other than the precharge period, one end of which is connected to the second node and which is gate-controlled by the precharge logic signal and connected to the precharge period. A P-channel first MOS transistor which is gate-controlled by the logic signal for precharging and is conductive during the precharge period, and one end of which is connected to the other end of the first MOS transistor and the other end of which is the first power supply Second MO of N-channel connected to and gated by select signal
It is composed of an S-transistor.

(Operation) In the semiconductor memory device of the present invention, the precharge means is inserted between the first power supply and the first node, and the precharge means precharges the first node during the precharge period. , An enhancement-type or depletion-type transistor is arranged based on the data to be stored, these are connected in series to form a plurality of data storage means, and one end of each of the plurality of data storage means is commonly connected to a second power source, Inserting a data storage means selection transistor between each of the other ends of the plurality of data storage means and the second node, and controlling conduction of these transistors based on a control signal during a period other than the precharge period. The data storage means is selected by the above-mentioned method, and the capacitance division that occurs when the data storage means selection transistor becomes conductive is performed. The potential drop at the second node is compensated by the coupling between the gate and drain of the P-channel MOS transistor.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an ion implantation mask type according to an embodiment of the present invention.
It is a circuit diagram which shows the structure of NAND-ROM. This ROM has (n + 1) (n = 8 in this embodiment) N channels each.
The configuration is based on m series circuits 10 in which MOS transistors are connected in series. Each of these series circuits 10 is provided on the side close to the node 11 (second node) and is output from a decoder circuit (not shown) to select signals Bi (i = 1 to 1) for selecting each series circuit 10. m, shown in FIG. 5) and an AND signal Ai of the inverted signal ▲ ▼ of the precharge control signal φP, and a selection transistor 12;
Eight types of word line signals (row address signals) R1 to R8
8 memory cell transistors whose gates are supplied to
It is composed of 13 and. One end of each series circuit 10 is commonly connected to the ground potential V _SS , and the other end, that is, the drain of the selection transistor 12 is commonly connected to the node 11.

Each of the above eight memory cell transistors 13 constitutes a data storage means, and is initially formed as an enhancement type transistor in the manufacturing process.
After that, impurities are ion-implanted into an arbitrary channel region by ion implantation using an ion implantation mask designed according to the data to be stored, and the depletion type is changed.

In addition, the high-potential power supply V _DD and the node 14 (first node,
Between the bit line) and a load circuit for precharging the node 14 based on the precharge control signal φP.
15 has been inserted. The load circuit 15 has an N-channel MOS transistor 16 whose source and drain are inserted between the power supply V _DD and the node 14 and whose gate is supplied with a precharge control signal φP, and which inverts the precharge control signal φP. Inverter 17 that outputs a signal
The drain is inserted between the power supply V _DD and the node 14 and the signal output from the inverter 17 is applied to the gate.
And a P-channel MOS transistor 18 supplied with.

Further, a charge share compensation circuit 20 is inserted between the nodes 11 and 14. This charge share compensation circuit 20 has an N-channel MO whose drain is connected to the power supply V _DD and whose column is supplied with the column selection signal Cj (j = 1 to 1).
S-transistor 21, a P-channel MOS transistor 22 having a source and a drain inserted between the source of the transistor 21 and the node 11, and a source and a drain inserted between the nodes 11 and 14 and the column at the gate. Selection signal
It is composed of an N-channel MOS transistor 23 to which Cj is supplied. The signal φP is supplied to the gate of the transistor 22 via the inverter 24.

 Next, the operation of the ROM as described above will be described.

First, when the signal φP rises to “1” level at a certain time, the N-channel MOS transistor 1 in the load circuit 15 is
The 6 and P-channel MOS transistor 17 are both rendered conductive and the node 14 is precharged to the V _DD level.

When the signal φP rises to "1" level, the output of the inverter 24 falls to "0" level, and the P-channel MOS transistor 22 in the charge share compensation circuit 20 whose gate is supplied with the output of the inverter 24 also becomes conductive. Here, if the column selection signal Ci is set to the "1" level in advance, the N-channel MOS transistors 21 and 2 in the charge share compensation circuit 20 will be described.
Since node 3 is in the conductive state, the node 11 is connected to the power source V _DD through the N-channel MOS transistor 21 and the P-channel MOS transistor 22 in the charge share compensation circuit 20 in series, or the N node in the charge share compensation circuit 20. By the potential of the node 14 via the channel MOS transistor 23, V
It is charged to the potential of _DD- VTN (where VTN is the threshold voltage of the N-channel MOS transistor in which the back gate bias effect is added). That is, the potential of the node 11 rises only up to V _DD −VTN when the power supply voltage is V _DD .

Also, during this precharge period, the decode and word line signals R1 to Bm for forming the selection signals B1 to Bm are formed.
Level setting for each R8 starts. Therefore, after this, the memory cell MOS transistor 13 in each series circuit 10
Are controlled in accordance with the word line signal Rk (k = 1, 2, ... 8). Here, during this precharge period,
Is 0 level, all signals Ai are 0 level,
Each transistor 12 is non-conductive, so all series circuits
10 is not selected. Therefore, during the precharge period, V _DD
There is no shoot-through current between V _SS and V _SS .

Next, when the signal φP falls to the “0” level and the precharge period ends, the precharge operation of the node 14 by the load circuit 15 ends. When the precharge ends ▲
▼ becomes “1” level. Therefore, only the transistor 12 to which the product signal Ai of the signal which has been previously set to the "1" level and the signal {circle around (1)} among the selection signal Bi is supplied, and one series circuit 10 is selected. If the memory cell MOS transistor 13 to which the activated word line signal Rk is supplied among all the memory cell MOS transistors 13 in the selected series circuit 10 is a depletion type, Since the depletion type MOS transistor is conducting, the nodes 11 and 14 are discharged through the series circuit 10, and the output data out drops to "0" level. On the other hand, the memory cell MO to which the activated word line signal Pk in the selected series circuit 10 is supplied.
If the S-transistor 13 is of the enhancement type, the enhancement-type MOS transistor becomes non-conductive, the nodes 11 and 14 are not discharged through the series circuit 10, and the output data out remains at "1" level. .

By the way, when the transistor 12 becomes conductive, if the charge share compensation circuit 20 is not provided, the "1"
The level potential may decrease. That is, since the transistors 12 in all the series circuits 10 are made non-conductive during the precharge period, the “1” level of the node 11 is held only by the parasitic capacitance (not shown) existing in this node. It has only been done. Next, when the transistor 12 is turned on, the charge previously stored in the parasitic capacitance of the node 11 is capacitively divided by the parasitic capacitance (not shown) existing at the series connection point of the transistors of the selected series circuit 10, As a result, the "1" level potential of the node 11 drops.

Since the charge share compensating circuit 20 is provided in the device of this embodiment, such a decrease in the "1" level potential of the node 11 is prevented. That is, when the transistor 12 becomes conductive, the precharge control signal φP falls to the "0" level. At this time, the output of the inverter 24 is inverted from the "0" level to the "1" level. Then, after this, the P-channel MOS transistor 22 in the charge share compensation circuit 20 becomes non-conductive and the charge share compensation circuit 20.
The charging of the node 11 by is finished. Here, when the transistor 22 becomes non-conductive, the signal at the gate of the transistor 22 is inverted from the “0” level to the “1” level, so that it exists between the gate and the drain of the transistor 22. The drain potential, that is, the potential of the node 11 rises due to the coupling due to the parasitic capacitance (not shown). Note that the rise value at this time is proportional to the gate width of the transistor 22. As the potential of node 11 rises,
The decrease in the "1" level potential of the node 11 due to the capacitance division is compensated. That is, the decrease of the "1" level potential of the node 11 is prevented.

Moreover, in the charge share compensation circuit 20 described above, the N-channel MOS transistor 21 is connected in series to the P-channel MOS transistor 22, and the transistor 21 is gate-controlled by the column selection signal Cj. As a result, the N-channel MOS transistor 21 conducts only in the selected column and becomes non-conductive in the non-selected column, so that the current flowing through the P-channel MOS transistor 22 for precharging the node 11 is selected. Generated only in the column, and the power consumption can be further reduced.

After the rise, if the potential of the node 11 becomes equal to or higher than the potential of the sum of the potential of the node 14 and the threshold voltage of the transistor 23, no current flows from the node 11 to the node 14 through the transistor 23. The potential of 11 never drops to that of node 14.

If the load circuit 15 does not include the N-channel MOS transistor 16, the potential of the node 14 rises by the P-channel MOS transistor 18 when the precharge period ends, as in the case of the charge share compensation circuit 20. I will end up. However, in this case, since the N-channel MOS transistor 16 is provided, the potential increase of the node 14 is coupled by the parasitic capacitance (not shown) existing between the gate and drain of the transistor 16. Canceled by. It should be noted that the load circuit 15 is used for P channel MO.
The reason why the S transistor 18 is used for precharging is to raise the potential of the node 14 to V _DD .

As described above, according to the ROM of the above embodiment, all the transistors 12 are turned off during the precharge period in which the load circuit 15 precharges the node 14, so that the conventional ROM shown in FIG. The through current that would occur is not generated. Also, the precharge period ends and the node
When reading data to 11, the gates of the transistors 12 in the selected one series circuit 10 may be driven. Therefore, the power consumption required to drive the gates of these transistors 12 is compared with that in the ROM of FIG. Can be drastically extinguished. As a result, the power consumption does not increase even if the capacity is increased, and the power consumption can be reduced as compared with the conventional case. Also, the number of elements in the series circuit only is the ROM of Fig. 5.
Compared with, the number of series circuits 10 increases by m, but
This can be significantly reduced compared to the ROM in the figure. Further, the operating speed, that is, the speed at which the node 11 is discharged to the “0” level is slower than that of the ROM of FIG. 5 by the amount of inserting the transistor 12, but as much as that of the ROM of FIG. The speed can be increased as compared with the case where the decoding transistors of are connected in series. Furthermore,
Insert transistor 12 into node 11
The provision of the charge share compensation circuit 20 also solves the drop in the level of the node 11 caused by selectively conducting 12 during periods other than precharging. Further, reduction of power consumption is also achieved by suppressing the maximum charge level of the node 11 to V _DD or less during the precharge period.

In such an ion implantation mask NAND-ROM, MOS for memory cells connected in series in the series circuit 10
It is known that a large number of transistors 13 slows down the operation speed. However, if the number of transistors in each series circuit 10 is increased, the total number of series circuits 10 is decreased, and the total area of the contact portion connecting each series circuit 10 and the node 11 is decreased. On the contrary, if the number of transistors in the series circuit 10 is reduced, the total number of series circuits 10 increases and the total area of the contact portion increases. Therefore, it is necessary to determine the number of transistors in each series circuit 10 so as to satisfy both the operating speed and the area. In the above embodiment, this number is set to 8,
It has been confirmed that both the operating speed and the area are sufficiently satisfied at this number.

FIG. 2 is a circuit diagram of another charge share compensating circuit considered in the middle of the present invention. The charge share compensation circuit in this case has an N-channel MOS transistor 31 having a source and a drain inserted between the power supply V _DD and the node 11 and having the gate supplied with the precharge control signal φP.
N-channel MO in which the source and drain are inserted between the nodes 11 and 14 and the column selection signal Cj is supplied to the gate.
It is composed of an S transistor 32. Then, the threshold voltage of the transistor 31 is set lower than that of the transistor 32, or the threshold voltages of both transistors 31 and 32 are set equal and the "1" level potential of the signal φP is lower than that of the signal Ci. Is set.

In the circuit having such a configuration, when the threshold voltage of the transistor 31 is set lower than that of the transistor 32, the transistor 31 is turned on and the node 11 is turned on during the precharge period in which the precharge control signal φP is set to the “1” level.
Is charged to V _DD -VTN31 (VTN31 is the threshold voltage of the transistor 31). However, this potential V _DD −VTN31 is
The potential is made higher than the potential V _DD -VTN32 (VTN32 is a threshold voltage of the transistor 31) of the node 11 which is charged through the transistor 32 when the transistor 31 is not provided. And
The charge share is compensated by this potential V _DD -VTN31, but V _DD -VTN31-ΔV> V _DD -VTN32 (however, VTN31 +
If the condition such as ΔV <VTN32) is satisfied, the potential drop of the node 11 does not occur. The same effect can be obtained by changing the gate bias voltage of the transistors 31 and 32 in this circuit.

FIG. 3 is a circuit diagram of another charge share compensating circuit considered in the middle of the present invention. In this case node 11
14 is short-circuited, and P is connected between this common node and the power supply V _DD.
The source and drain of the channel MOS transistor 41 are inserted, and the precharge control signal φP is supplied to the gate of the transistor 41 via the inverter 42. In this case, the load circuit 15 and the charge share compensation circuit 20
The function of is realized by one P-channel MOS transistor 41. That is, the node 11 (or 14) is precharged to the potential of the power supply V _DD via the transistor 41 during the precharge period. Then, at the timing when the precharge period ends, the output of the inverter 42 is inverted from the “0” level to the “1” level, whereby the parasitic capacitance existing between the gate and drain of the transistor 41 causes coupling to the node 11 (or The potential of 14) rises, and charge shear compensation is performed.

FIG. 4 is a circuit diagram of another charge share compensating circuit considered in the middle of the present invention. In this case, in the charge share compensation circuit 20, the N-channel MOS transistor 21 is removed from the circuit of the embodiment shown in FIG. 1, and the potential of the node 11 is V _DD by the transistor 22 during the precharge period.
Is different in that it is charged up to.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor memory device having low power consumption, a relatively small number of elements, and a high operating speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention,
2 to 4 are circuit diagrams each showing the configuration of another charge share compensating circuit considered in the course of the present invention, and FIGS. 5 and 6 are circuit diagrams of a conventional device, respectively. 10 ... Series circuit, 11 ... Node (second node), 12 ... Selection transistor, 13 ... Memory cell transistor, 14 ...
Node (first node), 15 ... Load circuit, 20 ... Charge share compensation circuit.

Claims (2)

(57) [Claims] 1. A first node for outputting read data, and a first node inserted between a first power source and the first node based on a logic signal for precharging. A precharge means for precharging the node and an enhancement type or depletion type transistor based on the data to be stored are arranged and connected in series. Each gate is driven by each bit signal of the address signal, and each end is driven by the second A plurality of data storage means commonly connected to a power source, a second node coupled to the first node, and a second node connected to each of the other ends of the plurality of data storage means and the second node, respectively. A plurality of data storages which are inserted and controlled in conduction during a period other than the precharge period based on a control signal for selecting the plurality of data storage means P and stage selection transistor, which is one end electrically connected to the precharge period is gated by the logic signal for precharging is connected to the second node
The first MOS transistor of the channel and one end of the first MOS transistor
And a second MOS transistor of N-channel, the other end of which is connected to the first power source and whose gate is controlled by a selection signal. 2. An N-channel third MOS transistor whose gate is controlled by the select signal is inserted between the first node and the second node. The semiconductor memory device according to 1.