KR100385463B1 - A word line control circuit of semiconductor memory device - Google Patents

Abstract

The wordline control circuit of the semiconductor memory device of the present invention employs a hierarchical negative voltage wordline driving scheme, and employs a triple-well structure with no N-well and P-well bias without additional channel implantation. Since the MOS transistor with high threshold voltage is applied by applying high voltage (VPP) and low voltage (VBB), respectively, the sub-threshold current flowing through the power supply voltage (VDD) terminal and the ground voltage (VSS) terminal Self-reverse biasing can be used to reduce the subthreshold current flowing through the high voltage (VPP) and low voltage (VBB) terminals.

Description

A word line control circuit of semiconductor memory device

The present invention relates to a word line control circuit of a semiconductor memory device, and more particularly, by using a hierarchical negative voltage word line driving method, using a triple-well structure to construct a circuit, and applying a self inversion biasing method. The present invention relates to a word line control circuit of a semiconductor memory device capable of reducing the subthreshold current.

As the semiconductor memory device is highly integrated, the semiconductor memory device is operated at a low voltage. The cell charge is reduced due to the low voltage operation, thereby reducing the refresh time.

To improve this, the refresh time is improved by using a shallow back bias voltage level.

However, this method lowers the threshold voltage of the cell transistor, causing a problem of increasing the subthreshold current in the turn-off state.

Therefore, a negative voltage wordline driver is used to improve this.

1 is a circuit diagram illustrating a negative voltage wordline driver according to the prior art.

As shown therein, a row decoder 1 for decoding a row address AXij and a word line driver 2 for driving a word line WL by a signal decoded in the row decoder 1 are included. It is composed.

Here, the word line driver 2 has the NMOS transistor NM1 for selectively transmitting the output signal DX of the row decoder 1 by applying the power supply voltage VDD to the gate, and the ground voltage VSS at the gate. Is applied to selectively transmit the output signal DX of the row decoder 1 to the PMOS transistor PM1 and the PMOS transistors PM2 and PM3 to which a high voltage VPP is applied to a source and the gates are connected to drains of each other. ) And the low voltage VBB is applied to the source, and the NMOS transistors NM2 and NM3 have gates connected to drains of each other. Here, the NMOS transistor NM1 and the PMOS transistor PM1 are constituted of a MOS transistor having a low threshold voltage.

The PMOS transistor PM3 is controlled according to the output signal DX of the row decoder 1 selectively transmitted by the NMOS transistor NM1 applied to the gate to drive the word line WL.

In the PMOS transistor PM2, the word line WL is connected to the gate to adjust the gate voltage of the PMOS transistor PM3 according to the level state of the word line WL. That is, when the level of the word line WL is high, the PMOS transistor PM2 is turned off, and the output signal DX of the low decoder 1 is at the low level. Thus, the PMOS transistor PM3 is turned on. If the word line WL is at a low level, the PMOS transistor PM2 is turned on to turn off the PMOS transistor PM3.

The NMOS transistor NM3 is controlled according to the output signal DX of the row decoder 1 selectively transmitted by the PMOS transistor PM1 applied to the gate to drive the word line WL.

In the NMOS transistor NM2, the word line WL is connected to the gate to adjust the gate voltage of the NMOS transistor NM3 according to the level state of the word line WL. That is, when the level of the word line WL is high, the NMOS transistor NM2 is turned on to turn off the NMOS transistor NM3. When the level of the word line WL is low, the NMOS transistor NM2 is turned on. ) Is turned off so that the output signal DX of the low decoder 1 is at a high level, so the NMOS transistor NM3 remains turned on.

Referring to the operation of the negative word line driver according to the prior art configured as described above are as follows.

First, when the word line WL is not selected, the output signal DX of the row decoder 1 is at a high level. Therefore, the NMOS transistor NM3 of the word line driver 2 is turned on. The voltage of the word line WL is set to the low level VBB.

Therefore, the voltage of the word line WL that is not selected because the PMOS transistor PM2 is turned off is maintained at the shallow back bias voltage VBB (about -0.5V in this case).

On the other hand, when the word line WL is selected, the output signal DX of the row decoder 1 is at a low level so that the NMOS transistor NM3 is turned off and the PMOS transistor PM3 is turned on so that the word The level of the line WL becomes the high level VPP.

Thus, the selected memory cell can be accessed.

Since the negative voltage wordline driver of the prior art wordline driving method does not have a hierarchical wordline structure, the wordline metal pitch is narrow, so that there is no process margin and the sublines generated by the wordline driver 2 at the standby time. Subthreshold currents are a problem that cannot be ignored as semiconductor memory devices are highly integrated.

An object of the present invention for solving such a problem is to secure the process margin and reduce the sub-threshold current by driving the word line driver using a hierarchical negative voltage word line driving method.

Another object of the present invention is to use a triple-well structure, the sub-threshold flowing to the power supply voltage (VDD) and the ground voltage (VSS) using the high voltage (VPP) and low voltage (VBB) as the N-well and P-well bias, respectively. Is to reduce the solder current.

Another object of the present invention is to reduce the subthreshold current flowing to the high voltage (VPP) and low voltage (VBB) terminal by configuring a word line driver by adopting a self-biasing scheme.

1 is a circuit diagram showing a negative voltage wordline driver of the prior art.

2 is a block diagram showing a preferred embodiment of a word line control circuit of a semiconductor memory device according to the present invention;

3 is a detailed circuit diagram illustrating a main row decoder in the block diagram of FIG.

4 is a detailed circuit diagram illustrating a sub word line driver in the block diagram of FIG.

FIG. 5 is a detailed circuit diagram illustrating a word line boosting signal generator in the block diagram of FIG. 2.

6 is a cross-sectional view illustrating a MOS transistor having a dual-threshold voltage in a triple-well structure in the circuit diagrams of FIGS. 3 and 5.

<Description of Symbols for Major Parts of Drawings>

10: main row decoder

21-24: Sub wordline driver

30: word line boosting signal generator

PM11-PM15, PM21, PM31-PM37: PMOS Transistor

NM11-NM16, NM21-NM22, NM31-NM39: NMOS Transistors

INV11-INV12, INV21-INV22: Inverter

A word line control circuit of a semiconductor memory device of the present invention for achieving the above object is a word line control circuit of a semiconductor memory device having a hierarchical word line, the first self to apply a high voltage higher than the power supply voltage as a back bias The first switching means is connected between the biasing means and the high voltage, and the second switching means is connected between the second self biasing means for applying a low voltage lower than the ground voltage as a back bias and the low voltage, and thus the input row address A main row decoder to decode the signal, a plurality of sub word line drivers to drive the sub word line by the signal decoded by the main row decoder, and first self biasing means to apply a high voltage higher than a power supply voltage with a back bias. A first switching means is connected between the high voltage and the high voltage, and the ground voltage A second switching means is connected between the second self biasing means for applying a lower voltage and the lower voltage, and the word line boosting signal for decoding the input upper row address and applying a word line boosting signal to the sub word line driver. Characterized in that it comprises a generating means.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating an embodiment of a word line control circuit of a semiconductor memory device having a hierarchical word line structure according to the present invention.

As shown in the drawing, the embodiment of the word line control circuit of the semiconductor memory device includes a main row decoder 10, four sub word line drivers 21-24, and a word line boosting signal generator 3. . Here, an example in which four sub word lines SWL0-SWL3 are driven by one main row decoder 10 will be described.

The main row decoder 10 is precharged by the row decoder precharge signal / XDP, and is enabled by the active signals ACT and / ACT to decode the row address AXij to decode the main word line driving signal (/). MWL), and the sub wordline drivers 21-24 are driven by the main wordline drive signal / MWL of the main row decoder 10 to provide the wordline boosting signals PX0-PX3 and / PX0- / PX3. Drive the sub word lines SWL0-SWL3, and the word line boosting signal generator 30 is enabled by the active signals ACT and / ACT to decode the upper row address AXmn to boost the word line. Output signals PX <0: 3> and / PX <0: 3>.

3 is a detailed circuit diagram of the main row decoder 10 in the block diagram of FIG. 2.

As shown therein, the main row decoder 10 is a negative voltage wordline driver, which is connected in series between the high voltage VPP and the ground voltage VSS higher than the power supply voltage VDD, and the high voltage VPP is applied to the bulk. NMOS transistors NM11-NM13 and PMOS transistors PM11 to which the PMOS transistor PM11 and the row address AXij, which are applied and controlled by the row decoder precharge signal / XDP, are respectively applied to the gates. And the inverter INV11 for inverting the voltage A of the common connected drain of the NMOS transistor NM11 and the inverted signal / ACT of the active signal ACT, which is a control signal for enabling the selected bank. PMOS transistor PM12 which is controlled to apply high voltage VPP to inverter INV11 and high voltage VPP is applied to bulk and controlled by output signal B of inverter INV11 to control PMOS transistor ( PM11) and NMOS transistor (NM1) PMOS transistor PM13 for latching voltage A of the common connected drain of 1), high voltage VPP is applied, inverter INV12 for inverting output signal B of inverter INV11, and bulk PMOS transistors PM14 and PM15 to which a high voltage VPP is applied, a source is connected to output terminals of the inverters INV11 and INV12, and a ground voltage VSS is applied to a gate, and a ground voltage to bulk. A low voltage VBB lower than VSS is applied, and an NMOS transistor NM14 and a source connected to a drain of each of the PMOS transistors PM14 and PM15 are connected to the drains of the PMOS transistors PM14 and PM15, respectively, and a source connected to the low voltage VBB. And an NMOS transistor NM15 and an NMOS transistor NM16 configured to selectively apply a low voltage VBB to a source of the NMOS transistor NM15 by controlling an active signal ACT applied to a gate thereof. PMOS transistors (PM15) and NMOS transistors The main word line driving signal / MWL is output from the common connected drain of the emitter NM14.

FIG. 4 is a detailed circuit diagram of the sub word line driver 21 in the block diagram of FIG. Here, since the configurations of the four sub word line drivers 21 to 24 are the same, the configuration of only one sub word line driver 21 will be described.

As shown therein, the sub word line driver 21 is connected in series between the word line boosting signal PX0 of the word line boosting signal generator 30 and the low voltage VBB, and the gate is commonly connected to the main word line. The PMOS transistor PM21 and the bulk to which the driving signal / MWL is applied and the drain connected in common are connected to the sub word line SWL0 to apply the high voltage VPP to the bulk driving the sub word line SWL0. The NMOS transistor NM21 to which the low voltage VBB is applied, the low voltage VBB to the bulk, and the inverted word line boosting signal / PX0 are applied to the gate to float the sub word line SWL. And an NMOS transistor NM22 for preventing the damage.

5 is a detailed circuit diagram of the word line boosting signal generator 30 in the block diagram of FIG. 2.

As illustrated, the word line boosting signal generator 30 may include a NAND gate ND1 for decoding the upper row address AXmn, and an inverter INV21 for inverting the output signal D of the NAND gate ND1. And an NMOS transistor NM31, which is controlled by the active signal ACT and selectively transmits the low voltage VBB, and which selectively controls the high voltage VPP, which is controlled by the inverted active signal / ACT. A MOS transistor PM31, a PMOS transistor PM32 to which a high voltage VPP is applied to a bulk, a gate is connected to a drain of each other, and a high voltage VPP is applied to a source, and a PMOS transistor PM31 to a source. The PMOS transistor PM33 to which the high voltage VPP selectively transferred by is applied, the low voltage VBB is applied to the bulk, the gate is connected to the drain of each other, and the low voltage VBB is applied to the source. NMOS transistor and NMOS on source The NMOS transistor NM33 to which the low voltage VBB selectively transmitted by the transistor NM31 is applied, the gate is connected in common, and the power supply voltage VDD is applied, and the drain is PMOS transistors PM32 and PM33, respectively. NMOS transistors NM34 and NM35 commonly connected to the drains of the NMOS transistors NM34 and NM35 and gates are commonly connected to the ground voltage VSS, and a PMOS transistor PM34 connected to the drains of the NMOS transistors NM33 and NM32 respectively. PM35 and the high voltage VPP and the NMOS transistor NM31 are connected in series, a high voltage VPP is applied to the bulk, and a gate is commonly connected between the PMOS transistor PM33 and the NMOS transistor NM35. PMOS transistor PM36 connected to the drain, NMOS36 NM36 having a power supply voltage VDD applied to the gate, and a low voltage VBB are applied to the bulk, and a gate is applied to the PMOS transistor PM35 and the NMOS transistor. The NMOS transistor NM36 connected to the common connected drain of NM32 and the gate are connected in common to the common connected drain of the PMOS transistor PM36 and the NMOS transistor 37, and a high voltage is applied to the bulk. It is connected between the NMOS transistor NM38 to which the low voltage VBB is applied to the MOS transistor PM37 and the bulk, the drain of the PMOS transistor PM37 and the drain of the NMOS transistor NM38, and the power supply voltage VDD to the gate. ) Is configured to include the applied NMOS transistor NM39.

Here, the common connected drains of the NMOS transistors NM34 and NM35 and the PMOS transistors PM34 and PM35 are connected to the output terminal of the NAND gate ND1 and the output terminal of the inverter INV21, respectively.

A common connected drain of the PMOS transistor PM37 and the NMOS transistor NM39 forms an output terminal to output the word line boosting signal PX <0: 3>, which is inverted using the inverter INV22. Output a line boosting signal (/ PX <0: 3>).

The operation in the standby mode of the word line control circuit of the semiconductor memory device of the present invention configured as described above is as follows. Here, only the standby mode state of the word line control circuit of the semiconductor memory device will be described. This is because the sub thrust current flows in the standby mode.

First, in the standby mode, the voltage of the sub word lines SWL0-SWL3 is set to the low voltage VBB which is a negative voltage.

In addition, since the low decoder precharge signal / XDP is at a low level in the standby mode, the signal A is a high voltage VPP, the output signal B of the inverter INV11 is a ground voltage VSS, The output signal C becomes the high voltage VPP and the voltage of the node N11 becomes the low voltage VBB. Therefore, the main word line driving signal / MWL becomes the high voltage VPP.

At this time, the sub-threshold current flows in the NMOS transistor NM15, the PMOS transistor (not shown) of the inverter INV11, and the NMOS transistor (not shown) of the inverter INV12, and self-inverted biasing (self). This subthreshold current can be reduced by using the reverse bias method. That is, the high voltage VPP is cut off in the standby mode by the PMOS transistor PM12 controlled by the inverted active signal / ACT, and the low voltage VBB is controlled by the active signal ACT. By NM16, it is possible to cut off in the standby mode to reduce the sub-threshold current flowing at the high voltage VPP and the low voltage VBB, respectively.

Since the active signal ACT is at the low level in the standby mode, the PMOS transistor PM12 and the NMOS transistor NM16 are turned off. Therefore, the sub-threshold current flowing in the high voltage VPP and the low voltage VBB in the main row decoder 10 repeatedly arranged is determined by the channel widths of the PMOS transistor PM12 and the NMOS transistor NM16. .

Further, an N-well of a PMOS transistor (not shown) of the inverter INV11 and a P-well of an NMOS transistor (not shown) of the inverter INV12 are shown in FIG. 6. As described above, since the PMOS transistor (not shown) of the inverter INV11 and the NMOS transistor (not shown) of the inverter INV12 are connected to the high voltage VPP and the low voltage VBB, respectively, the high threshold voltage is high. -Vt), the subthreshold current flowing through inverters INV11 and INV12 becomes negligibly small.

In addition, the PMOS transistors PM33 and PM37 of the word line boosting signal generator 30, NMOS 33 and NM36 of the word line boosting signal generator 30, and the PMOS transistors (not shown) of the inverter INV21 may be used. Threshold current flows.

Here, the sub-threshold current flowing through the PMOS transistor (not shown) of the inverter INV21 becomes negligibly small because it has a high threshold voltage by connecting the N-well to the high voltage VPP as shown in FIG. 6. do.

In the standby mode, the PMOS transistor PM31, which is controlled by the inverted active signal / ACT, is turned off in order to reduce the sub-threshold current flowing through the PMOS transistors PM33 and PM37, so that the high voltage VPP becomes PMOS. It is not applied to the transistors PM33 and PM37.

Similarly, in the standby mode, the NMOS transistor NM31, which is controlled by the active signal ACT, is turned off in order to reduce the sub-threshold current flowing through the NMOS transistors NM33 and NM36, so that the low voltage VBB becomes the NMOS transistor. Do not apply to (NM33, NM36).

As such, it is possible to reduce the sub-threshold current flowing through the main row decoder 10 and the word line boosting signal generator 30.

As described above, the word line control circuit of the semiconductor memory device according to the present invention uses a hierarchical word line structure to secure a process margin in the metal word line and to reduce the subthreshold current to hierarchical negative voltage words. Using high voltage (VPP) and low voltage (VBB) with N-well and P-well bias, respectively, using a line drive method and triple-well structure without additional channel implantation To reduce the current flowing through the power supply voltage (VDD) terminal and the ground voltage (VSS) terminal by using a MOS transistor having a high threshold voltage, and to the high voltage (VPP) terminal by using self-reverse biasing. And it can reduce the current flowing to the low voltage (VBB) terminal.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (4)

In a word line control circuit of a semiconductor memory device having a hierarchical word line, The first switching means is connected between the first self-biasing means and the high voltage is applied to the high voltage higher than the power supply voltage as the back bias, the second self-biasing means and the low voltage is applied to the low voltage lower than the ground voltage as the back bias A second switching means connected between the main row decoder to decode the input row address; A plurality of sub word line drivers for driving sub word lines by signals decoded by the main row decoder; A first switching means is connected between the first self biasing means to which the high voltage is applied as a back bias and the high voltage, and a second switching means between the second self biasing means and the low voltage to which the low voltage is applied as a back bias. And word line boosting signal generating means for decoding the input upper row address to apply a word line boosting signal to the sub word line driver. The method of claim 1, In standby mode, The first switching device blocks the high voltage from being applied to the back bias of the first self-biasing means, And the second switching means blocks the low voltage from being applied by the back bias of the second self-biasing means. The method of claim 1, And the switching element is controlled by a control signal for activating a selected bank. The method of claim 1, And the self-biasing means is formed in a triple well structure.